KR980011506A - Segmented EPROM arrays for high performance and methods for controlling them - Google Patents

Abstract

EPROM is a method of controlling a memory array and an array. The array is divided into array segments, each segment having an alternate bit and a source line. Each segment includes a column of several cells, each cell having a control gate coupled to a word line, a drain coupled to one of the bit lines, and a source coupled to a source line adjacent to the bit line. A pair of cells in a column has a common source connected to one of the source lines and a respective drain connected to two bit lines adjacent to the source line. The selected cell is read using a pair of segment selection transistors which selectively connect a positive voltage to the bit line connected to the drain of the selected cell and ground the source of the cell. The bit lines connected to the drains are selectively accessed and isolated and need not extend only to a single segment of the array. This greatly increases the speed of the memory read operation because it has a low capacitance bit line that can rapidly change states during consecutive read operations.

Description

Segmented EPROM arrays for high performance and methods for controlling them

Since this is a trivial issue, I did not include the contents of the text.

The present invention relates generally to non-volatile memories, and more particularly to EPROMs and memory control methods having erasable pyrometers or segmented arrays of memory cells to provide high performance.

The size of the EPROM has been reduced in order to increase the data storage capacity and increase the operation speed. Referring to the drawings, Figure 1 shows a conventional EPROM memory with control circuitry to be removed. An array with a capacity of 1 megabits consists of N-channel cells 10 of floating gate variation, with each cell having a channel region that mediates drain, source, drain and source, and a poly Silicon floating gates. The polysilicon control gate is laid over the floating gate and isolated from the floating gate. For clarity, the drain region of the disclosed N-channel cell 10 is the most positive of the drain / source region when the cell is read.

The floating gate cells 10 are arranged in columns 1024 and 1024 to form a 1-megabit array. As an example of the array, all the cells 10 have a source region connected in common to the circuits. All the cells 10 located in a particular row have a drain region connected to the common bit lines BL1-BL1024. The bit line may be performed by a metal bit line or a buried doped semiconductor line. All cells 10 located in a particular column have control gates connected to common word lines WL1-WL1024. The word line is performed by a doped polysilicon line.

The programming of the individual cells is accomplished by applying a relatively high positive voltage to the bit lines associated with the cells 10 to be programmed. Also, a positive voltage is applied to the word line associated with that cell to be programmed. The resulting electric field moves the electrons from the grounded source region to the positive drain region. Some of these accelerated electrons get enough energy to be deposited on the floating gate through the insulating oxide film that mediates the channel and the floating gate. This mechanism, sometimes referred to as hot electron injection, is placed on the negative charge on the floating gate where the cell's threshold voltage is increased compared to when the cell is in the erased state.

The reading of an individual cell is accomplished by applying a small positive voltage to the bit line associated with the cell to be read. Further, a positive voltage is applied to the word line coupled to the cell. When the read cell is in the erase state, the positive voltage applied to the word line exceeds the erase threshold voltage of the cell, so that the cell becomes conductive. The current flows from the bit line to the circuit common through the cell. A sense amplifier coupled to a bit line (not shown) senses current flow and indicates the erased state of the read cell. If the cell is already programmed, no current flows to indicate the programmed state of the cell to be read.

The cell 10 is removed by scanning the cell with ultraviolet light. Generally, an integrated circuit package comprising an array establishes a window through which light can pass. The light removes the charge present on the floating gate. No voltage is applied during U.V. removal.

The memory program and the memory erase operation require more time than the memory read operation. For this reason, the EPROM device mainly makes it possible as a reading device. That is, once the device is programmed, most of the next operations are read operations. The speed of the memory read operation therefore determines the overall speed of the EPROM for actual use.

One of the primary limitations on read speed is the inherent capacitance coupled to the memory bit line. Some of these capacitances are due to the coupling capacitance between the coupled bit line and the surrounding structure, and the remainder of the capacitance is due to the capacitance of the drain region of all the cells connected to the bit line. This capacity is very large in the example, and Figure 1 shows that the bit lines extend over the entire length of the array and are connected to each of the 1024 cells located in the combined array rows.

The delay associated with capacity worsens when the bit line has a large resistance. The resulting large RC time constant is very large to retard the speed of the memory read operation, especially when the bit line is formed of a doped semiconductor line that is diffused or implanted more than a metal line.

One approach to overcome this rate limitation is to use a memory cell that generates a large current at the time of reading. This large current reduces the time required to charge and discharge the bit line. However, large cell currents require large peripheral cells. Large peripheral cells reduce the number of cells that can be performed in an integrated memory device and cause the undesirable parasitic capacitance already discussed.

The effect of the bit line capacitance can be reduced by segmenting the bit line. By way of example, FIG. 2 shows a portion of a memory cell array of the prior art that utilizes segmentation techniques. Only one part of a single array row, i.e., a row connected to the bit line BLI, is shown. The array comprises segment 1 consisting of columns 1-32 of cells 10 and column 2 consisting of columns 33-64 of cells. Other segments may be added as needed, and the size of the segments may be increased to 64, 128, etc. in each segment. Also, the number of rows present in each segment may increase.

Each segment is coupled to a bit line BLI connected by a segment select transistor, where segment 1 is connected by transistor 12 and segment 2 is connected by transistor 14. By the read address, only one segment is selected one by one by the appropriate segment selection transistors SS1, SS2, and so on. Therefore, the total capacitance coupled to the bit line is substantially reduced. For example, when the segment 1 is selected, the selection transistor 12 is activated and the remaining selection transistors are kept off. Therefore, only the capacitance associated with the drain of cell 1-32 is charged and discharged during the read operation. The bit line BL1 still extends over the entire length of the array, but the capacitance due to the bit line only is much smaller than that associated with the drain region of the cell 10 of the unselected segment.

The prior art has reduced the area required for a memory array by alternating metal bit lines and diffused semiconductor bit lines. Since the metal bit line requires more area than the semiconductor bit line, if the metal and the semiconductor line are alternately used, the area of each cell can be greatly reduced. Such arrays are sometimes referred to as alternate metal virtual grounds or AMG arrays.

3 shows an AMG array of memory cells 10, which is an exemplary prior art. The array includes a plurality of segments including segment 1 comprising columns 1-64 and rows 1-6 of cells. The next segment is segment 2 and contains columns 65-128, and only one column is shown in the figure. In general, there may be additional segments within the AMG array.

Cells in a column are arranged in pairs, and each pair shares a common source region. For example, adjacent cells 10a and 10b are located in the column combined with the word line WL2 including the common n-type source region. The pair of cells 10E and 10F located in the column coupled with the word line WL3 are connected to the common N-type source connected to the common source region diffusion of the cells 10A and 10B by the buried N-type semiconductor bit line BLB Share area spread. Likewise, cells 10B and 10C in adjacent cell pairs have a common N-type drain region diffusion coupled to the common drain region of cells 10F and 10G by buried N-type semiconductor bit line BL2.

An alternate bit line including lines BL1, BL2, and BL3 is connected in parallel with a metal track (not shown), respectively, laid down. The metal tracks are connected to the bit lines buried by the contacts 16 located at the top and bottom of each segment.

Each segment of the conventional AMG array includes complementary segment selection signals SN, (SSN) which is controlled by a sense amplifier (not shown). The segment select signal is controlled by the address decoding circuit so that only one of the array segments is enabled during the read or write operation. When segment 1 is enabled, one selected signal S1, Is active and the other segment selection signals SN, ) Is inactive. The same segment select transistor is placed on both sides of each segment and is connected in parallel with the transistor located at the top of the array and has the same select signals SN, . The parallel arrangement of the segment selection transistors on both sides of the bit line reduces the effect of the bit line resistance by half.

The operation of the AMG array is described as an example. Cell 10B is assumed to be read. The control circuit (not shown) applies a positive voltage to the bit line BL2 by a load circuit (not shown). This voltage is directly applied to the drain region of the cell 10B. The control circuit also grounds the bit line BL1. The remaining bit lines BLN also maintain the same positive voltage as the bit line BL2. The segment selection signal ( ) Is active (high) and by definition S1 is inactive. Therefore, the segment selection transistor ( Is in the conductive state, and the transistor SS1 is in the off state. The conductive transistor SS1 is connected to the source region of the cell 10B to ground the bit line BL1. Further, the control circuit connects a positive voltage to the word line WL2.

Assuming that cell 10B is in an erased state, the above conditions place cell 10B in a conductive state. The current flows from the bit line BL2 to the bit line BLB through the cell and flows to the grounded bit line BL1 through the transistor SS1. The sense circuit senses the change in the voltage at the load connected to the bit line BL2 and senses the state of the cell 10B.

The word lines of the unselected array are all grounded and the cells of the unselected column are non-conductive irrespective of the programmed state. With respect to the cell 10A of the selected column, since both the drain and the source of the cell are at the ground potential, this cell is non-conductive. This also coincides the cells in the selected column to the left side of the selected cell 10A. Cell 10C is non-conductive because conductive transistor SS2 can cause the same positive voltage to the source and drain. As described above, in the cell 10D, the non-selected bit line BLN except the line BL1 is at the same positive potential as the bit line BL2, and the drain and source of the cell are connected to the right side of the cell 10D The same potential as the other cells in the column. Therefore, these non-selected cells are in a non-conductive state.

Programming of the selected cell 10B is accomplished by applying a positive voltage to the bit line BL2 and grounding the remaining bit line BLN through a high impedance load. A large positive voltage is applied to the selected word line WL2 and unselected word lines are grounded. Again, the selection signal, ST, is activated and S1 is inactive, so that the line BLB connected to the source of the cell 10B is at the ground potential and the drain connected to the bit line BL2 is at the positive potential. This combination of voltages programs the cell 10B. The cells in the non-selected columns are not programmed because all the unselected word lines are grounded. For the cell 10A in the selected column, no programming occurs because the source and the drain are on the same low potential. The cell 10C is not programmed because the drain and source of the cell are on the same high potential due to the conduction of the transistor SS2. Cell 10D is not programmed because it has a source of high potential and a drain grounded at high impedance.

One or more bit lines BLN are subjected to a high-level and low-level state cycle conversion when a continuous memory cell is read. The bit lines have a relatively low resistance due to the interconnected metal bit tracks that are connected in parallel but the bit lines extend over the entire length of the array and connect each of the array segments and the relatively high And capacitances. As described above, the AMG array rate decreases as the time required to perform the read operation is primarily a limiting factor in performing this type of full speed of the read memory.

AMG arrays can achieve high cell density, but there is a problem with speed due to the bit line capacitance already described. A memory array that provides the density of the AMG arrays and minimizes the speed of such arrays is highly desirable. The present invention aims at these. BRIEF DESCRIPTION OF THE DRAWINGS The advantages and other advantages of the present invention will become apparent in the following detailed description with reference to the drawings.

An EPROM memory system including an array of floating gate memory cells, selection means and control means is disclosed. The memory array includes a plurality of array segments, each segment including an alternate bit and a source line. Preferably, the bit line and the source line are parallel lines that perform the shape of the embedded semiconductor line, and the source line has the metal line that is laid in parallel.

Each array segment includes a plurality of columns, each column including a first memory cell having a word line and a control gate coupled to the word line. The first cell includes a drain connected to the first one of the bit lines, and a source connected to the first one of the source lines adjacent to the first bit line. Each column includes a second cell having a control gate connected to a word line, a source connected to the first source line, and a drain connected to the second bit line adjacent to the first source line. In general applications, the number of cells located in a row may be as many as 100 cells with the combined source / bit lines.

The selecting means of the memory system of the present invention is means for selectively connecting the first node to one of the first and second bit lines. The first node is electrically insulated from the first source line. Preferably, the selecting means serves as a pair of transistors, one common terminal being connected to the first node and each remaining terminal being connected to the first and second bit lines.

The control means of the memory system of the present invention is a means for reading and programming selected cells of the memory array. The reading means applies a positive voltage to the first node for the array circuit common and connects the first node to the selecting means to connect the bit line connected to the drain of the selected cell to provide the selected cell to dominate.

The memory system described above allows a bit line coupled to the common drain of a memory cell to be selectively isolated and accessed by the claimed selection means. Therefore, a bit line connected to the cell drain of the cell is unnecessary to extend across each segment of the array. The inherent low capacitance of such isolated bit lines allows for fast and continuous read operation, since it is the drain region of the cell that must be sharply converted between voltage states during consecutive memory read operations.

Figure 1 is a diagram of a conventional memory array.

Figure 2 is a partial diagram of a conventional segmented memory array.

Figure 3 is a diagram of a conventional alternate metal virtual ground (AMG) memory.

4 is a diagram of a memory array according to the present invention.

5 is a partial diagram of an alternative memory array according to the present invention showing a dual polysilicon segment select transistor.

6 is a schematic block diagram of a memory system that may be implemented by the present invention.

Referring to the drawings, Fig. 4 shows a memory array according to the present invention. The array of the present invention is a segmented array containing segment (1-N). Each segment includes a total of 64 columns of memory cells 10, which can be N channel cells of the same type used in conventional AMG arrays.

The cells 10 of the array of the present invention are arranged in rows and columns and each cell is located in a particular column having a control gate connected to a common word line. The cells in the column are arranged in pairs, and the N-type drain regions of the cell pairs are formed in common. For example, the cell pair 10A, 10B share a common drain region, such as a pair of cells 10E, 10F located in adjacent columns. The N-type drain region of a cell in a specific row is shared by a pair of cells 10A and 10B in one column and a buried N-type bit line such as a bit line BLB connected to a pair of cells 10E and 10F in an adjacent column Line. The bit line BLN is relatively short and extends only as long as one segment of the array.

The cells of adjacent cell pairs have a commonly formed source region. For example, cells 10B and 10C have common n-type source regions like cells 10F and 10G in adjacent columns. The source region of a cell located in a particular row forms a common source line (SLN) associated with the row and is connected to the source region of the cell in the same row by buried N-type diffusion. For example, the cells 10F and 10G have a common source region connected to the common source region of the cells 10B and 10C by the source line SL2.

Each segment N of the array is connected to segment select transistors SSN, ). The segment selection registers are arranged in pairs, and each pair has a common connection connected to the segment line AN. For example, the select transistor pair SSN, Have a common connection connected to the bit line segment line A1. And the pair of select transistors are connected between adjacent BLs. For example, the pair of transistors SS1, Are connected between the bit lines BLA and BLB. The segment selection transistors SSN and SSN are controlled by complementary segment selection signals SEGN and SEGN which are generated alternately in response to an address decoding circuit (not shown).

Each segment of the array preferably includes segment select transistors SSN ', SSN' located on both sides of the segment from the segment select transistors SSN, SSN, ). ≪ / RTI > The subset of select transistors is connected to the same set of segment select signals SEGN, ). The subset of select transistors are arranged in pairs with a common connection to a coupled segment AN ', each connected to a contact 16. For example, the transistors SS1 'and SS1' are connected to the segment line A1 '. Also, each pair of sub-sets of select transistors is connected to an adjacent bit line. The segment lines AN and AN 'have a metal line (not shown) laid between the adjacent contacts 16 so that all of the segment lines combined with a single row of the array are electrically connected together.

The source lines SLN of the array segments are connected to the respective source lines of the other segments of the array. For example, the source line SL1 of the segment 1 is connected to the source line SL1 of the segment N. [ There is a contact 16 for contacting a fast track (not shown) placed in parallel with a source line embedded in each source line for each segment of the array.

Each source line SLN has an associated source control transistor SCN connected between the line and the contact 16N. For example, the source line SL1 is terminated in the source control transistor SC1. The source control transistor is controlled by the signal SN. For example, the transistor SC1 is controlled by the signal Sl.

In operation, the selected cell 10 is programmed by all first inactivity of the segment selection signal SEGN in the segment where the selected cell is not located. Therefore, these non-selected segment selection transistors SSN become non-conductive. Next, the segment selection transistor connected to the bit line adapted to the cell to be programmed is turned on by the appropriate segment selection signal SEGT. For example, assuming cell 10B is programmed, signal SEG1 is active and signal SEGT is inactive. This conducts transistor SS2 and connects the drain of cell 10B to the drain of segment line A2.

Further, in order to program the cell 10B, the control circuit applies a positive voltage to the segment line A2. Therefore, the positive voltage is applied to the train of the cell 10B by the transistor SS2. Also, the preference S2 is activated and the source selection transistor SC2 is turned on. The terminal 16 is grounded and the source line SL2 connected to the source of the cell 10B is grounded, and the remaining source selection transistors are turned off. A high voltage is applied to the selected word line WL1 and the unselected word lines are grounded. Under elevated conditions, the cell 10B is programmed by thermionic injection. The programming current flows from line A2 through transistor SS2 and is grounded by transistor SC2 through the cell.

The cell 10 in the non-selected column is not programmed because the connected word line is grounded. Since the connected source selection transistor SC1 is turned off, the cell 10A is not programmed. Further, since the transistor SS2 is turned off, the cell 10C is not programmed because the cell does not have a high voltage applied to the drain.

The read operation is performed by applying a positive voltage to the segment line AN coupled to the cell to be read. For example, if cell 10B is to be read, a positive voltage is applied to line A2. Also, the signal SBG1 is activated so that the positive voltage is applied to the drain of the sensor 10B. The contact 16 is grounded by a control circuit. Further, the source of the cell 10B is connected to the ground by the operation of the signal S2 that conducts the transistor SC2. Finally, the positive voltage is applied to the selected word line WL1 and the unselected word lines are grounded.

The cell is erased in a conventional manner using U.V. light. When the U.V. erase is performed all the voltages are turned off.

Under the above-described conditions, the drain of the cell 10B is connected to the positive voltage and the source is grounded. When the cell 10 is in the erased state, the positive voltage on the word line WL2 sufficiently conducts the cell. A sense amplifier (not shown) connected to the line A2 senses the presence of a current to indicate the erased state of the cell 10B.

When a continuous memory read operation is performed, the selected bit line BL is switched between the ground and the positive voltage. However, the length of the bit line is limited to the selected segment, and the overall length of the array does not extend as in a conventional AMG array as shown in Fig. Therefore, the speed of consecutive memory read operations is not limited by long bit lines connected to a large number of cell drains.

The source line (SLN) of the array of the present invention extends over the entire length of the array. However, since these lines are at ground potential during subsequent read operations, the large capacitance coupled to the sine does not increase the speed of the memory operation. Conversely, the large capacitance of the source line acts to reduce line noise, thereby increasing the reliability of the operation. The source line that translates within a continuous memory program operation does not reduce the overall speed of the memory operation. Because, as already described, EPROM devices have a slow order of magnitude in program operation as compared to read operations, and are therefore primarily used for read applications.

As an alternative to programming, the functions of the drain and source regions of the cell are reversed. To match, the drain region of the N-channel memory cell 10 of the present invention is defined as the region of the cell connected to the largest positive voltage for cell read operations and the like, as previously described. Therefore, using an alternative programming method, the source of the cell to be programmed is connected to the positive voltage and the drain is grounded. For example, when the cell 10B is programmed, the line A2 is grounded and the selection transistor SS2 is conducted by the signal SEG1. In addition, the source of cell 10B is connected to a positive voltage by connecting a voltage to contact 16B and turning on transistor SC2.

If the first described programming method is used, the selection transistor SLN is preferably a single poly MOS transistor such as the source selection transistor SCN shown in Fig. A double poly transistor that is erased in a low threshold voltage state such as a transistor used in the memory cell 10 is not used. This is because a relatively large programming voltage applied to the dual polyselect transistor tends to program the transistor to an undesirably high threshold voltage. However, in alternative programming methods, the selection transistor SSN need not challenge a large programming voltage. Therefore, the select transistor SSN may be a single poly transistor as shown in Fig. 4 or a double poly transistor that is erased in a low limit voltage state as shown in Fig. In the case of using the double poly transistor selection transistor SSN, the manufacturing method can be simplified by disposing the single polysource selection transistor SCN outside the memory array. In this case, the single poly device does not need to be located in the memory.

Figure 5 is a schematic block diagram of an overall memory system. The system includes a memory array 20 that includes various array segments. The circuit for decoding address for memory read and program operation includes a row decoder 22. [ The row decoder 22 is composed of a segment selection transistor SSN and a source control transistor SCN having a program and an appropriate voltage to be applied to the source and bit lines during a read operation. The exact magnitude of these voltages depends on the characteristics of the particular memory cell 10 being used and is the same as that used in conventional AMG arrays.

The system also includes a column decoder 24 for decoding addresses for memory read and program operation with appropriate voltages to be applied to the word lines during read and program operations. Again, the voltage magnitude depends on the characteristics of the particular cell 10 being used. The column and row decoders 22 and 24 receive the appropriate control signals SEGN, , SN) and a control circuit block 26 which generates associated signals that perform read and program operations. The particular implementation of row and column decoders and control circuits is obvious to those skilled in the art and does not form part of the present invention. Therefore, such practice is not disclosed in order to avoid obscuring the nature of the present invention.

Another advantage of the disclosed memory array is that techniques combined with conventional AMG arrays, such as memory cell 10 structures, are used. In addition, the disclosed other metal bit line technology is very similar to a conventional AMG array, and the same layout can be used. For this reason, it is not necessary to describe the actual physical layout of the disclosed technique or the peripheral control circuit that generates and applies a suitable voltage for programming and reading the cell to implement the present invention. These details are known to those skilled in the art and are similar to conventional AMG devices. Further, the production of the present invention has not been described. This is because the manufacturing method for carrying out the present invention is conventional and not a part of the present invention.

Therefore, a novel EPROM array has been disclosed. Although the preferred embodiments have been described in detail, various changes may be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (25)

Each cell comprising a source, a drain, a channel arranged to mediate between the source and the drain, a floating gate folded from the channel, and a control gate insulated from the floating gate, wherein the array comprises two or more array segments Each array segment having columns and rows of a plurality of memory cells, cells in one column having control gates connected to a common word line and arranged in a pair of cells, cells in one pair being connected to a common source line A group of memory cells having a common source line and a bit line, a group of select transistors coupled with respective array segments, each of the select transistors having a drain connected to a separate bit line, 1, a second terminal and a gate, wherein one of the selection transistors is arranged in pairs Each pair comprising a common first terminal and a respective second terminal coupled to a bit line adjacent to the pair of memory cells, and a common first terminal electrically coupled to the bit line adjacent to the common bit line, A control transistor for programming and reading a selected cell of the memory array and a group of isolated selection transistors and a selection transistor coupled to the bit line coupled to the selected cell to apply a positive voltage And reading means for reading the selected cell by applying the selected cell. 2. The semiconductor memory device according to claim 1, wherein each pair of the selection transistors includes first and second selection transistors, the gates of the first selection transistors of each pair are connected to a common first selection line, And a gate coupled to a common second select line that is separate from the first select line. 3. The display device according to claim 2, wherein the reading means generates a first selection signal and a second selection signal which are complementary to the first selection signal, wherein the first selection signal is applied to the first selection line and the second selection signal is read And a second select line coupled to an array segment in which the cell is located. 4. The EPROM memory system of claim 3, wherein the bit lines of one array segment are electrically isolated from the bit lines of the other array segments. 5. The EPROM memory system of claim 4, wherein the source lines of one array segment coupled to a pair of specific pairs are connected to a source line of another array segment coupled to the same specific pair and row. 6. The EPROM memory system of claim 5, wherein the source line comprises a buried semiconductor line extending across all segments of the array. The EPROM memory system according to claim 6, wherein the metal source line is connected in parallel with the embedded source line. 8. The EPROM memory system of claim 7, wherein each bit line comprises an embedded semiconductor line. 6. The EPROM memory system according to claim 5, wherein said reading means comprises means for grounding a source line connected to a selected cell for an array circuit common. 10. The EPROM memory system of claim 9, wherein the reading means performs the function of applying a positive voltage to a first terminal of a used selection transistor and applying a selected voltage to a drain of a selected cell by making the selected selection transistor conductive. 11. The EPROM memory system of claim 10, wherein the control means further comprises a separate source transistor coupled to a source line of the array such that the source line is selectively controllable using a source transistor. 12. The EPROM memory system according to claim 11, wherein the reading means performs a function of grounding the source line coupled to the selected cell to the circuit common. 13. The EPROM memory system of claim 12, wherein said programming means performs a function of applying a positive voltage to a source line associated with a selected cell to be programmed for a drain of a selected cell to be programmed. 14. The EPROM memory system of claim 13, wherein said programming means performs the function of applying a positive voltage by means of a source line transistor coupled to a selected cell to be programmed. 13. The EPROM memory system of claim 12, wherein said programming means performs the function of applying a positive voltage to a bit line coupled to a selected cell to be programmed. 16. The EPROM memory system of claim 15, wherein said programming means performs the function of grounding a source line of a selected cell to be programmed for an array circuit common. Each segment including a replacement bit, a source line, and a plurality of columns of floating gate memory cells, each column comprising a word line, a first cell having a control gate coupled to the word line, A source connected to the source line adjacent to the first bit line, a second cell having a control gate connected to the word line, a source connected to the source line, and a second bit line connected to the first source line adjacent to the first source line Selection means for coupling a first node to a selected one of the first and second bit lines, wherein the first node comprises selection means electrically isolated from the source line, and selection means for selecting a selected cell of the memory array As a control means for programming and reading, a positive voltage is applied to the first node It was added EPROM memory system provided with a control means comprising a reading means for reading a selected cell by connecting the bit line connected to the selecting means to a first node, the drain of the selected cell. 18. The memory cell of claim 17, further comprising a third bit line and a second source line for mediating a third bit line, a second bit line, a third memory cell and a fourth memory cell, A drain connected to the second bit line, and a source connected to the second source, the fourth cell having a control gate connected to the word line of the column in which the first task 2 cell is located, a control gate connected to the word line of the second source A source coupled to the first bit line, and a drain coupled to the third bit line. 19. The EPROM memory system of claim 18 wherein the bit lines of one array segment are electrically isolated from the bit lines of the remaining segments. 20. The EPROM memory system of claim 19, wherein the source lines of each segment of the array coupled to a particular one of the array rows are connected in common. 21. The EPROM memory system of claim 20, wherein the bit line is a buried semiconductor bit line. 1. A memory array comprising a plurality of array segments, each segment including a replacement bit, a source line, and a plurality of columns of floating gate memory cells, each column comprising a first cell having a control gate connected to a word line, A source connected to the source line adjacent to the first bit line, a second cell having a control gate connected to the word line, a source connected to the source line, and a second bit line adjacent to the first source line, Selecting means for connecting the first node to the first and second bit lines; source line control means for controlling the state of the source line independently of the selecting means; and programming the selected cell of the memory array A positive voltage is applied to the first node and a second voltage is applied to the first node The EPROM memory system provided with a control means comprising a reading means for reading a selected cell by connecting the bit line to the drain of the selected cell connected to the selection means. 23. The method of claim 22, wherein the selecting means comprises a first transistor and a second transistor, each having a first and second terminal and a gate, the first transistor having a first terminal coupled to the first node and a first terminal coupled to the first node, The second transistor having a first terminal coupled to the first node and a second terminal coupled to the second transistor and the second bit line. 24. The EPROM memory system of claim 23, wherein said source line control means comprises a third transistor having a first and a second terminal and a gate, said first terminal being connected to a source line. CLAIMS 1. A method of controlling a memory array comprising a plurality of array segments, each segment including a replacement bit, a source line, and a plurality of columns of floating gate memory cells, each column comprising a word line, a control gate coupled to the word line, A first cell having a first cell, a drain connected to a first one of the bit lines, a source connected to a source line adjacent to the first bit line, a second cell having a control gate connected to a word line, a source connected to the source line, Wherein the first and second bit lines of one second mantle are electrically insulated from the other first and second bit lines of the segment and are connected to the source line of all the segments A method of controlling a commonly connected memory array includes the steps of: applying a positive voltage Programming a selected one of the cells including applying a voltage, applying a voltage to a bit line coupled to a drain of the selected cell, and applying a voltage to a word line coupled to a control gate of the selected cell Reading a selected one of the cells, wherein the applied voltage is positive for a source of a selected cell. ※ Note: It is disclosed by the contents of the first application.