RU2006924C1 - Device for information input-output - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has data segment decoder, two permission flip-flops, readiness flip-flop, AND gate, address determination unit, read-only memory unit, which group of information outputs is connected to group of information outputs of data segment decoder and to group of parallel data inputs of address determination unit. EFFECT: increased reliability of information protection from unauthorized access. 2 dwg

Description

 The invention relates to computer technology, in particular to systems for input-output of information in computers, and can be used in systems for transmitting information from a source to a receiver.

 A device for input / output of information containing a data storage latch, a six-bit input of which is a key input for connecting to a group of computer information outputs, three six-bit counters, three adjusters of the initial settings of counters, four selectors, four adjusters of the initial state of selectors, the And element OR, the output of which is the output of the key confirmation signal for connecting to the computer information input [1].

 The disadvantage of this device is the low reliability of information protection from unauthorized access, which is due, firstly, to the high probability of disclosing the initial settings of the counters (the total number of possible combinations of settings is 25147); secondly, the lack of additional non-volatile memory, which can accommodate various passwords and encryption keys available for computer reading programs.

 The closest in technical essence and the achieved effect to the proposed device is a device for interfacing a source and receiver of information, containing a memory unit, the information input and output of which are the corresponding input and output of the device for connecting to the information output of the information source and the information input of the information receiver, trigger, the inverse and direct outputs of which are the corresponding outputs of the device for connecting to the recording permission input of the information source and to the read permission input of the information receiver, the counter, the zeroing output, and the information output of which are connected respectively to the trigger reset input and the memory block address input, the synchronization input of which is connected via the delay element to the OR element output, the memory block operating mode input is connected to the trigger inverse output , the first and second inputs of the OR element are respectively the inputs of the device for connecting to the output of the clock of the source record and the output of the clock of the reading of the information receiver, d message end code encoder, the information input of which is connected to the input device for connecting the information output of the information source, and the output is connected to the installation input of the trigger, the synchronization end of the message end code decoder is connected to the input for connecting the synchronization output of the information source record and the counter input counter, subtracting the input which is connected to the input of the device for connecting the output of the clock pulses of the reading of the information receiver, the information output of the counter is connected to the output of the device wa for connecting to the indicator input information receiver [2].

The disadvantage of this device is the low reliability of information protection from unauthorized access, which is due, firstly, to a high probability of disclosing a message code transmitted from an information source (computer) to the information input of a message code decoder, since the total number of possible message code combinations to gain access to the prototype memory block is limited by the bit depth of the prototype information input and does not exceed 2 ⁿ , where n is the bit width of the information bus of the information source, secondly ryh, the probability of disclosing the initial installation of the address counter is close to one, which facilitates the process of unauthorized access to the contents (passwords) of the memory block in read mode (in the initial state, the information outputs of the address counter can be either all logical "0" or all logical "1").

 The aim of the invention is to increase the reliability of information protection from unauthorized access.

 This goal is achieved by the fact that in the device for input-output of information containing a decoder of the data code, the group of information inputs of which is the data input of the device for connecting to the data bus of the microcomputer, the address generation unit, the permanent memory unit, the group of address inputs of which are connected to the group of information the outputs of the address generation unit, and the group of information outputs is the data output of the device for connecting to the data bus of the subscriber, a readiness trigger, the output of which is connected to the input m of the mode of the address generation block is the output of the read permission of the device, the first and second triggers of resolution are entered, the And element, the first input of which is connected to the read permission input of the read-only memory block and is the read input of the device for connecting to the microcomputer read output, the reset inputs of the first and second permission triggers and readiness triggers are connected and are the reset input of the device for connecting to the microcomputer reset output, data reset inputs of the first and second permission triggers and the availability trigger These are connected and are the recording input of the device for connecting to the recording output of the microcomputer, the output of the first enable trigger is connected to the first information input of the data code decoder and to the second input of the I element, the output of which is connected to the data strobe input of the address generation unit, the group of parallel data inputs of which are connected with a group of information inputs of a data code decoder and with a group of information outputs of a read-only memory block, the output of the second resolution trigger is connected to the second information input a data code decoder, the first, second and third outputs of which are connected to the data inputs of the first and second enable and ready triggers, respectively, while the address generation unit contains two counters, the group of parallel data inputs of which are a group of parallel data inputs of the address generation unit, information group the outputs of the first and second counters are a group of information outputs of the address generation unit, the inputs of the data strobe of the first and second counters are connected and are the input ohm of the data gate of the address generation unit, the account resolution input and the first counter mode input are connected to the second counter mode input and are the address formation mode mode input, the information output of the first counter is connected to the account resolution input of the second counter.

 In FIG. 1 shows a block diagram of a device for input-output information; in FIG. 2 is a diagram of an address generating unit.

 The device contains a data code decoder 1, first and second triggers 2, 3 permissions, ready trigger 4, element 5, address generation unit 6, read-only memory unit 7, data input 8, input 9, input 10, reset and input 11 read devices for connecting, respectively, to the data bus, recording, reset and reading outputs of the microcomputer 12, the group of information outputs 13 of block 7, which is the data output of the device for connecting to the data bus of the subscriber, input 14 of the data strobe, input 15 of block 6 mode, which is the output of the read permission of the device group information outputs 16 block 6.

 Block 6 formation of the address (see Fig. 2) contains the first and second counters 17, 18.

 The decoder 1 of the data code is designed to generate a logical "0" signal at one of its information outputs when it comes to the information inputs 8 of the decoder 1 of the corresponding code set of logical zeros and ones from the data bus of the microcomputer 12.

 Triggers 2, 3, 4 are used to record information from the outputs of the decoder 1 when entering the input 9 of the recording device of the data strobe from the output of the microcomputer record 12, element I 5 is used to form the data strobe when the reading signal of the reading device comes from the reading output of the microcomputer reading 12, block 6 - for generating the address of the permanent memory cell of block 7, block 7 of permanent memory - for storing and displaying overhead information (passwords, encryption keys).

 The device operates as follows.

 In the initial state, triggers 2, 3, 4 are reset, at the outputs of the decoder 1 and triggers 2, 3, 4 there are logical “1” signals, the address generation unit 6 is switched to parallel data loading mode.

 At an arbitrary point in time, the microcomputer 12 sets the first data word on the data bus 8 and accompanies it with a recording strobe at input 9, as a result of which a logical “0” is generated at the first information output of the decoder 1, which is written into the first permission trigger 2 by the data strobe. At the output of trigger 2, a logical "0" is generated, which is fed to the first information input of decoder 1, preparing it for recognition of the next data word from microcomputer 12.

 At the same time, the logic signal “0” from the output of trigger 2 enters through the And element 5 to the input 14 of the data strobe of the data generating unit 6 and prepares it for receiving the data word from the data bus 8. Then, the microcomputer 12 sets the second data word on the data bus 8 and accompanies it recording gate by input 9. At the same time, logical 1 is present at the first and third information outputs of decoder 1, a logical “0” is generated at the second information output of decoder 1, which are recorded in triggers 2, 3, 4 by the data gate at input 9. 2, a logical “1” signal is generated (a positive edge, which is transmitted through input 5 to the input 14 of the data strobe of block 6, as a result of which the data word from the data bus 8 is written to its memory through the group of parallel inputs 13 of block 6 (counters 16, 17, Fig. 2) At the same time, logical “1” from the output of trigger 2 and logical “0” from the output of trigger 3 are fed to the first and second information inputs of decoder 1, preparing it for recognition of the next data word of microcomputer 12. After the microcomputer 12 exposes on the data bus and forms t recording gate at input 9, at the output of decoder 1, a logical “0” signal is generated, which is written to the readiness trigger 4 by the data gate. As a result of this, at the input 15 of the mode of block 6, a logical “0” signal will be set, which will transfer the address generation block 6 from the parallel loading mode to the operating mode (account resolution and prohibition of downloading parallel data of the counters 16, 17, Fig. 2).

 In the input-output mode of information, the microcomputer 12 performs the operation of reading data from block 6 by supplying read signals to the read input 11, while simultaneously outputting information to the subscriber. As a strobe of tracking data to the subscriber, a read signal at the input 11 of block 7 can be used. The reliability of the transmitted data to the subscriber is determined by the read permission signal at the output 15 of the device.

 In the process of reading information from block 7, the microcomputer sets up reading signals (logical "0") at the input 11 of the device, which are fed to the read permission input of block 7. At the same time, the data from the group of information outputs 13 of block 7 can be read by the microcomputer 12 and the subscriber. When a read signal is removed from input 11, a logical “1” signal is generated at the first input of AND element 5, as a result of which a data strobe (positive edge of the voltage drop) is formed at input 14 of the data gate of block 6, which changes the contents of block 6 (i.e. the contents of the counters 16, 17, Fig. 2) are changed. At the output 16 of block 6, the address of the next memory cell is formed for the next cycle of access to block 7.

 Thus, the device enters information into the microcomputer and displays information to the subscriber.

 Decoder 1 can be made on the basis of K555 ID7 chips. K573 RF2, triggers 2, 3, 4 - based on the K555 TM2, K555 TM8 microcircuits, the address generation unit - based on the K555 IE17, K555 IE16 microchip, the permanent memory unit 7 - on the K573 RF2 microcircuit, which is pre-programmed for a specific user application .

 The indicated operations of writing and reading data on the data bus 8 of the microcomputer 12 are carried out during one machine cycle of the microcomputer, based on the microprocessor KM 1810 VM86. The machine cycle of writing (reading) data to block 6 (from block 7) of the device is four clock pulses, the repetition rate of which is 5 MHz, and information can be written to block 6 by the positive difference of the write signal, and information from block 7 is read in the third cycle of the machine cycle. The activation of the write signals (input 9) and read (input 11) is carried out in the second cycle of the machine cycle. (56) Grinspan L.A. and Levin E.M. Electronic keys to protect information. - World of PC, 1991, N 4, p. 69-73, fig. 1.

 USSR author's certificate N 1661777, cl. G 06 F 13/00, 1990.

Claims (2)

 1. DEVICE FOR INFORMATION I / O, containing a data code decoder, the group of information inputs of which is a data input of the device for connecting to the microcomputer data bus, an address generation unit, a read-only memory unit, the address input group of which is connected to the information output group of the address generation unit, and the group of information outputs of the read-only memory block is the data output of the device for connecting to the subscriber data bus, a readiness trigger, the output of which is connected to the input of the block mode the formation of the address and is the output of the read permission of the device, characterized in that the first and second triggers of resolution are inserted into it, the And element, the first input of which is connected to the read permission input of the read-only memory block and is the read input of the device for connecting to the read output of the microcomputer, reset inputs the first and second enable triggers and the readiness trigger are combined and are the reset input of the device for connecting to the microcomputer reset output, the data strobe inputs of the first and second resolution triggers and three readiness headers are combined and are the input to the recording device for connecting to the output of the microcomputer record, the output of the first resolution trigger is connected to the first information input of the data code decoder and to the second input of the I element, the output of which is connected to the data gate input of the address generation unit, the group of parallel data inputs of which connected to a group of information inputs of a data code decoder and to a group of information outputs of a read-only memory block, the output of the second permission trigger is connected to the second inform the corresponding input of the data code decoder, the first, second, and third outputs of which are connected to the data inputs of the first and second enable and ready triggers, respectively.  2. The device according to claim 1, characterized in that the address generating unit contains two counters, the group of parallel data inputs of which is a group of parallel data inputs of the address generating unit, the group of information outputs of the first and second counters is a group of information outputs of the address generating unit, strobe inputs the data of the first and second counters are connected and are the input of the data strobe of the address generation unit, the account resolution input and the input of the first counter mode are connected to the input of the second counter mode They are the input of the mode of the address generation unit, the information output of the first counter is connected to the input of the account resolution of the second counter.

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