RU2168198C1 - Microcontroller network - Google Patents

Abstract

FIELD: automatics, computer engineering. SUBSTANCE: invention can be utilized while constructing distributed systems of program control over technological processes. Microcontroller network includes M*N identical modules integrated in matrix structure. Each module has program storage, address register, command register, multiplexer of logic conditions, address switch, synchronization unit, three OR gates, unit of NOT gates, register of vector of correspondence, buffer register, first and second decoders of number of synchronization vertex, first and second groups of AND gates, group of OR gates, unit of OR gates, first and second univibrators, delay element. EFFECT: expanded application field of microcontroller network, enhanced timeliness of intermodule transfer of control. 1 cl, 7 dwg

Description

 The invention relates to automation and computer technology and can find application in the construction of distributed software control systems for technological processes, robots and robotic complexes, as well as logical control subsystems of multi-level hierarchical ACS and multiprocessor systems of a wide class.

 A well-known distributed system for technological process control containing M • N channels (modules), each of which includes a program memory block, an address switch, address and instruction registers, a logic condition multiplexer, synchronization and analysis blocks, a buffer memory block, two blocks of elements And the element And (A.S. 1605212 CCCP, G 05 B 19/18; publ. 07.11.90, BI N 41).

 The disadvantage of this system is the narrow scope associated with the lack of synchronization tools for groups of parallel sections of programs assigned to various modules. The lack of synchronization tools in many cases is unacceptable, since it makes it possible to simultaneously execute incompatible commands (sections).

 The closest to the proposed network in technical essence is a discrete microcontroller network containing M • N modules of the same type combined into a matrix structure, where N is the number of modules in a row of the matrix network structure, M is the number of lines, each module of which includes a program memory block, a block analysis, address counter-register, instruction register, address switch, logical conditions multiplexer, synchronization block, parallel section synchronization control block, trigger, from the first to fourth blocks of AND elements, from the left the seventh elements AND, from the first to the third elements OR (patent 2110827 RF, G 05 B 19/18, G 06 F 9/28; publ. 10.05.98, BI N 13).

 A disadvantage of the known network is the low efficiency of inter-module control transfer when starting groups of parallel sections of (micro) programs (control algorithms) assigned to various modules, due to the need for consistent pairwise inter-module exchange of special control teams. This drawback leads to a decrease in the overall speed of the network. Another drawback of this network is the significant complexity of its modules.

 The technical problem to which the invention is directed is to increase the efficiency of inter-module transfer of control in a microcontroller network when starting groups of parallel sections of programs based on the organization of parallel launch of modules implementing these sections, while simplifying network modules.

и ко второй группе входов синхронизации (M. j)-го модуля,

группа выходов синхронизации (α,β)-го модуля,

подключена к первой группе входов синхронизации (α.β+1)-го модуля и ко второй группе входов синхронизации (α-l.β)-го модуля, группа выходов синхронизации (l.β)-го модуля соединена с первой группой входов синхронизации (l.β+l)-го модуля, группа выходов синхронизации (α,N)-го модуля соединена со второй группой входов синхронизации (α-l.N)-го модуля.The technical problem is solved in that in a microcontroller network containing M • N of the same type of modules combined into a matrix structure, where N is the number of modules in a row of the matrix structure of the network, M is the number of rows, each module includes a program memory block, an address register, a command register, a logical condition multiplexer, an address switch, a synchronization unit, from the first to the third OR element, the input of the operation code of the module being connected to the first information input of the address switch, the output of which is connected to the information input p an address histogram, the output of which is connected to the address input of the program memory block, the output of which is connected to the information input of the command register, the output label of the end of the program of which is connected to the control inputs of the address switch, the outputs of the logical condition code and the modifiable bit of the address of the command register are connected to the control and the first information the inputs of the multiplexer of logical conditions, respectively, the second information input of which is connected to the input of the logical conditions of the module, the first input of the synchronization unit And it is connected to the start input of the module, an additional block of elements NOT is introduced, and each module additionally includes a register of the correspondence vector, a buffer register, the first and second decoders of the synchronization vertex number, the first and second groups of AND elements, the group of OR elements, the block of OR elements, the first and the second one-shot, delay element, and the output of the non-modifiable part of the address of the register of commands in combination with the output of the multiplexer of logical conditions are connected to the first input of the block of OR elements and to the information input buffer The black register, the output of which is connected to the second input of the OR block of elements, the output of which is connected to the second information input of the address switch, the output of the microoperations of the command register is connected to the output of the microoperations of the module, the input of the correspondence vector of the module is connected to the information input of the register of the correspondence vector, outputs from the first to n which (where n is the maximum number of synchronization vertices in the programs being implemented) are connected to the first inputs of the elements of the OR group from the first to the n-th, respectively, the first output of the vertex number Synchronization of the command register is connected to the input of the first decoder of the synchronization vertex number, the outputs from the first to the nth of which are connected to the second inputs of the elements of the OR group from the first to the nth, respectively, the outputs of which are connected to the first inputs of the elements of the first group from the first to n respectively, the inputs of the first group of synchronization inputs of the module from the first to the n-th are connected to the second inputs of the elements And of the first group from the first to the n-th respectively, the outputs of which are connected to the outputs of the group of synchronization outputs of the module with first on the n-th, respectively, the second output of the number of the synchronization vertex number of the command register is connected to the input of the second decoder of the synchronization vertex number, the first to nth outputs of which are connected to the first inputs of the elements And the second group from the first to the n-th respectively, the inputs of the second group the synchronization inputs of the module from the first to the n-th are connected to the third inputs of the elements And the first group from the first to the n-th, respectively, the outputs of which are connected to the second inputs of the elements And the second group from the first to the n-th, respectively, the outputs of which are connected inens with the inputs of the first OR element from the first to the n-th respectively, the output of which is connected to the synchronization input of the buffer register and to the input of the first one-shot, the output of which is connected to the reset input of the command register and to the second input of the synchronization block, the first output of which is connected to the first input the second OR element, the output of which is connected to the synchronization input of the address register, the output of the label of the end of the section of the command register is connected to the input of the second one-shot, the output of which is connected to the third input of the synchronization block and, the second output of which is connected to the reset input of the buffer register and to the first input of the third OR element, the module setup input is connected to the second input of the second OR element, with the input of the synchronization register of the correspondence vector, as well as with the input of the delay element, the output of which is connected to the second input of the third OR element, whose output is connected to the synchronization input of the command register, the group of synchronization outputs (1.N) of the module is connected to the inputs of the block of elements NOT, the outputs of which are connected to the first group of synchronization inputs of the (i.1) th module,

and to the second group of synchronization inputs (M. j) -th module,

group of synchronization outputs of the (α, β) -th module,

connected to the first group of synchronization inputs (α.β + 1) of the module and to the second group of synchronization inputs (α-l.β) of the module, the group of synchronization outputs (l.β) of the module is connected to the first group of synchronization inputs (l.β + l) -th module, the group of synchronization outputs of the (α, N) -th module is connected to the second group of synchronization inputs of the (α-lN) -th module.

 The invention is illustrated by drawings, where in FIG. 1 is a functional diagram of a microcontroller network module; FIG. 2 shows a functional diagram of a synchronization unit, FIG. 3 is a structural diagram of a microcontroller network; FIG. 4 shows the formats of (micro) instructions implemented by the microcontroller network module; FIG. 5 is an illustrative example explaining the principles for implementing parallel algorithms (programs) in a microcontroller network.

и к группе 28 входов синхронизации (M. j)-го модуля,

группа 29 выходов синхронизации (α.β)-го модуля,

подключена к группе 27 входов синхронизации (α.β+l) -го модуля и к группе 28 входов синхронизации (α-l.β)-го модуля, группа 29 выходов синхронизации (l.β)-го модуля соединена с группой 27 входов синхронизации (l.β+l)-го модуля, группа 29 выходов синхронизации (α.N)-го модуля соединена с группой 28 входов синхронизации (α-l.N)-го модуля.The microcontroller network (Fig. 3) contains M • N modules of the same type combined into a matrix structure, where N is the number of modules in a row of the matrix network structure, M is the number of rows, and an additionally entered block of elements is NOT 36, with a group of 29 synchronization outputs ( 1.N) -th module is connected to the inputs of the block of elements NOT 36, the outputs of which are connected to the group of 27 synchronization inputs of the (i.1) -th module,

and to a group of 28 synchronization inputs (M. j) of the module,

group of 29 synchronization outputs of the (α.β) -th module,

connected to a group of 27 synchronization inputs (α.β + l) of the module and to a group of 28 synchronization inputs (α-l.β) of the module, a group of 29 synchronization outputs (l.β) of the module is connected to a group of 27 inputs synchronization of the (l.β + l) -th module, the group of 29 synchronization outputs of the (α.N) -th module is connected to the group of 28 synchronization inputs of the (α-lN) -th module.

 The microcontroller network module (Fig. 1) includes a program memory block 1, address register 2, command register 3 with outputs 3.1 of the logical condition code, 3.2 modifiable digit of the address; 3.3 non-modifiable part of the address, 3.4 microoperations, the first output 3.5 of the number of the synchronization vertex, the second output 3.6 of the number of the synchronization vertex, the output of 3.7 marks of the end of the section and the output of 3.8 marks of the end of the program, 4 logical condition multiplexer, switch 6 addresses, synchronization block 10, first 17, the second 15 and third 16 elements are OR, and the input 23 of the operation code of the module is connected to the first information input of the address switch 6, the output of which is connected to the information input of the address register 2, the output of which is connected to the address input and 1 program memory, the output of which is connected to the information input of the register of 3 teams, the output 3.8 of the end label of the program which is connected to the control inputs of the switch 6 addresses, outputs 3.1 of the logical condition code and 3.2 modifiable category of the address of the register of 3 commands are connected to the control and the first information inputs of the multiplexer 4 logical conditions, respectively, the second information input of which is connected to the input 21 of the logical conditions of the module, the first input of the synchronization unit 10 is connected to the input 25 of the module start, as well as additional The register 5 of the correspondence vector, buffer register 7, the first 8 and the second 9 are decoders of the synchronization vertex number, the first group of elements 11.1-11.n, the second group of elements 12.1-12. n, the group of elements OR 13.1-13.n, the block of elements OR 14, the first 19 and second 18 single vibrators, the delay element 20, the output 3.3 of the non-modifiable part of the address of the register of 3 teams in combination with the output of the multiplexer 4 of the logical conditions connected to the first input of the block of elements OR 14 and to the information input of the buffer register 7, the output of which is connected to the second input of the block of elements OR 14, the output of which is connected to the second information input of the switch 6 of the address, the output of 3.4 microoperations of the register of 3 teams is connected to the output of 22 microoperations of blowing, input 26 of the module compliance vector is connected to the information input of the register 5 of the correspondence vector, the outputs from the first to the nth of which are connected to the first inputs of the elements OR 13.1-13.n, respectively, the first output 3.5 of the synchronization vertex number of the register of 3 commands is connected to the decoder input 8 are the numbers of the synchronization vertex, the outputs from the first to the nth of which are connected to the second inputs of the elements OR 13.1-13.n, respectively, the outputs of which are connected to the first inputs of the elements AND 11.1-11. n, respectively, the inputs of the first group of synchronization inputs of the module 27.1-27.n (27) are connected to the second inputs of the elements AND 11.1-11.n, respectively, the outputs of which are connected to the outputs of the group of synchronization outputs of the module 29.1-29.n (29), respectively, the second output 3.6 of the synchronization vertex number of the register of 3 commands is connected to the decoder 9 input of the synchronization vertex number, the first to nth outputs of which are connected to the first inputs of AND elements 12.1-12. n, respectively, the inputs of the second group of synchronization inputs of the module 28.1-28. n (28) are connected to the third inputs of the elements AND 11.1 -11.n, respectively, the outputs of which are connected to the second inputs of the elements AND 12.1 -12.n, respectively, the outputs of which are connected to the inputs of the element OR 17 from the first to the nth respectively, the output of which connected to the synchronization input of the buffer register 7 and to the input of the one-shot 19, the output of which is connected to the reset input of the register 3 commands and to the second input of the synchronization unit 10, the first output of which is connected to the first input of the OR element 15, the output of which is connected to the synchronization input of the register 2 address ca, output 3.7 of the label of the end of the section of the register of 3 teams is connected to the input of the single-shot 18, the output of which is connected to the third input of the synchronization unit 10, the second output of which is connected to the reset input of the buffer register 7 and to the first input of the OR element 16, the module setup input 24 is connected to the second input of the OR element 15, with the input of the synchronization register 5 of the correspondence vector, as well as the input of the delay element 20, the output of which is connected to the second input of the OR element 16, the output of which is connected to the synchronization input of the register 3 teams.

 The synchronization block (Fig. 2) contains a pulse generator 30, a control trigger 31, a trigger 32, a first 33 and a second 34 AND elements, an OR element 35, the first and second inputs of which are the first and second inputs of the block, respectively, and the output is connected to the installation input control trigger 31, the reset input of which is the third input of the block, and the direct output is connected to the input of the pulse generator 30, the output of which is connected to the first inputs of the elements 33 and 34, as well as to the counting input of the trigger 32, the direct and inverse outputs of which are connected to the second in odes of AND gates 33 and 34, respectively, outputs of which are first and second output block, respectively.

 General features of the functional organization of the microcontroller network are as follows.

The microcontroller network (ISS) is formed from a variety of modules of the same type, combined into a matrix structure (Fig. 3). Each module of the ISS (microcontroller) is implemented in the form of VLSI with internal programmable program memory and has two input and one output information channels designed to connect to other similar modules and exchange control information. Network modules are identified by conditional numbers of the form ij, where i and j make sense, respectively, of the row numbers and column numbers of the matrix structure containing this module, "." - a symbol of concatenation. (Hereinafter, the module with the number ij is called the same as the (ij) th module or module m _ij ).

 The ISS serves to manage complex objects whose behavior is described by a set of programs and involves the parallel flow and interaction of many processes. The software package implemented by the network is divided into many parallel and sequential sections, which are distributed between different modules. Each module implements a subset of the plots.

During the execution of program sections, the ISS modules process two types of teams: operational and communication. Operational teams (these teams have the format F ₂ (Fig. 4)) provide the issuance of control actions on the control object and initiate the execution of the required micro-operations. Communication teams (format F ₃ (Fig. 4)) are used to organize interaction and coordination of various modules, including the launch of sections assigned to other modules (inter-module control transfer), and synchronization of parallel sections of programs.

 The organization of intermodular interaction in the proposed ISS is fundamentally different from the prototype. If the prototype explicitly provides for inter-module transfer of control and synchronization of parallel sections, then in the ISS under consideration there is no inter-module transfer of control in explicit form; only the synchronization procedure is performed. In this case, the launch of program sections implemented by various modules occurs when the corresponding synchronization conditions are met. Such a condition when starting sections immediately following a subset of other (parallel) sections, is the synchronization (completion) of all sections of this subset. When starting sites following a single site, the completion of that single site is a condition.

To set the moment of activation of a certain section B _k ^ij (e) (where e is the serial number of this section for the (ij) th module, k is the program number), this section is associated with the number of the synchronization vertex a _t immediately preceding it (if the activated section immediately preceded by a single section of the program, then the vertex a _t is considered fictitious). The start of the section B _k ^ij (e) occurs after the execution of the vertex a _t , i.e. as soon as all sections of the program immediately preceding it are completed.

Unlike the prototype, where the addresses of the launched sections (control reception addresses) are transmitted from the module initiating the launch, in the proposed network, the indicated addresses are generated directly by the modules realizing the launched sections (modules - control receivers) as a result of self-tuning. The address A _k ^ij (e + 1) of the beginning of the next ((e + 1) th) section executed by the (ij) th module is indicated in the final command of the previous (e-th) section of the program. To specify the addresses of the initial sections of the modules {A _k ^ij (1)}, the format ₁ configuration commands are used (Fig. 4). Each network module is assigned Q such commands, Q is the number of programs implemented by the microcontroller network (the number of programs in the complex being implemented). Each of the Q configuration commands determines the address A _k ^ij (1) of the first command executed by the (ij) th module during the implementation of the kth program, i.e. address of the initial section of the (ij) th module. (If the (i. J) th module is not involved in the execution of the k-th program, then the Ф ₁ command contains only zeros.) The Ф ₁ configuration commands are placed in the program memory block 1 (Fig. 1) at the starting addresses from 1 to Q inclusive. The configuration command, and therefore the program being implemented, is uniquely set by the address when accessing block 1.

 The synchronization process of parallel sections in the proposed ISS is also fundamentally different from the similar process in the prototype. Unlike the prototype, where synchronization is provided by counting one of the modules the number of messages - receipts of completion of parallel sections transmitted by other modules, synchronization in the ISS is based on the distribution and polling of individual signals of overestimation of groups of parallel sections. Each such signal propagates in a separate synchronization control channel, which corresponds to one of the synchronization (merging) vertices of parallel sections. The synchronization control channel is a combination of the elements of various ISS modules and corresponding communications, which ensure the synchronization process of a certain group of parallel sections. So, the qth channel of the synchronization control will include elements And 11.q modules and the qth element of the block of elements NOT 36 with their corresponding connections (Fig. 1, 3).

в общем случае соответствует Q различных векторов, каждый из которых отвечает определенной программе. Вектор соответствия для (i.j)-го модуля и k-й программы имеет вид
S^i.j(k)=(s₁ ^i.j,s₂ ^i.j,..., s_n ^i.j),
где

n_k - число вершин синхронизации в k-й программе.To ensure synchronization of arbitrary groups of parallel sections, each module of the ISS is assigned a vector that sets the correspondence between the set of synchronization vertices of the program and this module. (ij) -th module of the network,

in the general case, there correspond Q different vectors, each of which corresponds to a certain program. The correspondence vector for the (ij) th module and the kth program has the form
S ^ij (k) = (s ₁ ^ij , s ₂ ^ij , ..., s _n ^ij ),
Where

n _k is the number of synchronization vertices in the k-th program.

The value of the component of the vector S ^ij (k) is determined as follows:
s _q ^ij = 0, if the (ij) -th module is assigned a certain part of the program ending in the q-th synchronization vertex;
s _q ^ij = 1 if the (ij) th module does not realize any part ending in the qth synchronization vertex, or the qth synchronization vertex is absent in the kth program (which is possible for n _k <q).

}, завершающихся (сходящихся) в q-й вышине синхронизации, осуществляется на основе циклического распространения сигнала d_q завершения группы участков в q-м канале управления синхронизацией МКС. Сигнал d_q формируется (1.N)-м модулем сети (фиг. 3). В исходном состоянии d_q=0 (параллельные участки не завершены) и, следовательно,

= 1.Synchronization of a group of parallel sections B _q = {B ₁ ^q , B ₂ ^q , ...,

}, ending (converging) in the qth synchronization height, is based on the cyclical propagation of the signal d _q completion of the group of sections in the qth ISS synchronization control channel. The signal d _q is generated by the (1.N) -th module of the network (Fig. 3). In the initial state, d _q = 0 (parallel sections are not completed) and, therefore,

= 1.

Данный сигнал одновременно подается модулям с номерами 1.1, 2.1, ..., М.1 и М.2, М. 3, . . . , M.N. Далее сигнал

последовательно распространяется через все модули МКС в направлении от (М.1)-го модуля вверх и вправо (по схеме фиг. 3) и в конце концов появляется на выходе (1.N)-го модуля.The synchronization process includes two phases - the formation of the sign of the end of the synchronized sections and the transfer of this sign to all the ISS modules. The first of these phases begins with a single signal

This signal is simultaneously supplied to the modules with numbers 1.1, 2.1, ..., M.1 and M.2, M. 3,. . . , MN Further signal

sequentially propagates through all ISS modules in the direction from the (M.1) th module up and to the right (according to the scheme of Fig. 3) and finally appears at the output of the (1.N) th module.

через некоторый модуль m_i.j происходит следующим образом. Если s_q ^i.j = 1, то появление единичных сигналов

на нижнем и левом входах (i.j)-го модуля обусловливает формирование единичного сигнала

на его выходе. Если s_q ^i.j = 0, то формирование единичного сигнала

на выходе (i.j)-го модуля происходит только при условии завершения участка B_f ^q, реализуемого (i.j)-м модулем.Signal propagation

through some module m _ij occurs as follows. If s _q ^ij = 1, then the appearance of unit signals

at the lower and left inputs of the (ij) -th module determines the formation of a single signal

at its exit. If s _q ^ij = 0, then the formation of a single signal

at the output of the (ij) th module, it occurs only if the section B _f ^q completed by the (ij) th module is completed.

передается на выход (i. j)-го модуля и поступает на (i-1.j)-й и (i.j+1)-й модули.The condition of the plot B _f ^q is determined by the value of the signal - sign g _q ^ij : g _q ^ij = 1, if the plot B _f ^{q is} completed; g _q ^ij = 0 otherwise. In case the section B _f ^{q is} not completed, a zero signal is set at the output of the (ij) th module. This signal generates zero signals at the outputs of all modules located above and / or to the right of the (ij) th module. At the output of the (1.N) -th module, respectively, there will also be a zero signal d _q = 0. As soon as the completion of section B _f ^q , a single signal

It is transmitted to the output of the (i.j) th module and goes to the (i-1.j) th and (i.j + 1) th modules.

пройдет на входы (1.N)-го модуля и на выходе (1.N)-го модуля, таким образом, будет сформирован сигнал d_q = 1, сообщающий об окончании синхронизируемых параллельных участков. На этом первая фаза синхронизации завершается.After completion of all parallel sections of group B _q signal

will pass to the inputs of the (1.N) -th module and at the output of the (1.N) -th module, thus, a signal d _q = 1 will be generated, informing about the end of synchronized parallel sections. This completes the first phase of synchronization.

подается на входы модулей с номерами 1.1, 2.1, ..., M.1 и М.2, М.3, ..., M.N и распространяется через все модули МКС до модуля с номером 1. N. В процессе распространения сигнала происходит запуск всех модулей, ожидающих завершение параллельных участков группы B_q. Признаком запуска модуля является переход сигнала

из единицы в нуль (1 ---> 0). Вторая фаза и процесс синхронизации параллельных участков в целом завершаются после появления нулевого сигнала на выходе (1.N)-го модуля.The second phase of synchronization begins with the inversion of the signal d _q . Received Zero Signal

fed to the inputs of modules with numbers 1.1, 2.1, ..., M.1 and M.2, M.3, ..., MN and distributed through all modules of the ISS to module number 1. N. During signal propagation, start of all modules awaiting completion of parallel sections of group B _q . A sign of the module starting is a signal transition

from one to zero (1 ---> 0). The second phase and the synchronization process of parallel sections as a whole are completed after the appearance of a zero signal at the output of the (1.N) -th module.

The principles of organizing intermodular control transmission and synchronization of parallel sections in the proposed ISS are illustrated by an example of the implementation of the parallel control algorithm shown in FIG. 5a. The algorithm includes 20 parallel and sequential sections B _k ^ij (e), the belonging of which to a particular module is given by the superscript ij. The algorithm in question includes synchronization vertices a ₁ , a ₂ , ..., a ₁₁ ; the vertices a ₇ , a ₈ , a ₉ , a ₁₀ , a ₁₁ (shown by the dotted line) are fictitious, since they correspond to transitions between separate sections. The ISS contains 3x3 modules.

The module settings table, which determines the addresses of the initial sections A _k ^ij (1), as well as the numbers of synchronization vertices a _t , after which the corresponding modules must be launched, is presented in FIG. 5 B. In accordance with this table, the modules m _1.1 , m _3.2, and m _3.3 are launched after the synchronization vertex a _{1 is} executed, i.e. after the completion of section B _k ^2.2 (1), the launch of module m _{1.2 is} carried out after reaching the synchronization peak a ₇ , i.e. after completion of section B _k ^3.3 (1), etc. The m _2.2 module is activated immediately at the time of the ISS launch, regardless of the status of other modules.

The table of correspondence vectors for the considered algorithm is shown in FIG. 5c. According to this table, module m _1.1 implements sections that terminate at the vertices of synchronization a ₂ , a ₄ and a ₅ (s ₂ ^1.1 = s ₄ ^1.1 = s ₅ ^1.1 = 0), module m _1.2 - sections that converge at vertices a ₃ , a ₄ and a ₆ (s ₃ ^1.2 = s ₄ ^1.2 = s ₆ ^1.2 = 0), etc.

 The processes of synchronization and launch of parallel sections are described in more detail when considering the corresponding operating modes of the ISS modules.

 The purpose of the elements and blocks of the microcontroller network module (Fig. 1) is as follows.

 Block 1 of the program memory serves for the permanent storage of instructions constituting parallel and consecutive sections of programs assigned to the current module. Information (command) at the output of block 1 appears immediately after the corresponding address is supplied to its address input.

 Register 2 addresses is intended for temporary storage of the executive address of the next command.

 The register of 3 commands is used to fix the next command read from block 1 for the duration of its processing.

 The multiplier 4 of the logical conditions is used to interrogate the values of the logical conditions at the input of the module 21 and modify the least (modified) bit of the address of the next command at the branch points of programs.

Register 5 of the correspondence vector is introduced to store the vector S ^ij (k) during the execution time of the k-th program.

 The switch 6 addresses provides a choice of the direction of reception of the executive address of the next command.

 The buffer register 7 is designed to temporarily fix the executive address of the next command in the process of starting the current module after completion of a group of parallel sections of the program. The need for such a fixation is due to the disappearance of information at the outputs 3.2 and 3.3 of register 3 (due to the reset of register 3 at the time of completion of the group of parallel sections) until the actual address of the next command is written to register 2.

The decoder 8 is used to convert the code of the synchronization vertex number a _q corresponding to the program section to be completed into a unitary code and generate signals {g _q ^ij } - signs of the status (completion) of program sections.

The decoder 9 provides the conversion of the code of the synchronization vertex number a _t , which determines the moment of the subsequent start of the current module, into the corresponding unitary code, as well as blocking / opening of the elements And 12.1 - 12.n.

Block 10 synchronization is necessary for the formation of two shifted from each other sequences of pulses t ₁ and t ₂ synchronizing the operation of various nodes of the module.

Elements And 11.1, 11.2, ..., 11.n are introduced to control the propagation of signals d ₁ , d ₂ , ..., d _n from the inputs 27.1, 28.1; 27.2, 28.2; ...; 27.n, 28.n to the outputs 29.1, 29.2, ..., 29.n of the module, as well as to the inputs of the elements AND 12.1, 12.2, ..., 12.n, respectively.

Elements AND 12.1, 12.2,. .., 12.n serve to control the passage of signals d ₁ , d ₂ , ..., d _n from the outputs of the elements 11.1, 11.2, ..., 11.n, respectively, to the inputs of the element OR 17.

 Elements OR 13.1, 13.2, ..., 13.n are intended for combining signals from the first, second, etc., n-th outputs of the register 5 and decoder 8, respectively.

 The block of elements OR 14 provides the combination of codes (addresses) from the output of the buffer register 7, as well as from the output 3.3 of the register 3 and the output of the multiplexer 4.

 The OR element 15 is used to transmit pulses from the first output of block 10 and from the input 24 of the module settings to the synchronization input of register 2.

 The OR element 16 provides the transmission of pulses from the second output of block 10 and from the output of the delay element 20 to the synchronization input of register 3.

 The OR element 17 is used to combine the signals from the outputs of the elements AND 12.1-12.n.

 The one-shot 18 is designed to generate a pulse, which turns off the synchronization unit 10.

 The one-shot 19 serves to generate a pulse, which enables the module to start after the end of the required groups of parallel sections of programs.

 Element 20 provides a delay in transmitting the tuning pulse from the input 24 of the module to the second input of the OR element 16 during the reading of the tuning command from block 1.

The block of elements NOT 36 (Fig. 3) is designed to invert signals d ₁ , d ₂ , ..., d _n from the outputs 29.1, 29.2, ..., 29.n (1.N) of the ISS module.

 Consider the process of functioning of the microcontroller network in detail.

 Initially, the memory elements (registers and triggers) of all MKC modules are in a state of logical zero. The exception is triggers 32 of synchronization blocks 10 (Fig. 2), as well as bits 3.8 of registers 3 (Fig. 1), set to a single state. Based on the indicated state of the memory elements, the module synchronization blocks 10 are turned off, the switches 6 are configured to receive information from inputs 23, and logic zero signals are located at all module outputs. Zero signals from the outputs of the 29.1-29.n (1.N) -th MKC module (Fig. 3) form single signals at the outputs of the block of elements NOT 36.

Network operation begins with configuring the modules to execute the required program. Suppose this program has number k. Setting the (ij) th module to execute the kth program is reduced to setting the address A _k ^ij (1) (the address of the first command), as well as determining the number of the synchronization vertex a _t , after which the (ij) th module.

The setup process begins with the input of the 23 (ij) th module (Fig. 1) operation code. The operation code (CPC), which is the code number of the program (k), is transmitted through the switch 6 to the information input of register 2. At the same time, a tuning pulse is applied to the input 24 of the module. The specified pulse through the element OR 15 is fed to the input of the synchronization register 2 and the trailing edge fixes the CPC in this register. Next, the CPC from the output of register 2 is fed to the address input of block 1 and generates the configuration command Ф ₁ (Fig. 4) corresponding to the k-th program at its output.

At the same time, the tuning pulse through the delay element 20 and the OR element 16 (Fig. 1) is transmitted to the synchronization input of register 3 and trailing a write of the command read from block 1 into register 3. After fixing the command at the outputs 3.2 and 3.3 of register 3 the address A _k ^ij (1) is formed, and at the output 3.6, the code of the number (t) of the synchronization vertex (NVS) a _t is generated. The remaining outputs of register 3 are set to zero signals.

The zero signal from the output 3.8 of register 3 reconfigures the switch 6 to receive information from the output of the block of elements OR 14. Since the output 3.1 of register 3 contains a zero code (the logical conditions are not checked during configuration), the address A _k ^ij (1) passes without changes through the block of elements OR 14. Then this address is transmitted through the switch 6 and is installed on the information input of the register 2.

At the same time, the code of the synchronization vertex number a _t from the output 3.6 of register 3 is supplied to the input of the decoder 9. As a result, a single signal is generated at the t-th output of the decoder 9. This signal opens the element And 12.t and thereby provides the possibility of polling the signal level at the output of the element And 11. t. (The process of generating a signal at the output of element 11.t is described in detail below when considering the operation of the ISS in the synchronization mode of parallel sections.) For the ISS module, which implements the initial section of the kth program, the assignment of the NVS code is not required, since this module is activated immediately ISS launch regardless of synchronization conditions. At the output 3.6 of register 3 of the module in question, respectively, a zero code is set.

Simultaneously with the actions described above, the value of the vector S ^ij (k) is written to the register 5 of the module (the correspondence is established between the (i. J) th module and the set of synchronization vertices of the kth program). The vector S ^ij (k) is supplied to the input 26 of the module and on the trailing edge of the tuning pulse from the input 24 of the module is entered in register 5. This completes the setup process of the (ij) th module.

 Similarly, the process of setting up the remaining modules of the ISS proceeds, and the setting up of various modules is performed simultaneously. The inputs of the same modules are supplied to the inputs 23 of all modules; correspondence vectors for different modules are generally different. As a result of the setup, for each module, the moment of its launch when the k-th program is executed by the network is determined, the corresponding address (the address of the first command) is set, and, in addition, a subset of the synchronization vertices of the k-th program is established, in which the sections realized by the module end.

After the configuration is completed, the ISS is launched. To start the network, a start pulse is applied to input 25 of one of its modules. Such a module is a module that implements the initial section of the k-th program. Suppose that the specified module has the number ij (in the example in Fig. 5 it is the module m _2.2 ). The start pulse from the input of the 25th (ij) th module is transmitted to the first input of the synchronization unit 10. Further, this pulse passes through the OR element 35 (Fig. 2), acts on the input of the installation of the trigger 31 and puts this trigger in a single state. A single signal from the direct output of the trigger 31 is fed to the input of the generator 30 and allows the formation of a pulse train at its output.

The first pulse from the output of the generator 30 passes through the element And 33 to the first output of the synchronization unit (element 33 is opened by a single signal from the direct output of the trigger 32). On the trailing edge of the same pulse, the trigger 32 switches to the zero state. As a result, the AND element 33 is blocked and the And 34 element is opened. The second pulse from the output of the generator 30 passes through the open element 34 to the second output of the synchronization block. The trailing edge of this pulse again returns trigger 32 to its original (single) state. The third pulse passes again to the first output of the synchronization unit, and the fourth pulse passes to the second output, etc. Thus, at the outputs of the synchronization unit 10, the generation of two sequences of synchronization pulses t ₁ and t ₂ shifted relative to each other begins.

The first pulse t ₁ from the first output of the synchronization block 10 (Fig. 1) passes through the OR element 15 to the synchronization input of register 2 and fixes in this register the address A _k ^ij (1) coming from the output of the switch 6. Address A _k ^ij (1 ) from the output of register 2 goes to the address input of block 1 and generates the first command of the k-th program at its output.

The first pulse t ₂ from the second output of the synchronization block 10 passes through the OR element 16 and, then arriving at the synchronization input of register 3, writes to this register read from block 1
a team. At the same time, the same pulse is fed to the reset input of the buffer register 7 and confirms its zero state. Thus, the (ij) th module and the microcontroller network as a whole begin to execute the kth program.

We will consider the further functioning of the ISS under the assumption that the (ij) th module performs some (in the general case, not the initial) section of the kth program, for example, the section B _f ^q ending with the synchronization vertex a _q . In addition, we assume that at the same time as the (ij) th module some other ISS modules can function (other modules are in a passive state or in a standby state).

During the execution of the plot B _f ^q (ij) -th module can process commands of the formats F ₂ , F ₃ or F ₄ (Fig. 4). Processing a command of format Ф ₂ corresponds to the actual execution of the program section (mode A), command Ф ₃ determines the mode of completion of the program section (mode B), and command F ₄ determines the mode of completion of the program as a whole (mode C). Consider the operation of the module in each of these modes.

Mode A. The command recorded in register 3 has the format Ф ₂ (Fig. 4). In this case, at the output 3.4 of register 3 (Fig. 1), a microoperation code (MO) is generated, at the outputs 3.2 and 3.3 the address of the next command A _{sl is} generated (at the output 3.3 - the non-modifiable part, and at the output 3.2 - the modified bit of the address of the next command, changeable at the branch points of programs), the output code 3.1 sets the code of the interrogated logical condition (LU), and outputs 3.5-3.8 display logic zero signals.

 The MO code from the output 3.4 of register 3 is transmitted to the output 22 of the module and, coming further to the input of the control object, initiates the execution of the required micro-operations. Zero signals from the outputs 3.5 and 3.6 of register 3 act on the inputs of the decoders 8 and 9, respectively, and form zero signals on all their outputs. The zero signal from the output 3.8 of register 3 is fed to the control inputs of the switch 6 and sets it to receive the address of the next command from the output of the block of elements OR 14.

Simultaneously with the described actions, the executive address of the next command is formed. The specified address is formed from the address of the next A _cl command by replacing its modifiable (least significant) digit with the value of the interrogated LU. A new low-order value is formed at the output of the multiplexer 4. The process of generating this value proceeds as follows. Modifiable discharge (A _m) of the address A outputted from 3.2 _cl register 3 is fed to a first data input of the multiplexer 4, and output from the code LU 3.1 is supplied to the control input of the multiplexer 4. If LT code different from zero, the output of the multiplexer 4 is transmitted value corresponding LU from the input of 21 modules. If the LU code is zero, then the output of multiplexer 4 receives the value of A _m from the output of register 3.2. 3. The value from the output of multiplexer 4 in combination with the unmodifiable (high) part of the address of the next command (A _n ) from output 3.3 of register 3 forms the executive address of the following A team _ff ^*.

The address A _SL ^* through the block of elements OR 14 and the open switch 6 passes to the information input of the register 2. The next synchronization pulse t ₁ from the first output of the synchronization block 10 fixes the address A _SL ^* in the register 2. The address A _SL ^* from the output of the register 2 goes to address input of block 1 and provides reading from block 1 of the next command of the k-th program. The next pulse t ₂ from the second output of the synchronization block 10 through the OR element 16 is fed to the synchronization input of register 3 and writes the read command to this register.

This completes the work of the (ij) th module in mode A. The read command can again be in the format F ₂ or it can be a team in the format F ₃ or F ₄ .

Mode B. The command recorded in register 3 has the format Ф ₃ (Fig. 4). In this case, the (ij) th module completes the execution of a certain section of B _f ^q , performs self-tuning on the implementation of the next section of the k-th program, and enters the standby state. During self-tuning, the (ij) th module sets the address A _k ^ij (e + 1) of the beginning of the next ((e + 1) th) section B _h ^t (here e is the sequence number of the section B _f ^q for the (ij) th module) and fixes the number (t) of the synchronization vertex a _t (after reaching which the (i. j) th module should be launched).

At the output of register 3, 3, a single mark of the end of the program section (M _ku ) appears, indicating the format of the command read, at the outputs 3.2 and 3.3 of register 3, the address A _k ^ij (e + 1) is generated, at the output 3.1 the LU code is generated, and at the outputs 3.4 and 3.8 set logic zero signals. At the same time, the numbers (numbers of numbers) of the synchronization vertices are generated at the outputs 3.5 and 3.6 of register 3: at the output 3.5, the number (q) of the synchronization vertices a _q , which completes the section B _f ^q completed by the module; at output 3.6, the number (t) of the synchronization vertex a _t , which determines the moment of the next start of the (ij) th module (the case when t = q is admissible).

In the example of FIG. 5 after the execution of the section B _k ^2.2 (1) at the output of 3.5 register 3 of the module m _2.2 , the vertex number a ₁ will be generated, at the output 3.6, the number of the vertex a ₂ will be set, followed by the next section B _k ^2.2 (2), performed module m _2.2 . The start address of the area A _k ^2.2 (2) will be fixed at the outputs 3.2 and 3.3 of the register 3. After portion B _k ^2.2 (2) at the output register 3 3.5 m _2.2 unit will set a SiS _3, and the output 3.6 - a NAF ₆ , followed by the next section of the module m _2.2 - section B _k ^ij (3).

 Similarly, other modules are self-tuning.

The code of the synchronization vertex number a _q from the output 3.5 of register 3 goes to the input of the decoder 8 and excites a single signal g _q ^ij - a sign of the completion of the section B _f ^q - at its qth output. A single signal g _q ^ij passes through the OR element 13.q (at the first input of the element 13.q there is a signal s _q ^ij = 0 from the qth output of register 5). Next, the signal g _q ^{ij is} fed to the first input of AND 11.q and thereby indicates the end of the section B _f ^q . In turn, the NVS code a _t from the output 3.6 of register 3 is fed to the input of the decoder 9 and excites the signal of the logical unit at its t-th output. A single signal from the t-th output of the decoder 9 opens the And 12.t element, providing the possibility of the subsequent launch of the (ij) -th module at the completion of sections converging at the synchronization vertex a _t .

At the same time, the zero signal from the output 3.8 of register 3 sets the switch 6 to receive information from the output of the block of elements OR 14. The positive difference in the signal level (0 ---> 1) arising from the output 3.7 of register 3 acts on the one-shot 18 and generates its output is momentum. This pulse is supplied to the third input of the synchronization unit 10 and, then passing to the reset input of the trigger 31 (figure 2), switches this trigger to a state of logical zero. The zero signal from the direct output of the trigger 31 turns off the generator 30 and thereby stops the process of generating synchronization pulses t ₁ and t ₂ at the outputs of the synchronization unit 10. Thus, the process of reading commands from block 1 is temporarily stopped (the module enters the standby state).

Simultaneously with the described actions, the executive address of the next command is formed (the address from which the actual launch of the (ij) th module will occur after reaching the t-th synchronization vertex). The specified address is formed from the address A _k ^ij (e + 1) by modifying its low order (A _m ) with the value of the logical condition from the input 21 of the module (Fig. 1). The process of forming the executive address proceeds in the same way as when the module is in mode A (see above). The resulting executive address (we denote it as A _k ^ij (e + 1) *) goes to the information input of the buffer register 7, and also through the block of elements OR 14 and the switch 6 passes to the information input of the register 2.

This completes the operation of the module in mode B. Similarly, the completion of other sections of the kth program, including the sections {B _z ^q }, z ≠ f, converging at the qth vertex of synchronization.

}, сходящихся в вершине синхронизации a_q. Будем считать, что участки В₁ ^q, В₂ ^q, ...,

распределены между модулями МКС произвольным образом.Consider the operation of the ISS in the synchronization mode of a group of parallel sections, as well as the process of launching modules during synchronization. For definiteness, we will consider a specific group of sites, for example, a group of sites B _q = {B ₁ ^q , B ₂ ^q , ...,

} converging at the synchronization vertex a _q . We assume that the sections B ₁ ^q , B ₂ ^q , ...,

distributed between the ISS modules at random.

будут нулевыми, поскольку в каждой группе В₁, В₂, . . .,

имеется хотя бы один незавершенный участок. Уровень сигналов d_z, z = n_k+1, n_k+2, ..., n, при выполнении k-й программы несуществен. ) Сигнал d_q поступает на q-й вход блока элементов НЕ 36 (фиг. 3) и формирует на q-м выходе этого блока сигнал логической единицы

С появлением сигнала

начинается первая фаза синхронизации - формирование признака окончания участков группы B_q.The synchronization process of parallel sections in the ISS occurs cyclically. The next synchronization cycle starts from the moment the zero signal d _q (sign of completion of the group of parallel sections B _q ) appears at the output of the 29.q (1. N) -th module. (In the initial state, i.e., before the start of the kth program, all signals d ₁ , d ₂ , ...,

will be zero, since in each group B ₁ , B ₂ ,. . .,

there is at least one incomplete plot. The signal level d _z , z = n _k +1, n _k +2, ..., n, is not significant when executing the k-th program. ) The signal d _q arrives at the qth input of the block of elements NOT 36 (Fig. 3) and generates a signal of a logical unit at the qth output of this block

With the advent of the signal

the first phase of synchronization begins - the formation of a sign of the end of sections of the group B _q .

A single signal from the qth output of a block of elements NOT 36 is simultaneously supplied to the inputs 27.q of the ISS modules from (1.1) to (M.1) of the (modules of the first column) and to the inputs 28.q of the ISS modules with (M .1) th in (MN) th (modules of the Mth row). Single signals from inputs 27.q of modules from (1.1) through (M.1) th go to the second inputs of elements And 11.q (Figs. 1, 3), and single signals from inputs 28.q of modules with ( M.1) -th along (MN) -th are transferred to the third inputs of the elements And 11.q. Since at the inputs of 28.q modules from (1.1) th through (M-1.1) th and at the inputs of 27.q modules from (M.2) th through (MN) th, there are initially logical zero signals (due to zero the signal level at the output of the 29.q (M.1) -th module), at the outputs of their elements 11.q, zero signals are also stored regardless of the signal level at the outputs of the elements OR 13.q. At the same time, since single signals are set at the inputs of the 27.q and 28.q (M.1) th module, the And 11.q element of this module opens and the signal level at its output is determined only by the signal from the output of the OR 13 element. q. The latter, in turn, depends on the signal s _q ^M.1 from the qth output of the register 5 and the signal g _q ^M.1 from the qth output of the decoder 8.

с входов 27.q и 28.q на выход элемента 11.q).If s _q ^M.1 = 1, i.e. (M.1) -th module does not realize sections from the group of synchronized sections B _q (and, accordingly, should not affect the synchronization process), then a single signal is generated at the output of OR 13.q. This signal is fed to the first input of the And 11.q element and, since there are also single signals at the other inputs of this element, it forms a single signal at its output (i.e., it actually relays signals

from inputs 27.q and 28.q to the output of element 11.q).

ретранслируются на выход элемента 11.q). Однако в случае если участок В_w ^q не завершен, то g_q ^M.1 = 0 и на выходе элемента 13.q образуется нулевой сигнал. Этот сигнал блокирует элемент И 11.q и формирует на его выходе нулевой сигнал (передача сигналов

на выход элемента 11.q заблокирована). Нулевой сигнал на выходе элемента 11. q сохраняется до тех пор, пока не будет завершен участок В_w ^q.If s _q ^M.1 = 0, i.e. a certain section B _w ^{q of} group B _{q is} assigned to the (M.1) th module, the signal at the output of element 13.q is determined by the signal g _q ^M.1 from the qth output of the decoder 8 (signal generation _{q q} ^{M.1 is} described above by the example of the (i. j) th module). If section B _w ^{q is} completed, then g _q ^M.1 = 1 and a single signal appears at the output of element 13.q. Accordingly, a single signal will be at the output of element 11.q (signals

are relayed to the output of element 11.q). However, if the section B _w ^{q is} not completed, then g _q ^M.1 = 0 and a zero signal is generated at the output of element 13.q. This signal blocks the And 11.q element and generates a zero signal at its output (signal transmission

to the output of element 11.q is blocked). The zero signal at the output of element 11. q is maintained until the section B _w ^{q is completed} .

 The signal from the output of element 11.q goes to the output of the 29.q (M.1) th module and then extends to the input of the 27.q (M.2) th module (to the right, Fig. 3) and to the input 28.q (M-1.1) th module (up). If this signal is zero, then it blocks the elements of the 11. Q (M.2) th and (M-1.1) th modules (Figs. 1, 3) and thereby confirms the zero signal level at the outputs 29.q of these modules . The zero signals from the outputs of the 29.q (M.2) th and (M-1.1) th modules, in turn, determine the formation of logical zero signals at the outputs of the 29.q (M.2) th, (M. 3 ) th and (M-2.1) th modules. Zero signals from the outputs of the 29.q (M-1.2) th, (M.3) th and (M-2.1) th modules form zero signals at the outputs of the 29.q (M-1.2) th, (M- 1.3) th, (M.4) th and (M-3.1) th modules, etc. And finally, the zero signals from the outputs of the 29.q (1.N-1) th and (2.N) th modules confirm the zero signal dq at the output of the 29.q (1.N) th module.

с q-го выхода блока элементов НЕ 36). Теперь уровень сигнала на выходах указанных элементов определяется сигналами с выходов элементов ИЛИ 13.q. Формирование сигнала на выходах элементов 13.q (М.2)-го и (М-1.1)-го модулей происходит так же, как и в случае (М.1)-го модуля. Если s_q ^M.2 = 1 или s_q ^M.2 = 0 и g_q ^M.2 = 1, s_q ^M-1.1 = 1 или s_q ^M-1.1 = 0 и g_q ^M-1.1 = 1, то эти сигналы единичные. Если же s_q ^M.2 = 0 и g_q ^M.2 = 0, s_q ^M-1.1 = 0 и g_q ^M-1.1 = 0, то указанные сигналы нулевые.If the signal at the output of the 29.q (M.1) th module is single, then at the second and third inputs of the elements And 11.q (M.2) th and (M-1.1) th modules the units coincide (at the second the input of the element 11.q (M-1.1) of the module and the third input of the element 11. q (M.2) of the module receives a single signal

from the q-th output of the block of elements NOT 36). Now the signal level at the outputs of these elements is determined by the signals from the outputs of the elements OR 13.q. The signal formation at the outputs of the elements of the 13.q (M.2) th and (M-1.1) th modules occurs in the same way as in the case of the (M.1) th module. If s _q ^M.2 = 1 or s _q ^M.2 = 0 and g _q ^M.2 = 1, s _q ^M-1.1 = 1 or s _q ^M-1.1 = 0 and g _q ^M-1.1 = 1, then these signals are single. If s _q ^M.2 = 0 and g _q ^M.2 = 0, s _q ^M-1.1 = 0 and g _q ^M-1.1 = 0, then these signals are zero.

 The signals from the outputs of the elements of 11.q (M-1.1) th and (M.2) th modules go to the outputs 29. q of these modules and then apply to the inputs 28.q (M-2.1) th, 27.q (M-1.2) th modules and to the inputs of the 28.q (M-1.2) th, 27.q (M.3) th modules, respectively.

In a similar way, signals are generated at the outputs of the 29th, q (M-2.1) th, (M-1.2) th and (M.3) th modules, then signals are generated at the outputs of 29.q (M-1.3) in the same way ) th, (M-2.2) th, (M-3.1) th and (M.4) th modules, etc. In the end, a d _q signal is generated at the output of the 29.q (1.N) th module. As follows from the above, the value of this signal will remain zero until at least one of the remaining modules, for example, the (i. J) th module, has a zero signal at the output 29.q, or s _q ^1.N = 0 and g _q ^1.N = 0, i.e. while in the group B _q there is at least one incomplete section. The zero signal from the output of the 29.q (ij) th module will block all other modules located above and / or to the right of it (according to the scheme of Fig. 3). At the outputs 29. q of these modules there will be a zero signal level regardless of the signals at the outputs of their elements 13.q. As soon as all sections of the group B _q are completed, at the outputs 29. q of all network modules, single signals will appear. Accordingly, the signal d _q at the output of the 29.q (1.N) -th module will also take a single value.

обеспечивается подготовка модулей к последующему запуску. Для этого сигнал с выхода элемента 11.q (i.j)-го модуля передается на второй вход элемента И 12.q. В случае если данный сигнал нулевой, то он закрывает элемент 12.q. Если же этот сигнал единичный, то он открывает элемент 12.q и разрешает прохождение сигнала с q-го выхода дешифратора 9 на его выход. Если на q-м выходе дешифратора 9 находится единичный сигнал (что определяет необходимость запуска (i.j)-го модуля после достижения q-й вершины синхронизации), то на выходе элемента 12.q, а значит, и на выходе элемента ИЛИ 17 формируется единичный сигнал. Тем самым обеспечивается подготовка (i.j)-го модуля к последующему запуску. Запуск модуля произойдет в момент перехода сигнала на выходе элемента 17 из единицы в нуль (процесс запуска подробно рассмотрен ниже).During the implementation of the first phase of synchronization, along with the propagation of the signal

modules are prepared for subsequent launch. For this, the signal from the output of the element 11.q (ij) of the module is transmitted to the second input of the element And 12.q. If this signal is zero, then it closes the element 12.q. If this signal is single, then it opens the 12.q element and allows the signal to pass from the qth output of the decoder 9 to its output. If at the qth output of decoder 9 there is a single signal (which determines the need to start the (ij) th module after reaching the qth peak of synchronization), then at the output of element 12.q, and therefore, at the output of element OR 17, a single signal. This ensures the preparation of the (ij) th module for subsequent launch. The module will start when the signal at the output of element 17 passes from one to zero (the start-up process is discussed in detail below).

With the advent of a single signal d _q at the output of the 29.q (1.N) -th module, the first phase of synchronization ends and a transition to the second phase occurs.

A single signal d _q from the output of the 29.q (1.N) -th module is fed to the q-th input of the block of elements NOT 36, as a result of which a negative level drop occurs at the q-th output of the indicated block (1 ---> 0 ) This difference (which is a sign of the launch of modules awaiting completion of sections of group B _q ) is simultaneously transmitted to the inputs 27.q of the ISS modules from (1.1) through (M.1) of the (first column) and to the inputs 28.q of the ISS modules from (M.1) th to (M.N) th (Mth row). As a result, the outputs of the elements And 11.q of these modules also cause a negative difference in signal level. From the outputs 29.q of the modules from (1.1) -th through (M-1.1) -th and from (M.2) -th through (M.N) -th difference in signal level through the corresponding elements 11.q applies to outputs 29 .q modules from (1.2) th in (M-1.2) th and from (M-1.3) th in (M-1.N) th. Then, in a similar manner, the signal level difference propagates to the outputs 29.q of the modules from (1.3) th to (M-2.3) th and from (M-2.4) th to (M-2.N) th, etc. d. In the end, a negative signal level difference will reach one of the inputs - 27.q or 28.q - of the (1.N) -th module.

As a result, at the output of the 29.q (1.N) -th module, the zero signal d _q will be set.

With the appearance of a zero signal d _q , the second phase of synchronization and the next synchronization cycle of parallel sections as a whole are completed. Immediately after the formation of a zero signal at the output of the 29.q (1.N) -th module, the next synchronization cycle begins.

During the propagation of the signal level difference through the ISS, modules are launched that are waiting for the completion of the group of sections B _q . These modules implement sections of the k-th program immediately following the sections of the group B _q . For example, if B _q = B ₄ = {B _k ^3.1 (1), B _k ^1.1 (2), B _k ^1.2 (2)} (Fig. 5a), then such sections will be B _k ^2.3 (1), B _k ^1.1 (3) and B _k ^3.1 (2); accordingly, the modules m _2.3 , m _1.1 and m _3.1 will be launched.

 We will consider launching the ISS modules using the example of the operation of a module with the number (i.j).

If activation of the (ij) th module after the end of the group of sections B _{q is} not required, then the output 3.6 of register 3 of this module contains a code different from the NBC code a _q (this code can be zero if the (ij) th module executes some section of the kth program, and nonzero if the (ij) th module completed the execution of some section converging at the μth synchronization vertex, μ ≠ q). Accordingly, at the qth output of the decoder 9 is a zero signal. This signal blocks the AND 12.q element, and therefore, the appearance of a signal level difference at the output of the And 11.q element does not affect the signal level at the output of the OR element 17. The (ij) th module is not launched.

If the (i. J) -th module must be activated after the end of the group of sections B _q (i.e., upon reaching the synchronization peak a _q ), then the output 3.6 of register 3 of this module contains the NVC code a _q (set during operation of the module in B mode). Accordingly, at the qth output of the decoder 9 there is a signal of a logical unit, which opens the element And 12.q. Since a single signal is also set at the output of the AND 11.q element, a single signal will be at the output of the 12.q element, and therefore, at the output of the OR element 17.

As soon as a negative signal level drop occurs at the output of the And 11.q element, the signal at the output of the 12.q element goes from one to zero and a negative signal level drop is also formed at the output of the element 17. This differential effect on the single-shot 19 and excites at its output a start pulse of the module. At the same time, the same difference propagates to the synchronization input of buffer register 7 and fixes in this register the start address of the (ij) th module A _k ^ij (e + 1) ^* , formed at the completion of the (i. J) th module of the e-th section k program (see mode B). The address from the output of the register 7 confirms the information at the output of the block of elements OR 14.

At the same moment, the pulse from the output of the one-shot 19 arrives at the second input of the synchronization unit 10 and, passing further through the OR element 35 (Fig. 2) to the installation input of the trigger 31, switches this trigger to a single state. A single signal generated at the direct output of the trigger 31 includes a generator 30. Thus, at the outputs of the synchronization unit 10, the formation of synchronization pulses t ₁ and t ₂ begins.

At the same time, the pulse from the output of the single-shot 19 (Fig. 1) is fed to the reset input of register 3 and sets it to zero. At all outputs of register 3, zero signals are generated. As a result, at all outputs of the decoders 8 and 9, a zero signal level is formed. The address code at the first input of the OR block 14 also becomes zero. However, at the output of the block of OR elements 14, the address A _k ^ij (e + 1) ^* from the output of register 7 is still stored. Accordingly, this address is also stored at the information input of register 2.

The reset of register 3 immediately after the completion of sections of group B _{q is} necessary in order to prevent the restart of the (ij) th module as a result of the next synchronization cycle. This is due to the fact that the next synchronization cycle begins immediately after the end of the previous cycle and at the outputs of the elements 13.q of all modules implementing sections of the group B _q , single signals can still be found. Installation of the outputs 13.q of zero signals is carried out only at the time of launch of these modules.

Next, the first pulse t ₁ from the first output of the synchronization unit 10 through the OR element 15 is supplied to the synchronization input of register 2 and writes the address A _k ^ij (e + 1) ^* into it by a trailing edge. The address from the output of register 2 is fed to the address input of block 1 and provides the reading of the first command of the (e + 1) th section. The first pulse t ₂ from the second output of the synchronization block 10 resets the buffer register 7 and, simultaneously arriving through the OR element 16 to the synchronization input of the register 3, commits the command read from block 1 in this register. Thus, the (ij) th module starts to execute the (e + 1) th section of the k-th program. The command recorded in register 3 can have either the format Ф ₂ , or the format Ф ₃ , or the format Ф ₄ (Fig. 4). Accordingly, the (ij) th module can go into one of three possible modes - A, B or C.

Mode C. The module goes into this mode after writing to the register 3 commands format F ₄ (Fig. 4). The operation of the module in mode C is reduced to indicating the completion of the k-th program and the transition to a passive state. At the output 3.8 of register 3 (Fig. 1), a single signal is formed - the mark of the end of the program (M _CP ), at the output of 3.7, as in mode B, a single mark of the end of the section M _k appears. At all other outputs of register 3, a zero signal level is formed.

Zero signals from outputs 3.5 and 3.6 of register 3 form a zero signal level at the outputs of decoders 8 and 9. A single label M _CP from output 3.8 of register 3 is fed to the control inputs of switch 6 and sets it to receive the next CPC from input 23 of the module.

Simultaneously, the transition of the signal at the output of 3.7 register 3 from zero to unity excites a pulse at the output of the one-shot 18. This pulse is supplied to the third input of the synchronization unit 10, puts the trigger 31 (Fig. 2) to the zero state, and thereby prohibits the formation of synchronization pulses t ₁ and t ₂ at the outputs of block 10 synchronization (Fig. 1). Reading commands from block 1 stops.

 In a similar way, the operation of other ISS modules is also completed. The execution of the k-th program as a whole ends after the transition to the passive state of the last of the modules. After that, the network can proceed to the next program.

 We will evaluate the advantages of the proposed technical solution over the prototype.

 Initially, we will evaluate from the point of view of the efficiency of the process of inter-modular transfer of control when starting groups of parallel sections (in the analysis of the prototype, the numbering is carried out in accordance with the description of the prototype).

 In the prototype, intermodular control transfer provides for the exchange of messages containing control transfer addresses, and can be carried out in two ways.

 Method 1. The module - the initiator of the control transfer (let this module be number ij) sequentially reads several communication commands (in the prototype these are C or B format commands), each of which ensures the formation and delivery of one message and, accordingly, the launch of one of the required parallel plots.

Method 2. The module m _ij reads the communication command C (or B if the (i. J) th module is to pass into the passive state), which ensures the launch of a parallel section, assigned, for example, to the module with the number i ₁ .j ₁ . The (i ₁ .j ₁ ) th module, in turn, after starting also reads the C command and starts the next of the required parallel sections, implemented by the (i _2. j ₂ ) th module. Further, the (i ₂ .j ₂ ) th module similarly activates the next parallel section assigned to the module with the number i ₃ .j ₃ . In the end, all parallel sections will be activated.

где

- время передачи сообщения от модуля

модулю

;
h - порядковый номер запускаемого участка;
для первого способа справедливо равенство

,

поскольку все сообщения передаются (i.j)-м модулем;
для второго способа

.Regardless of the method used, the time of intermodular control transfer when starting a group of p parallel sections (i.e., the interval between the moment of reading the first communication command and the moment of starting the last, pth section) is defined as

Where

- message transmission time from the module

module

;
h - serial number of the launched section;
for the first method, the equality

,

since all messages are transmitted by the (ij) th module;
for the second method

.

, в свою очередь, зависит от расстояния

между модулями

и

и среднего времени t₀ передачи сообщения между соседними модулями и в общем случае

где t_зап - время запуска модуля

(промежуток времени от момента поступления сообщения на вход 28 или 29 (i_h.j_h)-го модуля до момента фиксации первой команды запускаемого участка в регистре 5 команд).Time

in turn depends on the distance

between modules

and

and average time t ₀ of message transmission between neighboring modules and in the general case

where t _zap - module start time

(the time interval from the moment the message arrives at the input of the 28th or 29th (i _h .j _h ) -th module until the first command of the run section is fixed in the register of 5 commands).

являются соседними (смежными) и, соответственно,

,

В этом случае, исходя из формул (1) и (2),
T = T_min = p(t₀+t_зап). (3)
Величина t₀ представляет собой время обработки сообщения блоком 2 анализа, которое, в свою очередь, складывается из времени пребывания сообщения в блоке памяти сообщений 36, 37 или 35 (t'₀) и времени передачи сообщения из указанного блока на один из выходов блока анализа (t''₀). Величина t_зап представляет собой сумму t₀+t'_зап, где t'_зап - промежуток времени от момента выхода сообщения из блока 2 анализа до момента записи первой команды в регистр 5 команд.The lowest value of T is achieved when the modules

are adjacent (adjacent) and, accordingly,

,

In this case, based on formulas (1) and (2),
T = T _min = p (t ₀ + t _app ). (3)
The value of t ₀ represents the processing time of the message by the analysis unit 2, which, in turn, is the sum of the time the message was in the message memory 36, 37 or 35 (t ' ₀ ) and the time the message was sent from the specified block to one of the outputs of the analysis unit (t '' ₀ ). The value of t _zap is the sum of t ₀ + t ' _zap , where t' _zap is the time interval from the moment the message leaves the analysis unit 2 until the first command is written to the 5 command register.

B то же время

где K - средняя длина очереди сообщений в блоке памяти сообщений 36, 37 или 35. Считая, что τ₈≈τ₄₂ и обозначая τ₈,τ₄₂ как τ, из (4) получим окончательное выражение для T_min:
T_min ≈ pτ(2K+3). (5)
В предлагаемой сети, как показано выше, обмен сообщениями при межмодульной передаче управления отсутствует. Запуск p параллельных участков производится практически одновременно в момент появления отрицательного перепада уровня сигнала завершения группы предшествующих параллельных участков на выходах элементов И 11.q (фиг. 1). Время межмодульной передачи управления T^* не зависит от значения p и определяется скоростью распространения сигнала через цепочку элементов И 11.q различных модулей.Based on the foregoing, formula (3) can be rewritten in the form
T _min = p (2t ' ₀ + 2t'' ₀ + t' _app ). (4)
It is easy to see that the value of t ' _{zap is} close to the period of the pulses of the synchronization unit 8 (τ ₈ ), and t'' ₀ is close to the period of the pulses of the distributor 42 (τ ₄₂ ), therefore, we can assume

B same time

where K is the average length of the message queue in the message memory block 36, 37 or 35. Assuming that τ ₈ ≈τ ₄₂ and denoting τ ₈ , τ ₄₂ as τ, from (4) we obtain the final expression for T _min :
T _min ≈ pτ (2K + 3). (5)
In the proposed network, as shown above, there is no messaging during intermodular control transfer. The launch of p parallel sections is carried out almost simultaneously at the moment of the appearance of a negative level difference of the signal of completion of the group of previous parallel sections at the outputs of the elements And 11.q (Fig. 1). The intermodular control transfer time T ^* does not depend on the value of p and is determined by the speed of signal propagation through the chain of elements AND 11.q of various modules.

The value of T ^{* is the} sum of time (t ₁ ^* ) between the moment of completion of the group of previous parallel sections and the moment of formation of a single signal d _q at the output of the 29.q (1.N) -th module, delay of the block of elements NOT 36 (Δt ₃₆ ), time (t ₂ ^* ) propagation of the signal level difference from the qth output of block 36 to the last of the ISS modules to be activated, as well as the start time of the specified module (t _app ^* ), i.e. time from the moment of the difference in signal level at the input 27.q or 28.q of the module to the moment of fixing the first command in register 3. In the extreme case, when the last completed section is executed by the (M. 1) -th module, and the last of the parallel sections launched - (1.N) -th module (Fig. 3),
t ₁ ^* = t ₁ ^* (max) - t ₂ ^* - t ₂ ^* (max) = (M + N - 2) t ₀ ^* ,
where t ₀ ^* is the delay of the signal passing through the ISS module from input 27.q or 28.q to output 29.q.

поэтому
t $\genfrac{}{}{0ex}{}{\text{*}}{\text{1}}$ (max) = t $\genfrac{}{}{0ex}{}{\text{*}}{\text{2}}$ (max) = (M+N-2)Δt_ll.q.
Как и в прототипе, t_зап ^* приближенно равно периоду следования импульсов синхронизации, который, очевидно, может быть принят равным τ. B то же время Δt₃₆≈Δt_ll.q≡Δt.
Исходя из всего сказанного, наибольшее значение Т^* может быть определено как

Для обеспечения устойчивости работы модулей МКС должно выполняться условие τ ≫ Δt, например τ~20Δt(Δt~0.05τ). Поэтому, подставляя Δt = 0.05τ в (6) и учитывая (5), окончательно получим следующие соотношения:
T ≥ T_min≈pτ(2K+3), (7а)
T^*≅ T $\genfrac{}{}{0ex}{}{\text{*}}{\text{m}}$ _ax≈(0.1(M+N)+0.85)τ. (7б)
Величины p, K, M и N характеризуются одним порядком (они, как правило, не превышают 10), поэтому для приближенной оценки можно считать p = K = M = N ≡ Θ ~ 1...10. С учетом этого допущения выражения (7а) и (7б) можно переписать в виде
T ≥ T_min ≈ 2Θ²τ+3Θτ, (8а)
T^*≅ T $\genfrac{}{}{0ex}{}{\text{*}}{\text{m}}$ _ax ≈ 0.2Θτ+0,85τ. (8б)
Сравнение выражений (8а) и (8б) позволяет установить, что T_min > T_max ^*. Отсюда следует, что в общем случае T >> T^*. Таким образом, в предлагаемой МКС обеспечивается существенно более высокая оперативность межмодульной передачи управления при запуске групп параллельных участков, чем в прототипе.The value of t ₀ ^* represents the delay in the operation of the element And

so
t $\genfrac{}{}{0ex}{}{\text{*}}{\text{1}}$ (max) = t $\genfrac{}{}{0ex}{}{\text{*}}{\text{2}}$ (max) = (M + N-2) Δt _ll.q.
As in the prototype, t _app ^{* is} approximately equal to the period of the synchronization pulses, which, obviously, can be taken equal to τ. At the same time, Δt ₃₆ ≈Δt _ll.q ≡Δt.
Based on the foregoing, the largest value of T ^* can be defined as

To ensure the stability of the operation of the ISS modules, the condition τ ≫ Δt, for example, τ ~ 20Δt (Δt ~ 0.05τ), must be satisfied. Therefore, substituting Δt = 0.05τ in (6) and taking into account (5), we finally obtain the following relations:
T ≥ T _min ≈pτ (2K + 3), (7a)
T ^* ≅ T $\genfrac{}{}{0ex}{}{\text{*}}{\text{m}}$ _ax ≈ (0.1 (M + N) +0.85) τ. (7b)
The quantities p, K, M, and N are characterized by the same order of magnitude (as a rule, they do not exceed 10); therefore, for an approximate estimate, we can assume p = K = M = N ≡ Θ ~ 1 ... 10. Given this assumption, expressions (7a) and (7b) can be rewritten in the form
T ≥ T _min ≈ 2Θ ² τ + 3Θτ, (8a)
T ^* ≅ T $\genfrac{}{}{0ex}{}{\text{*}}{\text{m}}$ _ax ≈ 0.2Θτ + 0.85τ. (8b)
A comparison of expressions (8a) and (8b) allows us to establish that T _min > T _max ^* . It follows that in the general case T >> T ^* . Thus, the proposed ISS provides a significantly higher efficiency of intermodular control transfer when starting groups of parallel sections than in the prototype.

 Along with increasing the efficiency of intermodular control transfer, the proposed solution can significantly reduce the complexity of the ISS module.

 Since the intermodular interaction in the ISS does not involve the exchange of messages, respectively, storage and selection of message routes are not required, analysis unit 2 can be excluded from the module (here the numbering is carried out in accordance with the prototype description) containing three message memory blocks (each of which includes a group from ~ 10 registers, a demultiplexer and several groups of ~ 10 logic elements), a constant generator 39, a block 40 for selecting the direction of transmission of the message, as well as a pulse distributor 42 and a number of other elements ov. In addition, the module 3 excludes synchronization control unit 3 of parallel sections, which includes two separate memory blocks of synchronization conditions (blocks 55 and 56) and a number of other elements. Instead of the indicated blocks and elements, the correspondence vector register 5 (here the numbering is given in accordance with the ISS description), decoders 8 and 9, buffer register 7, block of OR elements 14, three groups of n logical elements (the number of logical elements n represents is the maximum number of synchronization vertices in implemented programs, which in most cases does not exceed 50).

 The total complexity of all input elements, taking into account the corresponding relationships, is significantly lower than the total complexity of blocks 2 and 3 of the prototype. Thus, a significant simplification of the ISS module is achieved. Despite the simplification of the modules, the proposed ISS has all the functionality of the prototype, allowing, in particular, to launch and synchronize arbitrary groups of program sections without restrictions on the way of their intermodular distribution.

 Thus, based on the foregoing, the present invention provides a solution to the claimed technical problem, namely: it allows to increase the efficiency of inter-module transmission in a microcontroller network when starting groups of parallel sections of programs while simplifying the modules. This, in turn, helps to increase the overall speed of the ISS and reduce the complexity of its industrial production.

Claims (2)

1. A microcontroller network containing M • N modules of the same type combined into a matrix structure, where N is the number of modules in a row of the network matrix structure, M is the number of lines, with each module including a program memory block, address register, instruction register, logical multiplexer conditions, the address switch, synchronization unit, from the first to the third elements OR, and the input of the operation code of the module is connected to the first information input of the address switch, the output of which is connected to the information input of the address register, the output of which is connected is connected to the address input of the program memory block, the output of which is connected to the information input of the command register, the output of the end of the program label is connected to the control inputs of the address switch, the outputs of the logical condition code and the modifiable bit of the address of the command register are connected to the control and the first information inputs of the logic condition multiplexer, respectively , the second information input of which is connected to the input of the logical conditions of the module, the first input of the synchronization unit is connected to the input of the start of the module, o characterized in that it additionally contains a block of elements NOT, and each module additionally includes a register of the correspondence vector, a buffer register, the first and second decoders of the synchronization vertex number, the first and second groups of AND elements, the group of OR elements, the block of OR elements, the first and second single vibrators, delay element, and the output of the non-modifiable part of the address of the command register in combination with the output of the multiplexer of logical conditions are connected to the first input of the block of OR elements and to the information input of the buffer a histra, the output of which is connected to the second input of the block of OR elements, the output of which is connected to the second information input of the address switch, the output of the microoperations of the command register is connected to the output of the microoperations of the module, the input of the correspondence vector of the module is connected to the information input of the register of the correspondence vector, the outputs from the first to n- whose (where n is the maximum number of synchronization vertices in the programs being implemented) are connected to the first inputs of the elements of the OR group from the first to the n-th, respectively, the first output of the sync vertex number lowering the command register is connected to the input of the first decoder of the synchronization vertex number, the outputs from the first to the nth of which are connected to the second inputs of the elements of the OR group from the first to the nth, respectively, the outputs of which are connected to the first inputs of the elements of the first group from the first to n- respectively, the inputs of the first group of synchronization inputs of the module from the first to the n-th are connected to the second inputs of the elements And of the first group from the first to the n-th, respectively, the outputs of which are connected to the outputs of the group of the synchronization outputs of the module from the first nth, respectively, the second output of the synchronization vertex number of the command register is connected to the input of the second decoder of the synchronization vertex number, the first to nth outputs of which are connected to the first inputs of the elements And of the second group from the first to the nth, respectively, the inputs of the second group of synchronization inputs modules from the first to the n-th are connected to the third inputs of the elements And the first group from the first to the n-th, respectively, the outputs of which are connected to the second inputs of the elements And the second group from the first to the n-th, respectively, the outputs of which are connected to odes of the first OR element from the first to the n-th respectively, the output of which is connected to the synchronization input of the buffer register and to the input of the first one-shot, the output of which is connected to the reset input of the command register and to the second input of the synchronization block, the first output of which is connected to the first input of the second element OR, the output of which is connected to the synchronization input of the address register, the output of the end mark of the section of the command register is connected to the input of the second one-shot, the output of which is connected to the third input of the synchronization block, the second the output of which is connected to the reset input of the buffer register and to the first input of the third OR element, the module settings input is connected to the second input of the second OR element, with the synchronization register register input of the correspondence vector, as well as with the input of the delay element, the output of which is connected to the second input of the third OR element whose output is connected to the synchronization input of the command register, the group of synchronization outputs of the (1, N) -th module is connected to the inputs of the block of the element NOT, the outputs of which are connected to the first group of synchronization inputs (i. 1) th module,

and to the second group of synchronization inputs (MJ) of the module,

group of synchronization outputs of the (α, β) -th module,

connected to the first group of synchronization inputs (α.β + 1) of the module and to the second group of synchronization inputs (α-l.β) of the module, the group of synchronization outputs (l.β) of the module is connected to the first group of synchronization inputs (l.β + l) -th module, the group of synchronization outputs of the (α, N) -th module is connected to the second group of synchronization inputs of the (α-lN) -th module.  2. The network according to claim 1, characterized in that the synchronization unit contains a pulse generator, a control trigger, a trigger, the first and second AND elements, an OR element, the first and second inputs of which are the first and second inputs of the block, respectively, and the output is connected to the input installation of the control trigger, the reset input of which is the third input of the block, and the direct output is connected to the input of the pulse generator, the output of which is connected to the first inputs of the first and second elements And, as well as with the counting input of the trigger, the direct and inverse outputs of which th connected to the second inputs of the first and second AND gates, respectively, the outputs of which are first and second output block, respectively.

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