RU2176129C1 - Method and device for compressing infinite- alphabet character string being coded to form binary coded character string - Google Patents

Abstract

FIELD: electrical communications. SUBSTANCE: method and device are designed to compress digital messages for their transmission and storage such as voice, sound, television, facsimile, and the like messages converted to digital form. Proposed method involves pre-sampling infinite-alphabet character string being coded, organizing approximating strings to be coded, coding these strings, determining length of each approximating coded string and comparing it with preset maximum permissible length, erasing strings whose length exceeds maximum permissible value, selecting string closest to that coded out of remaining strings, and taking this string as binary-coded character string. EFFECT: reduced time for coded string transmission over communication channel or reduced space requirement for coded string storage. 11 cl, 29 dwg

Description

 The proposed technical solutions are united by a single inventive concept and relate to the field of telecommunications, namely to the technique of compressing discrete messages for their transmission and storage, such as speech, sound, television, facsimile, etc. converted to digital form. messages.

 The claimed invention can be used to reduce the transmission time of the encoded sequence of binary symbols over the communication channel or to reduce the required volume of storage devices for the encoded sequence of binary symbols.

 A known method of compressing an encoded sequence of characters from an infinite alphabet into an encoded sequence of binary characters, described, for example, in the textbook: A.G. Zyuko, D.D. Klovsky, V.I. Korzhik, M.V. Nazarov "Theory of electrical communication." - M.: Radio and Communications, 1999, pp. 24-25. It consists in reading out the next character of the encoded sequence, consisting of k characters of the infinite alphabet, comparing it with the characters of the ordered m-ary alphabet and choosing from them the closest to the next character of the encoded sequence, which is converted into binary representation and written into the encoded sequence of binary characters. This method is known as a pulse-code modulation method of pre-sampled sequences of continuous values.

 There is also a method of compressing a coded sequence of infinite alphabet characters into a coded sequence of binary characters, described, for example, in the book: Banquet V.L., Dorofeev V.M. "Digital methods in satellite communications." - M.: Radio and communication, 1982, p. 98. It consists in reading out the next character of the encoded sequence, consisting of k characters of the infinite alphabet, comparing it with the predicted value of the next character of the encoded sequence and writing a zero binary character into the encoded sequence of binary characters, if the predicted value is greater than or equal to the value of the next character of the encoded sequence. If the predicted value is less than the value of the next character of the encoded sequence, then a single binary symbol is written into the encoded sequence of binary symbols. This method is known as a delta modulation method of pre-sampled sequences of continuous values.

 A disadvantage of the known methods for compressing the encoded sequence from infinite alphabet characters to the encoded binary character sequence is the relatively long transmission time of the encoded binary character sequence over the communication channel or the relatively large required storage capacity of the encoded sequence. This is due to the fact that the known methods are not able to compress an encoded sequence having a probability P of its occurrence into an encoded sequence of binary symbols of length L bits less than the value of P logP, as described, for example, in the book: R.E. Krichevsky "Compression and information search" - M.: Radio and communications, 1988, p. 6.

 Known devices for compressing an encoded sequence from infinite alphabet characters into an encoded binary character sequence are described, for example, in the book by McHole J., Rukos S., Guiche G. Vector quantization in speech encoding. - TIIER, 1985, t. 73, N 11, p. 19-61. These devices include blocks for converting the next character of the encoded sequence to the nearest character of the ordered m-ary alphabet, blocks for counting the frequency of occurrence of characters of the ordered m-ary alphabet in the encoded sequence, and blocks for encoding characters of the ordered m-ary alphabet in binary characters. The device inputs are the inputs of the blocks for converting the next character of the encoded sequence to the nearest character of the ordered m-ary alphabet, the outputs of which are connected to the information inputs of the character coding blocks of the ordered m-ary alphabet into binary characters and with the information inputs of the blocks for counting the frequency of occurrence of characters of the ordered m-ary alphabet in coded sequence. The outputs of the blocks for counting the frequency of occurrence of characters of the ordered m-ary alphabet in the encoded sequence are connected to the control inputs of the blocks of encoding characters of the ordered m-ary alphabet in binary characters. The operation of these devices consists in sequentially reading the next character of the encoded sequence, converting it into the nearest character of the ordered m-ary alphabet, mapping the nearest character of the ordered m-ary alphabet into a coded sequence of binary characters according to a rule that takes into account the probability of occurrence of characters of the ordered m-ary alphabet, counted blocks counting the frequency of occurrence of the characters of the ordered m-ary alphabet in the encoded sequence.

 A disadvantage of the known devices for compressing an encoded sequence from infinite alphabet characters to an encoded binary symbol sequence is the relatively long transmission time of the encoded binary symbol sequence over the communication channel or the relatively large required storage capacity of the encoded binary symbol sequence. This is due to the fact that known devices are not able to compress an encoded sequence having a probability P of its appearance into an encoded sequence of binary symbols of length L bits less than the value of P logP, which is described, for example, in the book: R.E. Krichevsky "Compression and information search". - M.: Radio and Communications, 1988, p. 6.

The closest in technical essence to the claimed method is a known method described in US patent N 4652856, IPC ⁶ H 03 M 7/30 from 03.24.87. The prototype method consists in pre-setting the binary value of the lower coding limit of 2w binary bits, where w ≥ 2, and the binary value of the code interval with the length w of binary bits. The binary value of the lower coding limit of 2w bits is set equal to a binary number consisting of w zero bits in its integral part and from w zero bits in its fractional part and the binary value of the code interval with a length of w bits is set to a binary number consisting of unit value in its whole part and w-1 zero binary digits in its fractional part.

 Sequentially, starting from the first to the last, the next character of the encoded sequence consisting of k characters, where k ≥ 2, of the ordered m-ary alphabet, where m ≥ 2, is read and identified with i, where i = 1, 2 , ..., m, by the symbol of the ordered m-ary alphabet.

Then, the statistical parameters of the next character of the encoded sequence are calculated, for which, in the part of the encoded sequence preceding the next character of the encoded sequence, the binary number n _{i of} its occurrences, the sum Q _{j of} binary numbers of occurrences of characters of the encoded sequence preceding the next character of the encoded sequence in the ordered m-ary are determined alphabet, the sum of Q _m binary numbers of occurrences of characters of the encoded sequence preceding the last character in order the m-ary alphabet, and the binary number N of occurrences of all the characters of the ordered m-ary alphabet.

очередного символа кодируемой последовательности равным значению последовательно сдвинутого в направлении старших разрядов двоичного числа N появлений всех символов упорядоченного m-ичного алфавита в части кодируемой последовательности, предшествующей очередному символу кодируемой последовательности, на такое число γ разрядов, при котором нормализованное значение

будет находиться в предопределенном диапазоне значений. Затем устанавливают нормализованное значение

очередного символа кодируемой последовательности равным значению последовательно сдвинутого в направлении старших разрядов на γ разрядов двоичного числа n_i появлений очередного символа кодируемой последовательности в части кодируемой последовательности, предшествующей очередному символу кодируемой последовательности. После чего устанавливают нормализованное значение суммы

очередного символа кодируемой последовательности равным значению последовательно сдвинутой в направлении старших разрядов на γ разрядов суммы Q_i двоичных чисел появлений символов кодируемой последовательности, предшествующих очередному символу кодируемой последовательности в упорядоченном m-ичном алфавите, в части кодируемой последовательности, предшествующей очередному символу кодируемой последовательности. Далее устанавливают нормализованное значение суммы

очередного символа кодируемой последовательности равным значению последовательно сдвинутой в направлении старших разрядов на γ разрядов суммы Q_j,m двоичных чисел появлений символов кодируемой последовательности, предшествующих последнему символу в упорядоченном m-ичном алфавите, в части кодируемой последовательности, предшествующей очередному символу кодируемой последовательности.After that, the calculated statistical parameters N, n _i , Q _i and Q _{m of the} next character of the encoded sequence are normalized by performing the following sequence of actions: the normalized value is set

of the next character of the encoded sequence equal to the value of the binary number N of the occurrences of all characters of the ordered m-ary alphabet sequentially shifted in the direction of the most significant bits in the part of the encoded sequence preceding the next character of the encoded sequence by the number of γ bits at which the normalized value

will be in a predefined range of values. Then the normalized value is set.

the next character of the encoded sequence equal to the value of the binary digits n _i occurring sequentially shifted in the direction of the most significant bits by γ bits of the occurrence of the next character of the encoded sequence in the part of the encoded sequence preceding the next character of the encoded sequence. Then set the normalized value of the amount

of the next character of the encoded sequence equal to the value of the sum of Q _i binary numbers of occurrences of characters of the encoded sequence preceding the next character of the encoded sequence in the ordered m-ary alphabet in the part of the encoded sequence preceding the next character of the encoded sequence, sequentially shifted in the direction of the upper digits by γ bits; Next, set the normalized value of the amount

of the next character of the encoded sequence equal to the value of the sum of Q _{j, m} binary numbers of occurrences of characters of the encoded sequence preceding the last character in the ordered m-ary alphabet, in the part of the encoded sequence preceding the next character of the encoded sequence, sequentially shifted in the direction of the upper digits by γ bits;

 The lower limit of the predetermined range of values is set equal to the binary number 0.11, and the upper limit of the predetermined range of values is set smaller than the binary number 1.1.

очередного символа кодируемой последовательности уточняют двоичные значения нижней границы кодирования и кодового интервала выполнением следующей последовательности действий.Then, according to the normalized values of the statistical parameters

the next character of the encoded sequence, the binary values of the lower encoding boundary and the code interval are specified by performing the following sequence of actions.

очередного символа кодируемой последовательности меньше двоичного значения кодового интервала, то значение переменной β устанавливают в нулевое значение, иначе значение переменной β устанавливают в единичное значение. Далее, если очередной символ кодируемой последовательности не является последним символом упорядоченного m-ичного алфавита, то двоичное значение нижней границы кодирования заменяют суммой нормализованного значения суммы

очередного символа кодируемой последовательности и двоичного значения нижней границы кодирования и двоичное значение кодового интервала заменяют нормализованным значением n_i очередного символа кодируемой последовательности. Иначе, если очередной символ кодируемой последовательности является последним символом упорядоченного m-ичного алфавита, то двоичное значение нижней границы кодирования заменяют суммой нормализованного значения суммы

очередного символа кодируемой последовательности и двоичного значения нижней границы кодирования и двоичное значение кодового интервала заменяют разностью между двоичным значением кодового интервала и нормализованным значением суммы

очередного символа кодируемой последовательности. Далее, если переменная β имеет единичное значение, то двоичные значения нижней границы кодирования и кодового интервала сдвигают в направлении их старших разрядов на один разряд.If the normalized value of the amount

the next character of the encoded sequence is less than the binary value of the code interval, then the value of the variable β is set to zero, otherwise the value of the variable β is set to a single value. Further, if the next character of the encoded sequence is not the last character of the ordered m-ary alphabet, then the binary value of the lower coding boundary is replaced by the sum of the normalized value of the sum

the next character of the encoded sequence and the binary value of the lower encoding boundary and the binary value of the code interval are replaced with the normalized value n _{i of the} next character of the encoded sequence. Otherwise, if the next character of the encoded sequence is the last character of the ordered m-ary alphabet, then the binary value of the lower coding boundary is replaced by the sum of the normalized value of the sum

the next character of the encoded sequence and the binary value of the lower coding limit and the binary value of the code interval are replaced by the difference between the binary value of the code interval and the normalized value of the sum

the next character of the encoded sequence. Further, if the variable β has a unit value, then the binary values of the lower coding boundary and the code interval are shifted in the direction of their most significant bits by one bit.

 Then the unchanged part of the binary value of the lower encoding boundary is extracted and read into the encoded sequence. The allocation of the unchanged part of the binary value of the lower coding limit is performed by determining the number of high order bits of the binary value of the lower coding limit, at which the binary value of the code interval sequentially shifted in the direction of the upper bits is in a predetermined range of values.

последнего символа кодируемой последовательности, из позиций старших разрядов двоичного значения нижней границы кодирования последовательно считывают w двоичных символов в кодированную последовательность.Next, the read part of the binary value of the lower coding limit is erased, the binary value of the lower coding limit in the direction of the upper bits is shifted by the number of bits of its read part, and the binary value of the lower coding limit from the side of the lower bits is supplemented with the same number of zero binary symbols. After clarification of the binary value of the lower coding boundary by the normalized values of statistical parameters

the last character of the encoded sequence, w binary symbols are sequentially read into the encoded sequence from the high-order bits of the binary value of the lower coding boundary.

 Due to the enumerated set of essential features, the prototype method, in comparison with the known analogues, is capable of compressing a coded sequence of characters from an ordered m-ary alphabet having a probability P of its occurrence into a coded sequence of binary characters of length L bits arbitrarily close to the value of P logP.

 However, the prototype method has disadvantages.

 The prototype method has a limited scope. This is because the prototype method is capable of compressing encoded sequences consisting only of characters of an ordered m-ary alphabet, where the value of m is finite, while in practice it is often required to compress encoded sequences consisting of characters of an infinite alphabet.

 In addition, the prototype method has the disadvantage of a relatively large transmission time of the encoded sequence of binary symbols over the communication channel or the relatively large required amount of storage devices for the encoded sequence. This is due to the fact that when performing a preliminary conversion of a coded sequence consisting of k characters of an infinite alphabet into a coded sequence consisting of k characters of an ordered m-ary alphabet, the prototype method is not capable of compressing a coded sequence of characters of an ordered m-ary alphabet having the probability P of its occurrence, in an encoded sequence of binary characters of length L bits, is less than the value of P logP, as described, for example, in the book: P.E. Krichevsky "Compression and information search". - M.: Radio and Communications, 1988, p. 6.

The closest in technical essence to the claimed device is a known device described in US patent N 4652856, IPC ⁶ H 03 M 7/30 from 03.24.87. A known device - the prototype includes an identification unit, the input of which is the input of the device. The output of the identification unit is connected to the information input of the statistical parameter calculation unit, the output of the binary number N _{j of} occurrences of all characters of the ordered m-ary alphabet, in the part of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence, which is connected to the information input a first normalization unit, an output amount Q _{j, m} the numbers of occurrences of binary symbols j-th approximating encoded sequence preceding the last sim ol in an ordered m-ary alphabet in part j-th approximating encoded sequence preceding the next symbol of j-th approximating encoded sequence output amount Q _{j, i} occurrences of symbols j-th approximating encoded sequence preceding the next symbol of j-th approximating encoded sequence in the ordered m-ary alphabet in the part of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence, you binary number n _{j, i} occurrences of the next character of the jth approximating encoded sequence in the part of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence of the unit for calculating statistical parameters are connected to the information inputs of the first, second, and third registers normalizing shift. The control inputs of each of the registers of the normalizing shift are combined and connected to the output of the first normalization block. The identification output of the next character of the jth approximating encoded sequence with the last character of the ordered m-ay alphabet of the statistical parameter calculation unit is connected to the control input of the third switching unit. The output of the first register of the normalizing shift is connected to the first information input of the comparator, the outputs of the second and third registers of the normalizing shift are connected to the information inputs of the first and second registers of the right shift, and in addition to the first information inputs of the first and second switching blocks, respectively. The second information inputs of the first and second switching units are connected to the outputs, respectively, of the first and second registers of the right shift. The output of the comparator is connected to the control inputs of the first and second switching units. The output of the first switching unit is connected to the first inputs of the subtractor and the adder, the second input of the subtractor is connected to the second information input of the comparator and the output of the code interval register. The output of the second switching unit is connected to the first information input of the third switching unit, the second information input of which is connected to the output of the subtractor. The output of the third switching unit is connected to the information inputs of the second normalization unit and the first register of the left shift. The output of the second normalization block is connected to the control inputs of the first and second registers of the left shift. The information input of the second register of the left shift is connected to the output of the adder, the second input of which is connected to the output of the register of the lower coding boundary. The second information input of the register of the lower coding boundary is connected to the output of the first coding parameter memory block, the output of the first left shift register is connected to the first information input of the code interval register, the second information input of which is connected to the output of the second coding parameter memory. The write output of the second left shift register is the output of the device, the overwrite output of the second left shift register is connected to the first information input of the lower coding boundary register. The statistical parameter calculation unit, the second encoding parameter memory block and the first encoding parameter memory block are provided with an additional control input, the first normalization block, the first and second right shift registers, the second normalization block, the code interval register and the lower coding boundary register are equipped with the first and second additional control inputs, and the first, second and third registers of the normalizing shift, the first and second registers of the left shift are equipped with the first, second and third complement effective control inputs.

 Due to the above set of essential features, the prototype device, in comparison with known analogues, is capable of compressing a coded sequence of characters from an ordered m-ary alphabet that has a probability P of its appearance into a coded sequence of binary characters of length L bits arbitrarily close to the value of P logP.

 However, the prototype device has disadvantages.

 The prototype device has a limited scope. This is because the prototype device is capable of compressing encoded sequences consisting only of characters of an ordered m-ary alphabet, where the value of m is finite, while in practice it is often necessary to compress encoded sequences consisting of characters of an infinite alphabet.

 In addition, the prototype device has the disadvantage of a relatively large transmission time of the encoded sequence of binary symbols over the communication channel or the relatively large required volume of storage devices for the encoded sequence. This is due to the fact that when performing a preliminary conversion of a coded sequence consisting of k characters of an infinite alphabet into a coded sequence consisting of k characters of an ordered m-ary alphabet, the prototype device is not capable of compressing a coded sequence of characters of an ordered m-ary alphabet having the probability P of its occurrence, in an encoded sequence of binary characters of length L bits, is less than the value of P logP, as described, for example, in the book: P.E. Krichevsky "Compression and information search". - M .: Radio and communications, 1988, p. 6.

 The aim of the claimed invention is to develop a method and device for compression of the encoded sequence, allowing to expand the scope of their application when compressing not only the encoded sequence consisting of characters of the ordered m-ary alphabet, but also when compressing the encoded sequence consisting of symbols of the infinite alphabet into an encoded binary sequence to reduce the transmission time of the encoded sequence of binary symbols over the communication channel or reduce the need the volume of storage devices for the encoded sequence of binary characters due to the additional compression of the encoded sequence, in which the error introduced into the encoded sequence is acceptable for its recipients. In particular, when compressing a coded sequence of infinite alphabet characters, which in their physical essence are sequences of image elements, the human eye does not notice an error in the brightness values of image elements, if this error does not exceed 5 ... 7% of their brightness values, as described, for example, in the book of A.V. Dvorkovich, V.P. Dvorkovich, Yu.B. Zubarev et al. "Digital processing of television and computer images." - M .: Edition of the international center for scientific and technical information, 1997, p. 78.

очередного символа кодируемой последовательности уточняют двоичные значения нижней границы кодирования и кодового интервала. Выделяют и считывают в кодированную последовательность неизменяемую часть двоичного значения нижней границы кодирования, после чего стирают считанную часть двоичного значения нижней границы кодирования, сдвигают двоичное значение нижней границы кодирования в направлении старших разрядов на число разрядов его считанной части и дополняют таким же числом нулевых двоичных символов двоичное значение нижней границы кодирования со стороны младших разрядов. После уточнения двоичного значения нижней границы кодирования по нормализованным значениям статистических параметров

последнего символа кодируемой последовательности, из позиций старших разрядов двоичного значения нижней границы кодирования последовательно считывают w двоичных символов в кодированную последовательность, отличающийся тем, что предварительно формируют T, где T ≤ m^k, аппроксимирующих кодируемых последовательностей, состоящих из k символов упорядоченного m-ичного алфавита, путем выбора k символов из упорядоченного m-ичного алфавита случайным образом. Для каждой из них устанавливают двоичное значение нижней границы кодирования длиной 2w двоичных разрядов равное двоичному числу, состоящему из w нулевых двоичных разрядов в целой его части и из w нулевых двоичных разрядов в дробной его части, и устанавливают двоичное значение кодового интервала длиной w двоичных разрядов равным двоичному числу, состоящему из единичного значения в целой его части и w-1 нулевых двоичных разрядов в дробной его части.In the claimed method, the goal is achieved in that in the known method, which consists in pre-setting the binary value of the lower coding limit of 2w binary bits, where w ≥ 2, and the binary value of the code interval with a length w of binary bits. Sequentially, starting from the first to the last, the next character of the encoded sequence consisting of k characters of the alphabet is read, where k ≥ 2, sequentially, starting from the first and the last, the next character of the encoded sequence consisting of k characters of the ordered m-ary alphabet is read , where m ≥ 2, and identify it with the i-th, where i = 1, 2, ..., m, with the symbol of the ordered m-ary alphabet. The statistical parameters of the next character of the encoded sequence are calculated, for which the binary number n _{i of} its occurrences, the sum Q _{i of the} binary numbers of occurrences of characters of the encoded sequence preceding the next character of the encoded sequence in the ordered m-ary alphabet are determined in the part of the encoded sequence preceding the next character of the encoded sequence , the amount Q _m binary numbers of occurrences of symbols encoded sequence preceding the last character in the streamline nnom m-ary alphabet and a binary number N of occurrences of all symbols ordered m-ary alphabet. After that, the calculated statistical parameters N, n _i , Q _i and Q _{m of the} next character of the encoded sequence are normalized, and then by the normalized values of the statistical parameters

the next character of the encoded sequence specify the binary values of the lower bound of the coding and the code interval. The unchanged part of the binary value of the lower coding limit is extracted and read into the coded sequence, after which the erased part of the binary value of the lower coding limit is erased, the binary value of the lower coding limit is shifted in the direction of the higher bits by the number of bits of its read part, and the binary number is supplemented with the same number of zero binary symbols the value of the lower bound of the coding from the side of the least significant bits. After clarification of the binary value of the lower coding boundary by the normalized values of statistical parameters

the last character of the encoded sequence, from the high-order bits of the binary value of the lower coding boundary, w binary symbols are sequentially read into the encoded sequence, characterized in that T, where T ≤ m ^k , are approximated to the encoded sequences consisting of k characters of the ordered m-ary alphabet , by choosing k characters from the ordered m-ary alphabet randomly. For each of them, set the binary value of the lower coding boundary with a length of 2w binary digits equal to a binary number consisting of w zero binary digits in its integral part and from w zero binary digits in its fractional part, and set the binary value of the code interval with a length of w binary digits equal to binary number, consisting of a unit value in its integral part and w-1 zero binary digits in its fractional part.

 Consecutively, starting from the first to the last, the next character of the encoded sequence consisting of k characters of the infinite alphabet is read, compared with the characters of the ordered q-ary alphabet, where q ≥ m, and the one closest to the next character of the encoded sequence is selected from them, which recorded in a discrete coded sequence. To compare each next character of the encoded sequence consisting of k characters of the infinite alphabet with the characters of the ordered q-ary alphabet, the value of each character of the ordered q-ary alphabet is subtracted from the value of the next character of the encoded sequence, and the character of ordered q is selected closest to the next character of the encoded sequence -ary alphabet with the smallest positive value of the resulting difference.

 Then, from each jth, where j = 1, 2, ..., T, of the approximating encoded sequence, sequentially, starting from its first character to the last, the next character of the jth approximating encoded sequence is read and identified with the ith symbol of the ordered m-ary alphabet.

Next, the statistical parameters N _j , n _{j, i} , Q _{j, i} and Q _{j, m of the} next character of the jth approximating encoded sequence are calculated, for which purpose, in the part of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence define a binary number n _{j, i} of its occurrences, the amount Q _{j, i} binary numbers of occurrences of symbols j-th approximating encoded sequence preceding the next symbol of j-th approximating encoded sequence in an ordered m-ary Alf vite, sum of binary numbers Q _m of occurrences of symbols j-th approximating encoded sequence preceding the last character in an ordered m-ary alphabet and a binary number N _j of occurrences of all symbols ordered m-ary alphabet.

очередного символа j-й аппроксимирующей кодируемой последовательности равным значению последовательно сдвинутого в направлении старших разрядов двоичного числа N появлений всех символов упорядоченного m-ичного алфавита в части j-й аппроксимирующей кодируемой последовательности, предшествующей очередному символу j-й аппроксимирующей кодируемой последовательности, на такое число γ разрядов, при котором нормализованное значение

будет находиться в предопределенном диапазоне значений. Нижний предел предопределенного диапазона значений устанавливают равным двоичному числу 0.11, а верхний предел предопределенного диапазона значений устанавливают меньшим двоичного числа 1.1. Затем устанавливают нормализованное значение

очередного символа j-й аппроксимирующей кодируемой последовательности равным значению последовательно сдвинутого в направлении старших разрядов на γ разрядов двоичного числа n_j,i появлений очередного символа j-й аппроксимирующей кодируемой последовательности в части j-й аппроксимирующей кодируемой последовательности, предшествующей очередному символу j-й аппроксимирующей кодируемой последовательности. После чего устанавливают нормализованное значение суммы

очередного символа j-й аппроксимирующей кодируемой последовательности равным значению последовательно сдвинутой в направлении старших разрядов на γ разрядов суммы Q_j,i двоичных чисел появлений символов j-й аппроксимирующей кодируемой последовательности, предшествующих очередному символу j-й аппроксимирующей кодируемой последовательности в упорядоченном m-ичном алфавите, в части j-й аппроксимирующей кодируемой последовательности, предшествующей очередному символу j-й аппроксимирующей кодируемой последовательности. Далее устанавливают нормализованное значение суммы

очередного символа j-й аппроксимирующей кодируемой последовательности равным значению последовательно сдвинутой в направлении старших разрядов на γ разрядов суммы Q_j,m двоичных чисел появлений символов j-й аппроксимирующей кодируемой последовательности, предшествующих последнему символу в упорядоченном m-ичном алфавите, в части j-й аппроксимирующей кодируемой последовательности, предшествующей очередному символу j-й аппроксимирующей кодируемой последовательности.Then, the statistical parameters N _j , n _{j, i} , Q _{j, i} and Q _{j, m of the} next character of the jth approximating encoded sequence are normalized by the following sequence of actions. Set the normal value.

of the next character of the jth approximating encoded sequence equal to the value of the binary number N of sequences of all characters of the ordered m-ary alphabet sequentially shifted in the direction of the upper digits in the part of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence by such a number γ bits at which the normalized value

will be in a predefined range of values. The lower limit of the predetermined range of values is set equal to the binary number 0.11, and the upper limit of the predetermined range of values is set smaller than the binary number 1.1. Then the normalized value is set.

of the next character of the jth approximating encoded sequence equal to the value of the binary digit n _{j, i} occurrences of the next character of the jth approximating encoded sequence in the part of the jth approximating encoded sequence preceding the next character of the jth approximating coded sequence. Then set the normalized value of the amount

of the next character of the jth approximating encoded sequence equal to the value of the sum of Q _{j, i} binary numbers of occurrences of symbols of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence in the ordered m-ary alphabet, sequentially shifted in the direction of the upper digits by γ bits , in the part of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence. Next, set the normalized value of the amount

of the next character of the jth approximating encoded sequence equal to the value of the sum of Q _{j, m} binary numbers of occurrences of symbols of the jth approximating encoded sequence preceding the last character in the ordered m-ary alphabet, in part of the jth the approximating encoded sequence preceding the next character of the jth approximating encoded sequence.

очередного символа j-й аппроксимирующей кодируемой последовательности j-е двоичные значения нижней границы кодирования и кодового интервала уточняют выполнением следующей последовательности действий. Если нормализованное значение суммы

очередного символа j-й аппроксимирующей кодируемой последовательности меньше j-го двоичного значения кодового интервала, то значение переменной β устанавливают в нулевое значение, иначе значение переменной β устанавливают в единичное значение. Далее, если очередной символ j-й аппроксимирующей кодируемой последовательности не является последним символом упорядоченного m-ичного алфавита, то j-е двоичное значение нижней границы кодирования заменяют суммой нормализованного значения суммы

очередного символа j-й аппроксимирующей кодируемой последовательности и j-го двоичного значения нижней границы кодирования и j-е двоичное значение кодового интервала заменяют нормализованным значением

очередного символа j-й аппроксимирующей кодируемой последовательности. Иначе, если очередной символ j-й аппроксимирующей кодируемой последовательности является последним символом упорядоченного m-ичного алфавита, то j-е двоичное значение нижней границы кодирования заменяют суммой нормализованного значения суммы

очередного символа j-й аппроксимирующей кодируемой последовательности и j-го двоичного значения нижней границы кодирования и j-е двоичное значение кодового интервала заменяют разностью между j-м двоичным значением кодового интервала и нормализованным значением суммы

очередного символа j-й аппроксимирующей кодируемой последовательности. Далее, если переменная β имеет единичное значение, то j-е двоичные значения нижней границы кодирования и кодового интервала сдвигают в направлении их старших разрядов на один разряд.Then, according to the normalized values of the statistical parameters

of the next character of the jth approximating encoded sequence, the jth binary values of the lower coding boundary and the code interval are specified by performing the following sequence of actions. If the normalized value of the amount

the next character of the jth approximating encoded sequence is less than the jth binary value of the code interval, then the value of the variable β is set to zero, otherwise the value of the variable β is set to a single value. Further, if the next character of the jth approximating encoded sequence is not the last character of the ordered m-ary alphabet, then the jth binary value of the lower coding boundary is replaced by the sum of the normalized value of the sum

the next character of the jth approximating encoded sequence and the jth binary value of the lower coding boundary and the jth binary value of the code interval are replaced with the normalized value

the next character of the jth approximating encoded sequence. Otherwise, if the next character of the jth approximating encoded sequence is the last character of the ordered m-ary alphabet, then the jth binary value of the lower coding boundary is replaced by the sum of the normalized value of the sum

the next character of the jth approximating encoded sequence and the jth binary value of the lower coding boundary and the jth binary value of the code interval are replaced by the difference between the jth binary value of the code interval and the normalized value of the sum

the next character of the jth approximating encoded sequence. Further, if the variable β has a unit value, then the jth binary values of the lower coding boundary and the code interval are shifted in the direction of their highest bits by one bit.

 Then, the unchanged part of the jth binary value of the lower encoding boundary is extracted and read into the jth approximating encoded sequence. The unchanging part of the jth binary value of the lower coding boundary is extracted by determining the number of high order bits of the jth binary value of the lower coding limit, at which the jth binary value of the code interval is sequentially shifted in the direction of the high bits, in a predetermined range of values.

 Then, the read part of the jth binary value of the lower coding boundary is erased, the jth binary value of the lower coding boundary is shifted in the direction of high bits by the number of bits of its read part, and the same number of zero binary symbols is supplemented by the jth binary value of the lower coding boundary from the side lower digits.

последнего символа j-й аппроксимирующей кодируемой последовательности, из позиций старших разрядов j-го двоичного значения нижней границы кодирования последовательно считывают w двоичных символов в j-ю аппроксимирующую кодированную последовательность.After clarifying the j-th binary value of the lower coding boundary by the normalized values of statistical parameters

of the last character of the jth approximating encoded sequence, w binary symbols are sequentially read from the high-order bits of the jth binary value of the lower coding boundary into the jth approximating encoded sequence.

Then determine and compare the length L _{j of} each j-th approximating encoded sequence with a predetermined maximum permissible length L _PR A predetermined maximum permissible length L _pr set at least w + 1 binary digits. Next, the jth approximating encoded sequences for which the lengths L _{j of their} corresponding approximating encoded sequences exceed the maximum permissible length L _CR are erased.

 After that, the remaining approximating encoded sequences are compared with the discrete encoded sequence, the closest to the discrete encoded sequence is selected from them, and the approximating encoded sequence corresponding to the selected approximating encoded sequence is taken as a coded binary symbol sequence. To compare each remaining approximating encoded sequence with a discrete encoded sequence, the value of the next symbol of a discrete encoded sequence is subtracted from the values of each successive symbol of the remaining approximated encoded sequence, the absolute values of the differences obtained are summed, and the remaining approximated encoded sequence is selected closest to the discrete encoded sequence with the smallest sum of received differences.

Due to the new set of essential features due to the formation of approximating encoded sequences, replacing the encoded sequence consisting of symbols of the infinite alphabet with a discrete encoded sequence consisting of characters of the q-ary alphabet, and the subsequent replacement of the discrete encoded sequence by such an approximating encoded sequence, which is compressed in approximating encoded sequence with a length of not more than the maximum permissible length L _CR and cat At the same time, it is closest to the discrete coded sequence, which reduces the transmission time of the encoded sequence over the communication channel or reduces the required storage capacity of the encoded sequence.

In the claimed device, the goal is achieved by the fact that in the known device containing an identification unit, the output of which is connected to the information input of the statistical parameter calculation unit, the output of the binary number N _{j of} occurrences of all symbols of the ordered m-ary alphabet in the part of the jth approximating encoded sequence, preceding the next character of the jth approximating encoded sequence, connected to the information input of the first normalization block. The output of the sum of Q _{j, m} binary numbers of occurrences of the symbols of the jth approximating encoded sequence preceding the last character in the ordered m-ary alphabet in the part of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence, the output of the sum Q _{j, i} occurrences of characters of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence in the ordered m-ary alphabet in the part of the jth approximation simulating the encoded sequence preceding the next character of the jth approximating encoded sequence and the output of the binary number n _{j, i} occurrences of the next character of the jth approximating encoded sequence in the part of the jth approximating encoded sequence calculations of statistical parameters are connected to the information inputs, respectively, of the first, second and third registers of normalizing shear ha. The control inputs of the first, second and third registers of the normalizing shift are combined and connected to the output of the first normalization block, the identification output of the next character of the jth approximating encoded sequence with the last character of the ordered m-ary alphabet of the statistical parameter calculation unit is connected to the control input of the third switching unit. The output of the first register of the normalizing shift is connected to the first information input of the comparator, the outputs of the second and third registers of the normalizing shift are connected to the information inputs of the first and second registers of the right shift, and in addition to the first information inputs, respectively, of the first and second switching units, and the second information the inputs of the first and second switching units are connected to the outputs, respectively, of the first and second registers of the right shift. The output of the comparator is connected to the control inputs of the first and second switching units, the output of the first switching unit is connected to the first inputs of the subtractor and adder. The second input of the subtractor is connected to the second information input of the comparator and the output of the code interval register, the output of the second switching unit is connected to the first information input of the third switching unit, the second information input of which is connected to the output of the subtractor. The output of the third switching unit is connected to the information inputs of the second normalization unit and the first register of the left shift, the output of the second normalization unit is connected to the control inputs of the first and second registers of the left shift. The information input of the second register of the left shift is connected to the output of the adder, the second input of which is connected to the output of the register of the lower coding boundary, the first information input of which is connected to the output of the rewriting of the second register of the left shift. The second information input of the register of the lower coding boundary is connected to the output of the first coding parameter memory block. The output of the first left shift register is connected to the first information input of the code interval register, the second information input of which is connected to the output of the second coding parameter memory. The unit for calculating statistical parameters, the first and second blocks of memory of the encoding parameters are provided with an additional control input, the first and second normalization blocks, the first and second registers of the right shift, the code interval register and the register of the lower encoding boundary are equipped with the first and second additional control inputs, and the first, second and the third registers of the normalizing shift, the first and second registers of the left shift are equipped with the first, second and third additional control inputs to which control signals generated by the control unit that is not part of the claimed device. In addition, a discrete coded sequence unit has been introduced, the information input of which is the input of the device, and its output is connected to the first information input of the selection unit, the second information input of which is connected to the first output of the switch, the second output of which is connected to the input of the identification unit. The information input of the switch is connected to the output of the memory block of the approximating encoded sequences, the selection input of which is connected to the output of the comparison block. The output of the selection block of the approximating sequence closest to the encoded one is connected to the control input of the memory block of the approximating encoded sequences, the recording input and the counting input of which are connected to the recording output and the counting output, respectively, of the second left shift register. The read output of the memory block of the approximating encoded sequences is the information output of the device, the comparison output of the memory block of the approximating encoded sequences is connected to the first information input of the comparison block, the second information input of which is connected to the output of the memory block of the maximum permissible length, with the switch, the comparison block and the memory block of the maximum permissible the lengths are provided with an additional control input, and the discrete coded sequence block, the block Selecting the memory block approximating encoded sequences and a memory unit sequences approximating the encoded with first and second complementary control inputs, which receive control signals generated by the control unit, not forming part of the claimed device.

Due to the new set of essential features due to the additional introduction of a discrete coded sequence block, a memory block of approximating coded sequences, a selection block, a memory block of approximating coded sequences, a comparison block and a maximum permissible length memory block that perform the actions of replacing a coded sequence consisting of infinite symbols alphabet, on a discrete encoded sequence consisting of characters of the m-ary alphabet and, followed by replacement of the latter to such an approximating encoded sequence, which is compressed in approximating the encoded sequence with a length of not more than the maximum allowable length L _ave and which simultaneously is the closest to a discrete encoded sequence decreases the transmission encoded sequence via a communication channel or the requested volume is reduced coded sequence storage devices.

 The analysis of the prior art by the applicant has made it possible to establish that there are no analogues that are characterized by sets of features identical to all the features of the claimed method and device for compressing the encoded sequence from infinite alphabet characters into an encoded sequence of binary characters. Therefore, each of the claimed inventions meets the condition of patentability "Novelty".

 The results of the search for known solutions in this and related fields of technology in order to identify features that match the distinctive features of the prototypes of each claimed invention showed that they do not follow explicitly from the prior art. From the prior art determined by the applicant, the influence of the provided for by the essential features of each of the claimed inventions on the achievement of the specified technical result is not revealed. Therefore, each of the claimed inventions meets the condition of patentability "Inventive step".

The claimed objects of the invention are illustrated by drawings, in which:
- in FIG. 1 - oscillograms explaining the essence of the proposed method for compressing an encoded sequence from infinite alphabet characters into an encoded sequence of binary characters;
- in FIG. 2 is an algorithm for compressing an encoded sequence from infinite alphabet characters into an encoded binary symbol sequence according to the claimed method;
- in FIG. 3 - values of the statistical parameters of the next character of the encoded sequence according to the prototype method;
- in FIG. 4 - values of encoding parameters during compression of the encoded sequence from the characters of the ordered m-ary alphabet into an encoded sequence of binary symbols according to the prototype method;
- in FIG. 5 - values of the statistical parameters of the next character of the encoded sequence according to the proposed method;
- in FIG. 6 - values of encoding parameters during compression of the encoded sequence from the characters of the ordered m-ary alphabet into an encoded sequence of binary symbols according to the proposed method;
- in FIG. 7 is a structural diagram of a device for compressing an encoded sequence of infinite alphabet characters into an encoded binary symbol sequence;
- in FIG. 8 is a block diagram of a block of discrete encoded sequence 1;
- in FIG. 9 is a block diagram of a voltage reference module 1.2.1;
- in FIG. 10 is a block diagram of a memory block of approximating encoded sequences 2;
- in FIG. 11 is a structural diagram of a switch 3;
- in FIG. 12 is a structural diagram of a controlled switch 3.1;
- in FIG. 13 is a block diagram of a selection block 4 of an approximating sequence closest to the encoded one;
- in FIG. 14 is a structural diagram of an identification unit 5;
- in FIG. 15 is a structural diagram of a unit for calculating statistical parameters 6;
- in FIG. 16 is a structural diagram of a first normalization block 7;
- in FIG. 17 is a structural diagram of a first register of normalizing shift 8;
- in FIG. 18 is a structural diagram of a first register of a right shift 11;
- in FIG. 19 is a structural diagram of a first switching unit 15;
- in FIG. 20 is a structural diagram of a second normalization block 18;
- FIG. 21 is a block diagram of a code slot register 22;
- in FIG. 22 is a block diagram of a first left shift register 23;
- in FIG. 23 is a structural diagram of a second left shift register 24;
- in FIG. 24 is a block diagram of a memory block of approximating encoded sequences 26;
- in FIG. 25 is a block diagram of a switching module 26.3;
- in FIG. 26 is a block diagram of a first multiplexing module 26.7;
- in FIG. 27 is a block diagram of a second multiplexing module 26.8;
- in FIG. 28 is a block diagram of a comparison unit 27;
- in FIG. 29 is a timing chart explaining the essence of the operation of a device for compressing a coded sequence of infinite alphabet characters into an encoded binary character sequence.

 The implementation of the proposed method is explained as follows.

 For the timely transmission of encoded sequences from infinite alphabet characters over communication channels or for their storage in storage devices with a limited permissible volume of storage devices, they are preliminarily converted into encoded sequences consisting of characters of an ordered m-ary alphabet, which are then compressed into coded sequences of binary symbols, which allows to reduce the transmission time of the encoded sequence over the communication channel or the required volume of encoder storage devices constant sequence. Preliminary conversion of encoded sequences from infinite alphabet characters to encoded sequences from ordered m-ary alphabet characters is performed due to the impossibility of processing infinite alphabet characters by known methods of digital processing using existing computing tools with limited bit depth.

In known methods for compressing an encoded sequence from ordered m-ary alphabet characters into an encoded binary character sequence, the transmission time of the encoded sequence over the communication channel or the required storage capacity of the encoded sequence cannot be made smaller than the L / R value, in which L is the length of the encoded binary sequence characters equal to the value of P logP, where P is the probability of the appearance of the encoded sequence of characters of the ordered m-ary alpha Vita, and R is the transmission rate of the encoded sequence over the communication channel or its recording in the storage device, as described, for example, in the book: R.E. Krichevsky "Compression and information search". - M .: Radio and communications, 1988, p. 6. However, the transmission time of the encoded sequence over the communication channel or the required volume of its storage devices can be made smaller than the L / R value by compressing the encoded sequences from infinite alphabet characters with an error admissible for the recipient of the encoded sequence, as described, for example, in the book by K. Shannon, "Works on Information Theory and Cybernetics." - M .: Foreign literature, 1963, p. 618. The admissibility of the indicated error of the encoded sequences is explained by the fact that, for example, the human eye does not notice image distortion if the brightness of their constituent elements, which are elements of the encoded sequences, are generally displayed with infinite values lengths are distorted by no more than 5-7%, as described in the book, for example, A. V. Dvorkovich, V. P. Dvorkovich, Yu. B. Zubarev and others. "Digital processing of television and computer images." - M .: Edition of the International Center for Scientific and Technical Information, 1997, p. 78. The type of error-tolerant encoded sequences of analog speech, sound, television, facsimile and similar messages, sampled at a sampling rate of F = 1 / T, is shown in FIG. 1 (a). The type of error-tolerant encoded sequences of digital speech, sound, television, facsimile and similar messages, sampled at a sampling rate of F = 1 / T and quantized to 2 ^m levels (2 ^m > 2), is shown in FIG. 1 (b). The type of error-tolerant encoded sequences of digital speech, sound, television, facsimile and similar messages, sampled at a sampling rate of F = 1 / T and quantized to 2 ^q levels (2 ^q > 2), where q> m, is shown in FIG. 1 (c). A view of coded binary symbol sequences is shown in FIG. 1 (g).

In FIG. 1 (d) it is shown that the length of the encoded sequence of binary symbols can be greater than the maximum permissible length L _CR , where the value of the maximum permissible length L _CR is less than the value of P logP, where P is the probability of the appearance of the encoded sequence from the characters of the ordered m-ary alphabet. Additional compression of the encoded sequence with the specified permissible error allows to reduce the transmission time of the encoded sequence over the communication channel or the required amount of storage devices for the encoded sequence. Therefore, for transferring encoded sequences over communication channels or for storing them in storage devices with a limited permissible volume of storage devices, the use of compressing an encoded sequence from infinite alphabet characters to an encoded binary character sequence with loss of information that is not essential for the recipient provides a significant reduction in transmission time or the volume of their storage devices.

In the claimed method, T is preformed, where T ≤ m ^k , m ≥ 2, k ≥ 2, approximating encoded sequences consisting of k characters of an ordered m-ary alphabet. The larger the number of T approximating encoded sequences formed, the higher the probability of choosing among them the closest to the encoded sequence. Each approximating encoded sequence is formed by choosing k characters from the ordered m-ary alphabet in a random manner, described, for example, in the book: D. Knut "The Art of Computer Programming." - M .: Mir, 1977, v. 2, p. 22. View T approximating encoded sequences shown in Fig. 1 (d).

 For each approximating encoded sequence, a binary value of the lower coding limit of 2w bits is set equal to a binary number consisting of w zero bits in its integral part and from w zero bits in its fractional part and a binary value of the code interval with a length of w binary bits is set equal to a binary number consisting of a unit value in its whole part and w-1 zero binary digits in its fractional part. Known methods for establishing a binary value of a lower coding limit of 2w binary bits and a binary code interval of a length w of binary bits are described, for example, in Rissanen J., Langdon G. Universal modeling and coding. // IEEE Transaction on Information Theory. - Vol. IT-27, 1981, N 1, Jan., p. 12-23.

 Successively, starting from its first character to the last, the next character of the encoded sequence consisting of k characters of the infinite alphabet is read. Known methods for sequentially reading the next character from the encoded sequence are described, for example, in the textbook: A. G. Zyuko, D. D. Klovsky, V. I. Korzhik, M. V. Nazarov “Theory of electrical communication”. - M .: Radio and communications, 1999, p. 26. The next character of the encoded sequence is compared with the characters of the ordered q-ary alphabet and the ones closest to the next character of the encoded sequence, which are recorded in a discrete encoded sequence, are selected from them. To compare each next character of the encoded sequence consisting of k characters of the infinite alphabet with the characters of the ordered q-ary alphabet, the value of each character of the ordered q-ary alphabet is subtracted from the value of the next character of the encoded sequence. Closest to the next character of the encoded sequence, the character of the ordered q-ary alphabet with the smallest positive value of the resulting difference is selected. Known methods for subtracting from the value of the next character of the encoded sequence of character values of the ordered q-ary alphabet are described, for example, in the textbook: A.G. Zyuko, D.D. Klovsky, V.I. Korzhik, M.V. Nazarov "Theory of electrical communication " - M .: Radio and communications, 1999, p. 52. Known methods for choosing the closest q-decimal alphabet character to the encoded sequence of characters from the smallest positive value of the resulting difference are described, for example, in D. Knut's book "The Art of Computer Programming " - M .: Mir, 1978, t. 3, p. 219. Known methods for writing characters of an ordered q-ary alphabet into a discrete coded sequence are described, for example, in the book of B.A. Kalabekov "Microprocessors and their use in transmission and processing systems". - M.: Radio and Communications, 1988, p. 34.

 Consistently, starting from its first character to the last, the next character is read from each j-th one, where j = 1, 2, ..., T, which approximates the encoded sequence. Known methods for sequentially reading the next character from an approximating encoded sequence are described, for example, in the book of B.A. Kalabekov "Microprocessors and their use in transmission and processing systems". - M.: Radio and Communications, 1988, p. 34.

 The next character of the jth approximating encoded sequence is identified with the i-th character of the ordered m-ary alphabet. To identify the next character of the jth approximating encoded sequence with the ith character of the ordered m-ary alphabet, it is sequentially compared with each of the m characters of the ordered m-ary alphabet until a match is found. Known identification methods are described, for example, in the book: W. Peterson, E. Weldon, "Codes for Correcting Errors." - M.: Mir, 1976, p. 15.

Next, calculate the statistical parameters N _j , n _{j, i} , Q _{j, i} and Q _{j, m of the} next character of the jth approximating encoded sequence. For this, in the part of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence, the binary number n _{j, i of} its occurrences is determined, as described, for example, in US patent N 4652856 of 03.24.87.

In the part of the jth approximating encoded sequence preceding its next character, the sum of Q _{j, i} binary numbers of occurrences of characters of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence in the ordered m-ary alphabet is determined, as described, for example, in US patent N 4652856 from 03.24.87.

In the part of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence, the sum of Q _m binary numbers of occurrences of characters of the jth approximating encoded sequence preceding the last character in the ordered m-ary alphabet is determined, as described, for example, in U.S. Patent No. 4,652,856 of March 24, 87.

In the part of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence, the binary number N _{j of} occurrences of all characters of the ordered m-ary alphabet is determined, as described, for example, in U.S. Patent No. 4,652,856 of 03.24.87.

очередного символа j-й аппроксимирующей кодируемой последовательности равным значению последовательно сдвинутого в направлении старших разрядов двоичного числа N появлений всех символов упорядоченного m-ичного алфавита в части j-й аппроксимирующей кодируемой последовательности, предшествующей очередному символу j-й аппроксимирующей кодируемой последовательности, на такое число γ разрядов, при котором нормализованное значение

будет находиться в предопределенном диапазоне значений. Нижний предел предопределенного диапазона значений устанавливают равным двоичному числу 0.11, а верхний предел предопределенного диапазона значений устанавливают меньшим двоичного числа 1.1. Известные способы последовательного сдвига в направлении старших разрядов двоичного числа описаны, например, в книге Б.А. Калабеков "Микропроцессоры и их применение в системах передачи и обработки". - М.: Радио и связь, 1988, стр. 10. Известные способы сравнения двоичного числа с нижним и верхним пределами предопределенного диапазона значений описаны, например, в книге Д. Кнут "Искусство программирования на ЭВМ". - М.: Мир, 1978, т. 3, стр. 219.Then, the statistical parameters N _j , n _{j, i} , Q _{j, i} and Q _{j, m of the} next character of the jth approximating encoded sequence are normalized by the following sequence of actions. Set the normal value.

of the next character of the jth approximating encoded sequence equal to the value of the binary number N of sequences of all characters of the ordered m-ary alphabet sequentially shifted in the direction of the upper digits in the part of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence by such a number γ bits at which the normalized value

will be in a predefined range of values. The lower limit of the predetermined range of values is set equal to the binary number 0.11, and the upper limit of the predetermined range of values is set smaller than the binary number 1.1. Known methods of sequential shift in the direction of the most significant bits of a binary number are described, for example, in the book B.A. Kalabekov "Microprocessors and their use in transmission and processing systems". - M.: Radio and Communications, 1988, p. 10. Known methods for comparing a binary number with the lower and upper limits of a predefined range of values are described, for example, in D. Knut's book "The Art of Computer Programming." - M.: Mir, 1978, v. 3, p. 219.

очередного символа j-й аппроксимирующей кодируемой последовательности равным значению последовательно сдвинутого в направлении старших разрядов на γ разрядов двоичного числа n_j,i появлений очередного символа j-й аппроксимирующей кодируемой последовательности в части j-й аппроксимирующей кодируемой последовательности, предшествующей очередному символу j-й аппроксимирующей кодируемой последовательности. После чего устанавливают нормализованное значение суммы

очередного символа j-й аппроксимирующей кодируемой последовательности равным значению последовательно сдвинутой в направлении старших разрядов на γ разрядов суммы Q_j,i двоичных чисел появлений символов j-й аппроксимирующей кодируемой последовательности, предшествующих очередному символу j-й аппроксимирующей кодируемой последовательности в упорядоченном m-ичном алфавите, в части j-й аппроксимирующей кодируемой последовательности, предшествующей очередному символу j-й аппроксимирующей кодируемой последовательности. Далее устанавливают нормализованное значение суммы

очередного символа j-й аппроксимирующей кодируемой последовательности равным значению последовательно сдвинутой в направлении старших разрядов на γ разрядов суммы Q_j,m двоичных чисел появлений символов j-й аппроксимирующей кодируемой последовательности, предшествующих последнему символу в упорядоченном m-ичном алфавите, в части j-й аппроксимирующей кодируемой последовательности, предшествующей очередному символу j-й аппроксимирующей кодируемой последовательности.Then the normalized value is set.

of the next character of the jth approximating encoded sequence equal to the value of the binary digit n _{j, i} occurrences of the next character of the jth approximating encoded sequence in the part of the jth approximating encoded sequence preceding the next character of the jth approximating coded sequence. Then set the normalized value of the amount

of the next character of the jth approximating encoded sequence equal to the value of the sum of Q _{j, i} binary numbers of occurrences of symbols of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence in the ordered m-ary alphabet, sequentially shifted in the direction of the upper digits by γ bits , in the part of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence. Next, set the normalized value of the amount

of the next character of the jth approximating encoded sequence equal to the value of the sum of Q _{j, m} binary numbers of occurrences of symbols of the jth approximating encoded sequence preceding the last character in the ordered m-ary alphabet, in part of the jth the approximating encoded sequence preceding the next character of the jth approximating encoded sequence.

очередного символа j-й аппроксимирующей кодируемой последовательности j-е двоичные значения нижней границы кодирования и кодового интервала уточняют выполнением следующей последовательности действий. Если нормализованное значение суммы

очередного символа j-й аппроксимирующей кодируемой последовательности меньше j-го двоичного значения кодового интервала, то значение переменной β устанавливают в нулевое значение, иначе значение переменной β устанавливают в единичное значение. Известные способы сравнения нормализованного значения суммы

очередного символа j-й аппроксимирующей кодируемой последовательности с j-м двоичным значением кодового интервала описаны, например, в книге Д. Кнут "Искусство программирования на ЭВМ". - М. : Мир, 1978, т. 3, стр. 219. Далее, если очередной символ j-й аппроксимирующей кодируемой последовательности не является последним символом упорядоченного m-ичного алфавита, то j-е двоичное значение нижней границы кодирования заменяют суммой нормализованного значения суммы

очередного символа j-й аппроксимирующей кодируемой последовательности и j-го двоичного значения нижней границы кодирования и j-е двоичное значение кодового интервала заменяют нормализованным значением

очередного символа j-й аппроксимирующей кодируемой последовательности. Иначе, если очередной символ j-й аппроксимирующей кодируемой последовательности является последним символом упорядоченного m-ичного алфавита, то j-е двоичное значение нижней границы кодирования заменяют суммой нормализованного значения суммы

очередного символа j-й аппроксимирующей кодируемой последовательности и j-го двоичного значения нижней границы кодирования и j-е двоичное значение кодового интервала заменяют разностью между j-м двоичным значением кодового интервала и нормализованным значением суммы

очередного символа j-й аппроксимирующей кодируемой последовательности. Далее, если переменная β имеет единичное значение, то j-е двоичные значения нижней границы кодирования и кодового интервала сдвигают в направлении их старших разрядов на один разряд. Известные способы сдвига в направлении старших разрядов на один разряд j-х двоичных значений нижней границы кодирования и кодового интервала описаны, например, в книге Б.А. Калабеков "Микропроцессоры и их применение в системах передачи и обработки". - М.: Радио и связь, 1988, стр. 10.Then, according to the normalized values of the statistical parameters

of the next character of the jth approximating encoded sequence, the jth binary values of the lower coding boundary and the code interval are specified by performing the following sequence of actions. If the normalized value of the amount

the next character of the jth approximating encoded sequence is less than the jth binary value of the code interval, then the value of the variable β is set to zero, otherwise the value of the variable β is set to a single value. Known methods for comparing the normalized value of a sum

the next character of the jth approximating encoded sequence with the jth binary value of the code interval are described, for example, in the book “The Art of Computer Programming” by D. Knut. - M.: Mir, 1978, v. 3, p. 219. Further, if the next character of the jth approximating encoded sequence is not the last character of the ordered m-ary alphabet, then the jth binary value of the lower coding boundary is replaced by the sum of the normalized value amounts

the next character of the jth approximating encoded sequence and the jth binary value of the lower coding boundary and the jth binary value of the code interval are replaced with the normalized value

the next character of the jth approximating encoded sequence. Otherwise, if the next character of the jth approximating encoded sequence is the last character of the ordered m-ary alphabet, then the jth binary value of the lower coding boundary is replaced by the sum of the normalized value of the sum

the next character of the jth approximating encoded sequence and the jth binary value of the lower coding boundary and the jth binary value of the code interval are replaced by the difference between the jth binary value of the code interval and the normalized value of the sum

the next character of the jth approximating encoded sequence. Further, if the variable β has a unit value, then the jth binary values of the lower coding boundary and the code interval are shifted in the direction of their highest bits by one bit. Known methods of shifting in the direction of the higher bits by one bit of j-binary values of the lower coding boundary and the code interval are described, for example, in the book of B.A. Kalabekov "Microprocessors and their use in transmission and processing systems". - M .: Radio and communications, 1988, p. 10.

 The selection of the immutable part of the jth binary value of the lower coding boundary is as follows. The unchanging part of the jth binary value of the lower coding boundary is extracted by determining the number α of the upper bits of the jth binary value of the lower coding boundary, at which the jth binary value of the code interval that is sequentially shifted in the direction of the higher bits is in a predetermined range of values. The part of the jth binary value of the lower coding boundary, which is the number α of the most significant bits, is an unchanged part of the jth binary value of the lower coding boundary. In the book, for example, Rissanen J., Langdon G. Universal modeling and coding. // IEEE Transaction on Information Theory. - Vol. IT-27, 1981, N 1, Jan., p. 12-23, it is proved that, with the indicated sequence of actions, the extracted part of the jth binary value of the lower coding boundary does not change for any subsequent readable characters of the approximating encoded sequence, which allows the unchanged part of the jth binary value to be read into the jth approximating encoded sequence lower bound coding. Known methods for isolating the unchanged part of the jth binary value of the lower encoding boundary are described, for example, in US patent N4652856 from 03.24.87.

 The unchanged part of the jth binary value of the lower encoding boundary is read into the jth approximating encoded sequence. Known methods for reading into the jth approximating encoded sequence of the unchanged part of the jth binary value of the lower encoding boundary are described, for example, in US Pat. No. 4,652,856 of 03.24.87.

 The read part of the jth binary value of the lower encoding boundary is erased. Known methods for erasing the read part of the jth binary value of the lower encoding boundary are described, for example, in the book: W. Peterson, E. Weldon, “Correcting Error Codes”. - M.: Mir, 1976, p. 17.

 Then, the jth binary value of the lower coding boundary is shifted in the direction of the higher bits by the number of bits of its read part and the jth binary value of the lower coding boundary from the side of the least significant bits is added with the same number of zero binary symbols. Known methods for shifting the jth binary value of the lower coding boundary in the direction of the higher bits by the number of bits of its read part are described, for example, in the book of B.A. Kalabekov "Microprocessors and their use in transmission and processing systems". - M.: Radio and communications, 1988, p. 10. Known methods for supplementing with the same number of zero binary characters of the jth binary value of the lower coding limit from the low order are described, for example, in the book of B.A. Kalabekov "Microprocessors and their use in transmission and processing systems". - M .: Radio and communications, 1988, p. 14.

последнего символа j-й аппроксимирующей кодируемой последовательности, последовательное считывание w двоичных символов из позиций старших разрядов j-го двоичного значения нижней границы кодирования в j-ю аппроксимирующую кодированную последовательность заключается в следующем. Уточнение j-го двоичного значения нижней границы кодирования по нормализованным значениям статистических параметров

последнего символа j-й аппроксимирующей кодируемой последовательности выполняют точно так же, как уточнение j-го двоичного значения нижней границы кодирования по нормализованным значениям статистических параметров

очередного символа j-й аппроксимирующей кодируемой последовательности. В качестве последнего символа j-й аппроксимирующей кодируемой последовательности используется наиболее редко встречающийся символ конца последовательности, поэтому для обеспечения возможности восстановления кодируемой последовательности из кодированной последовательности необходимо последовательное считывание w двоичных символов из позиций старших разрядов j-го двоичного значения нижней границы кодирования в j-ю аппроксимирующую кодированную последовательность. Известные способы последовательного считывания w двоичных символов из позиций старших разрядов j-го двоичного значения нижней границы кодирования в j-ю аппроксимирующую кодированную последовательность описаны, например, в книге Б.А. Калабеков "Микропроцессоры и их применение в системах передачи и обработки". - М.: Радио и связь, 1988, стр. 34. Вид T аппроксимирующих кодированных последовательностей представлен на фиг. 1(е).After clarifying the j-th binary value of the lower coding boundary by the normalized values of statistical parameters

the last character of the jth approximating encoded sequence, sequential reading of w binary symbols from the positions of the most significant bits of the jth binary value of the lower encoding boundary into the jth approximating encoded sequence is as follows. Refinement of the j-th binary value of the lower coding boundary by the normalized values of statistical parameters

the last character of the jth approximating encoded sequence is performed in exactly the same way as the refinement of the jth binary value of the lower coding boundary using normalized values of statistical parameters

the next character of the jth approximating encoded sequence. The last character of the end of the sequence is used as the last character of the jth approximating encoded sequence; therefore, to ensure the possibility of recovering the encoded sequence from the encoded sequence, it is necessary to sequentially read w binary symbols from the high-order positions of the jth binary value of the lower coding boundary to the jth approximating encoded sequence. Known methods for sequentially reading w binary symbols from the high-order positions of the jth binary value of the lower encoding boundary into the jth approximating encoded sequence are described, for example, in the book of B.A. Kalabekov "Microprocessors and their use in transmission and processing systems". - M .: Radio and communication, 1988, p. 34. A view of T approximating encoded sequences is shown in FIG. 1 (e).

Then determine and compare the length L _{j of} each j-th approximating encoded sequence with a predetermined maximum permissible length L _PR The determination of the length L _{j of} each j-th approximating encoded sequence consists in counting the number of bits in each j-th approximating encoded sequence. Known methods for determining the length L _{j of} each jth approximating encoded sequence are described, for example, in the book of B.A. Kalabekov "Microprocessors and their use in transmission and processing systems". - M .: Radio and communications, 1988, p. 14. Known methods for comparing the length L _{j of} each jth approximating encoded sequence with a predetermined maximum allowable length L _{pr are} described, for example, in the book by W. Peterson, E. Weldon "Codes corrective errors. " - M.: Mir, 1976, p. 52.

The establishment of a predetermined maximum permissible length L _CR is as follows. The maximum permissible length L _pr set at least w + l binary digits. With an increase in the number of binary digits equal to the maximum permissible length L _pr , the error in compressing the encoded sequence from infinite alphabet characters into the encoded binary character sequence decreases, which is described, for example, in the book by K. Shannon, "Works on Information Theory and Cybernetics." - M .: Foreign Literature, 1963, p. 618. Known methods for establishing a predetermined maximum permissible length L _{pr are} described, for example, in the book by K. Shannon, "Works on Information Theory and Cybernetics." - M.: Foreign Literature, 1963, p. 618.

The erasure of the jth approximating encoded sequences for which the lengths L _{j of their} corresponding approximating encoded sequences exceed the maximum permissible length L _CR is as follows. For each jth approximating encoded sequence, its length L _{j is} compared with the maximum permissible length L _CR , and if the value of L exceeds the value of L _CR , the jth approximating encoded sequence is erased. Known methods for erasing approximating encoded sequences are described, for example, in the book: W. Peterson, E. Weldon "Error Correcting Codes". - M .: Mir, 1976, p. 17. A view of the remaining approximating encoded sequences is shown in FIG. 1 (g).

 The remaining approximate encoded sequences are compared with a discrete encoded sequence. Known methods for comparing the remaining approximating encoded sequences with a discrete encoded sequence are described, for example, in the book: W. Peterson, E. Weldon "Error Correcting Codes". - M .: Mir, 1976, p. 52. For comparison, use the Lee metric, according to which, to compare each remaining approximating encoded sequence with a discrete encoded sequence, the value of the next symbol of the discrete encoded sequence is subtracted from the value of each subsequent character of the remaining approximated encoded sequence and for each remaining approximating encoded sequence, the absolute values of the resulting differences are summed.

 From the remaining approximating encoded sequences, the one closest to the encoded sequence corresponding to the smallest sum of the differences obtained is selected. Known methods for selecting the minimum value among several values are described, for example, in the book: D. Knut, "The Art of Computer Programming." - M .: Mir, 1978, v. 3, p. 219. An exemplary view of the selected approximating encoded sequence is shown in FIG. 1 (h).

 As the encoded sequence of binary symbols, an approximating encoded sequence corresponding to the selected approximating encoded sequence is adopted. An exemplary view of an approximating encoded sequence corresponding to a selected approximating encoded sequence adopted as a coded binary symbol sequence is shown in FIG. 1 (s). An algorithm for compressing an encoded sequence from infinite alphabet characters into an encoded binary symbol sequence according to the proposed method is shown in FIG. 2.

 In an analytical form, these actions can be written as follows.

ν = 1, 2,..., k,
X^{^} = (x $\genfrac{}{}{0ex}{}{\text{^}}{\text{1}}$ ,x $\genfrac{}{}{0ex}{}{\text{^}}{\text{2}}$ ,...,x $\genfrac{}{}{0ex}{}{\text{^}}{\text{ν}}$ ,...,x $\genfrac{}{}{0ex}{}{\text{^}}{\text{k}}$ ), ν = 1, 2,..., k,
S = (s₁, s₂,..., s_i,..., s_m), i = 1, 2,..., m,
Y_j = (y_1,j,y_2,j,...,y_ν,j,...,y_k,j), ν = 1, 2,..., k, j = 1, 2,..., T, T ≤ m^k,
Z_j = (z_1,j,z_2,j,...,z_ν,j,...,z_k,j), ν = 1, 2,..., k, j = 1, 2,..., T, T ≤ m^k,
Q_j,i = n_j,1 + n_j,2 + ... + n_j,i-1,
Q_j,m = n_j,1 + n_j,2 + ... + n_j,m-1,
N_j = n_j,1 + n_j,2 + ... +n_j,m,
0,11 ≤ 2^γ×N_j< 1,1,

Z $\genfrac{}{}{0ex}{}{\text{*}}{\text{j}}$ = argmin {d(X^{^},Y_j), j = 1,2,...,T}
при условии L_j ≤ L_пр,
где X - кодируемая последовательность, состоящая из k, где k ≥ 2, символов бесконечного алфавита,
X^ - кодируемая последовательность, состоящая из k, где k ≥ 2, символов упорядоченного q-ичного алфавита,
S - упорядоченный m-ичный алфавит, состоящий из m, где m ≥ 2, символов,
Y_j - j-я аппроксимирующая кодируемая последовательность, состоящая из k символов упорядоченного m-ичного алфавита,
Z_j - j-я аппроксимирующая кодированная последовательность двоичных символов,
Q_j,i - сумма двоичных чисел появлений символов j-й аппроксимирующей кодируемой последовательности, предшествующих очередному символу j-й аппроксимирующей кодируемой последовательности в упорядоченном m-ичном алфавите, в части j-й аппроксимирующей кодируемой последовательности, предшествующей очередному символу j-й аппроксимирующей кодируемой последовательности,
Q_j,m - сумма двоичных чисел появлений символов j-й аппроксимирующей кодируемой последовательности, предшествующих последнему символу в упорядоченном m-ичном алфавите, в части j-й аппроксимирующей кодируемой последовательности, предшествующей очередному символу j-й аппроксимирующей кодируемой последовательности,
N_j - двоичное число появлений всех символов упорядоченного m-ичного алфавита в части j-й аппроксимирующей кодируемой последовательности, предшествующей очередному символу j-й аппроксимирующей кодируемой последовательности,
γ - число разрядов, при котором значение последовательно сдвинутого в направлении старших разрядов двоичного числа N_j появлений всех символов упорядоченного m-ичного алфавита в части j-й аппроксимирующей кодируемой последовательности, предшествующей очередному символу j-й аппроксимирующей кодируемой последовательности, будет находиться в предопределенном диапазоне значений,

- нормализованные значения статистических параметров очередного символа j-й аппроксимирующей кодируемой последовательности,
C_j - j-е двоичное значение нижней границы кодирования,
A_j - j-е двоичное значение кодового интервала,
Z $\genfrac{}{}{0ex}{}{\text{*}}{\text{j}}$ - принятая в качестве кодированной последовательности двоичных символов аппроксимирующая кодированная последовательность, соответствующая выбранной аппроксимирующей кодируемой последовательности.

ν = 1, 2, ..., k,
X ^{^} = (x $\genfrac{}{}{0ex}{}{\text{^}}{\text{1}}$ , x $\genfrac{}{}{0ex}{}{\text{^}}{\text{2}}$ , ..., x $\genfrac{}{}{0ex}{}{\text{^}}{\text{ν}}$ , ..., x $\genfrac{}{}{0ex}{}{\text{^}}{\text{k}}$ ), ν = 1, 2, ..., k,
S = (s ₁ , s ₂ , ..., s _i , ..., s _m ), i = 1, 2, ..., m,
Y _j = (y _{1, j} , y _{2, j} , ..., y _{ν, j} , ..., y _{k, j} ), ν = 1, 2, ..., k, j = 1, 2 , ..., T, T ≤ m ^k ,
Z _j = (z _{1, j} , z _{2, j} , ..., z _{ν, j} , ..., z _{k, j} ), ν = 1, 2, ..., k, j = 1, 2 , ..., T, T ≤ m ^k ,
Q _{j, i} = n _{j, 1} + n _{j, 2} + ... + n _{j, i-1} ,
Q _{j, m} = n _{j, 1} + n _{j, 2} + ... + n _{j, m-1} ,
N _j = n _{j, 1} + n _{j, 2} + ... + n _{j, m} ,
0.11 ≤ 2 ^γ × N _j <1.1,

Z $\genfrac{}{}{0ex}{}{\text{*}}{\text{j}}$ = argmin {d (X ^{^} , Y _j ), j = 1,2, ..., T}
subject to L _j ≤ L _CR
where X is the encoded sequence consisting of k, where k ≥ 2, symbols of the infinite alphabet,
X ^ is the encoded sequence consisting of k, where k ≥ 2, characters of the ordered q-ary alphabet,
S is an ordered m-ary alphabet consisting of m, where m ≥ 2, characters,
Y _j is the jth approximating encoded sequence consisting of k characters of an ordered m-ary alphabet,
Z _j - the jth approximating encoded sequence of binary characters,
Q _{j, i} is the sum of the binary numbers of occurrences of the symbols of the jth approximating encoded sequence preceding the next symbol of the jth approximating encoded sequence in the part of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequences
Q _{j, m} is the sum of the binary numbers of occurrences of the characters of the jth approximating encoded sequence preceding the last character in the ordered m-ary alphabet, in the part of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence,
N _j is the binary number of occurrences of all the characters of the ordered m-ary alphabet in the part of the jth approximating encoded sequence preceding the next symbol of the jth approximating encoded sequence,
γ is the number of digits at which the value of the binary sequence number N _{j of} successively shifted in the direction of the higher digits occurrences of all symbols of the ordered m-ary alphabet in the part of the jth approximating encoded sequence preceding the next symbol of the jth approximating encoded sequence will be in a predetermined range values

- the normalized values of the statistical parameters of the next character of the jth approximating encoded sequence,
C _j is the jth binary value of the lower encoding boundary,
A _j is the jth binary value of the code interval,
Z $\genfrac{}{}{0ex}{}{\text{*}}{\text{j}}$ - adopted as an encoded sequence of binary characters approximating encoded sequence corresponding to the selected approximating encoded sequence.

 The ability to reduce the transmission time of the encoded sequence of binary symbols over the communication channel or to reduce the required amount of storage devices for the encoded sequence of binary symbols in the proposed method compared with the known prototype method can be shown as follows.

Consider the compression of an encoded sequence from infinite alphabet characters into an encoded binary character sequence. Let it be necessary to compress an encoded sequence of the form, for example, X = (x ₁ , x ₂ , x ₃ , x ₄ , x ₅ , x ₆ , #), consisting of 6 symbols of the infinite alphabet and the symbol # of the end of the encoded sequence, where x ₁ = 1.076591 ..., x ₂ = 2.295049 ...., x ₃ = 2.370069. .., x ₄ = 2,99021 ..., x ₅ = 1,7475304002 ..., x ₆ = 2,124994087. Set the maximum permissible length L _CR , for example, L _CR = 15.

Let an ordered q-ary alphabet consist of characters 0,0; 0.1; 0.2; 0.3; 0.4, 0.5, ..., 3.0. The characters of this alphabet are ordered in ascending order and neighboring characters differ from each other by 0.1. Obviously, q = 31. We choose among the characters of the ordered q-ary alphabet that are closest to the next characters of the encoded sequence:
x ^ ₁ = 1.0, x ^ ₂ = 2.2, x ^ ₃ = 2.3, x ^ ₄ = 2.9, x ^ ₅ = 1.7, x ^ ₆ = 2.1.

We form T approximating encoded sequences consisting of 6 characters of an ordered ternary (m = 3) alphabet of the form {1, 2, 3}. For example, choosing T = 2, we form Y ₁ = 1, 3, 3, 2, 1, 2, # and Y ₂ = 1, 2, 2, 3, 2, 2, #. In FIG. 3 and 4 sequentially indicate the values of the parameters during compression of the first approximating encoded sequence of the form Y ₁ = 1, 3, 3, 2, 1, 2, # using the known prototype method at w = 4. In the third column of the table shown in FIG. 4, the unchanged parts of the binary value of the lower coding boundary sequentially read into the first approximating encoded sequence are selected, which are extracted by compressing the next character of this approximating encoded sequence. From the obtained values it follows that the length of the approximating encoded sequence of binary symbols formed from the first approximating encoded sequence using the known prototype method is equal to 17 bits.

In FIG. 5 and 6 sequentially indicate the values of the parameters during compression of the second approximating encoded sequence of the form Y ₂ = 1, 2, 2, 3, 2, 2, # using the known prototype method at w = 4. From the obtained values it follows that the length of the second approximating the encoded sequence generated from the second approximating encoded sequence Y ₂ is 13 bits, which is 4 bits less than the length of the first approximating encoded sequence. It can be seen that the length of the second approximating encoded sequence, in contrast to the length of the first approximating encoded sequence, does not exceed the maximum permissible length L _CR = 15. Therefore, the second approximating encoded sequence is the remaining approximating encoded sequence.

Suppose that, while compressing a given encoded sequence, some error is admissible. The error can be determined, for example, by the Lee metric described, for example, in the book by W. Peterson, E. Weldon, "Codes for Correcting Errors." - M .: Mir, 1976, p. 52. Mathematically, the error in the Lee metric is described by the expression
d (x $\genfrac{}{}{0ex}{}{\text{^}}{\text{ν}}$ , y _νj ) = | x $\genfrac{}{}{0ex}{}{\text{^}}{\text{ν}}$ , y _νj |,
where | x $\genfrac{}{}{0ex}{}{\text{^}}{\text{ν}}$ , y _νj |, means the calculation of the absolute value of the difference between the values of x $\genfrac{}{}{0ex}{}{\text{^}}{\text{ν}}$ , y _{ν, j} ..

For the second approximating encoded sequence, the total error is
d (X ^, Y ₂ ) = d (x ^ ₁ , y _1,2 ) + d (x ^ ₂ , y _2,2 ) + d (x ^ ₃ , y _3,2 ) + d (x ^ ₄ , y _4,2 ) + d (x ^ ₅ , y _5,2 ) + d (x ^ ₆ , y _6,2 ) = 1,0.

 To compress the encoded sequences of analog speech, sound, television, fax and similar messages, such an error may be permissible.

Note that for the first approximating encoded sequence, the total error is
d (X ^, Y ₁ ) = d (x ^ ₁ , y _1,1 ) + d (x ^ ₂ , y _2,1 ) + d (x ^ ₃ , y _3,1 ) + d (x ^ ₄ , y _4,1 ) + d (x ^ ₅ , y _5,1 ) + d (x ^ ₆ , y _6,1 ) = 2,2,
which is significantly larger than the total error at Y ₂ .

 Thus, it is shown that when using the proposed method, it is possible to reduce the transmission time of the encoded sequence of binary symbols over the communication channel or to reduce the required amount of storage devices for the encoded sequence of binary symbols.

 A device for compressing an encoded sequence from infinite alphabet characters into an encoded binary symbol sequence shown in FIG. 7 includes a block of discrete coded sequence 1, a memory block of approximating coded sequences 2, a switch 3, a selection block 4, an identification block 5, a unit for calculating statistical parameters 6, a first normalization block 7, first, second and third normalization shift registers 8, 9 and 10, the first and second right shift registers 11 and 12, the subtractor 13, the comparator 14, the first, second and third switching blocks 15, 16 and 17, the second normalization block 18, the adder 19, the first and second memory blocks of the encoding parameters 20 and 21, code register and interval 22, the first and second registers of the left shift 23 and 24, the register of the lower encoding boundary 25, the memory block of the approximating encoded sequences 26, the comparison block 27, the memory block of the maximum permissible length 28.

The information input of the discrete encoded sequence 1 unit is the input of the device, and its output is connected to the first information input of the approximation sequence selection block 4, closest to the encoded one, the second information input of which is connected to the first output of switch 3, the second output of which is connected to the input of identification unit 5. The information input of the switch 3 is connected to the output of the memory block of the approximating encoded sequences 2, the selection input of which is connected to the output of the block is compared I 27. The output of the selection block 4 of the approximating sequence closest to the encoded one is connected to the control input of the memory block of the approximating encoded sequences 26, the recording input and the counting input of which are connected to the recording output and the counting output, respectively, of the second left shift register 24. The output of the identification block 5 is connected to the data input of the calculation unit 6 of the statistical parameters, the output binary number N _j of occurrences of all symbols ordered m-ary alphabet, in the j-th part approximating the coding emoy sequence preceding the next symbol of j-th approximating encoded sequence of which is connected to the data input of the first normalization unit 7. Yield amount Q _{j, m} the numbers of occurrences of binary symbols j-th approximating encoded sequence preceding the last character in an ordered m-ary alphabet in part the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence, the output of the sum Q _{j, i} occurrences of symbols of the jth the approximating encoded sequence preceding the next character of the jth approximating encoded sequence in the ordered m-ary alphabet in the part of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence and the output of the binary number n _{j, i} occurrences of the next character j of the approximating encoded sequence in the part of the jth approximating encoded sequence preceding the next character of the jth approximating the encoded sequence of the unit for calculating statistical parameters 6, connected to the information inputs, respectively, of the first, second and third registers of the normalizing shift 8, 9 and 10. The control inputs of the registers of the normalizing shift 8, 9 and 10 are combined and connected to the output of the first normalization block 7. Output identifying the next character of the jth approximating encoded sequence with the last character of the ordered m-ay alphabet of the unit for calculating statistical parameters 6 is connected to the control input the third switching unit 17. The output of the first register of the normalizing shift 8 is connected to the first information input of the comparator 14. The outputs of the second and third registers of the normalizing shift 9 and 10 are connected to the information inputs, respectively, of the first and second registers of the right shift 11 and 12 and in addition to the first information the inputs, respectively, of the first and second switching units 15 and 16. The second information inputs
the first and second switching blocks 15 and 16 are connected to the outputs, respectively, of the first and second registers of the right shift 11 and 12. The output of the comparator 14 is connected to the control inputs of the first and second switching blocks 15 and 16. The output of the first switching block 15 is connected to the first inputs of the subtractor 13 and adder 19. The second input of the subtractor 13 is connected to the second information input of the comparator 14 and the output of the code interval register 22. The output of the second switching unit 16 is connected to the first information input of the third switching unit 17, the second the information input of which is connected to the output of the subtractor 13. The output of the third switching unit 17 is connected to the information inputs of the second normalization block 18 and the first left shift register 23. The output of the second normalization block 18 is connected to the control inputs of the first and second left shift registers 23 and 24. Information input the second register of the left shift 24 is connected to the output of the adder 19, the second input of which is connected to the output of the register of the lower coding boundary 25, the first information input of which is connected to the overwrite output in the left shift register 24. The second information input of the lower coding boundary register 25 is connected to the output of the first coding parameter memory unit 20. The output of the first left shift register 23 is connected to the first information input of the code interval register 22, the second information input of which is connected to the output of the second memory block encoding parameters 21. The comparison output of the memory block of the approximating encoded sequences 26 is connected to the first information input of the comparison block 27, the second information the input of which is connected to the output of the memory block of the maximum permissible length 28. The read output of the memory block of the approximating encoded sequences 26 is the information output of the device.

 The switch 3, the unit for calculating statistical parameters 6, the first and second blocks of memory of the encoding parameters 20 and 21, the comparison unit 27 and the memory unit of the maximum permissible length 28 are equipped with an additional control input. Block of discrete encoded sequence 1, memory block of approximating encoded sequences 2, selection block 4 of the approximating sequence closest to the encoded one, first normalization block 7, first and second right shift registers 11 and 12, second normalization block 18, code interval register 22, lower register the boundaries of the coding 25 and the memory block of the approximating encoded sequences 26 are equipped with two additional control inputs. The first, second and third registers of the normalizing shift 8, 9 and 10, the first and second registers of the left shift 23 and 24 are equipped with three additional control inputs. The additional control inputs are fed control signals from the control unit, not shown in the figures and not included in the inventive device.

 The discrete coded sequence block 1 shown in FIG. 8, is designed to read the next character of the encoded sequence, consisting of k characters of the infinite alphabet, compare it with the characters of the ordered q-ary alphabet, and select from them the closest to the next character of the encoded sequence, which is recorded in a discrete encoded sequence. The block of discrete coded sequence 1 consists of comparators 1.1.1, 1.1.2, ..., 1.1.q, voltage reference modules 1.2.1, 1.2.2, ..., 1.2.q, encoder 1.3, and a discrete coded memory module sequences 1.4. The first information inputs of the comparators 1.1.1, 1.1.2, ..., 1.1.q are connected and are the input of the discrete coded sequence block 1. The outputs of the voltage reference modules 1.2.1, 1.2.2, ..., 1.2.q are connected to the second information inputs of the respective comparators 1.1.1, 1.1.2, ..., 1.1.q. The outputs of the comparators 1.1.1, 1.1.2, ... , 1.1. q are connected to the corresponding inputs "1", "2", ..., "q" of the encoder 1.3. The outputs of the encoder 1.3 are combined into a single information bus and connected to the input of the memory module of the discrete encoded sequence 1.4. The additional control inputs of the comparators 1.1.1, 1.1.2, ..., 1.1.q and the first additional control input of the discrete coded sequence memory module 1.4 are combined and are the first additional control input of the discrete coded sequence block 1. The second additional control input of the discrete memory module of the encoded sequence 1.4 are the second additional control input of the block of discrete encoded sequence 1. The output of the memory module of the discrete encoded sequence 1.4 is the output of a block of discrete coded sequence 1.

 Comparators 1.1.1, 1.1.2, ..., 1.1.q are intended to compare the voltage levels supplied to their information inputs. Each of the comparators generates an output signal of a single level if the voltage value corresponding to the next character of the encoded sequence supplied to its first input is greater than or equal to the voltage value corresponding to the character of the ordered q-ary alphabet arriving at its second input. Otherwise, the comparator generates an output signal of zero level. The comparator circuit is known, for example, is given in the book: Shilo V.L. "Linear integrated circuits in electronic equipment." - 2nd ed., Revised. and add. - M.: Sov. Radio, 1979 - 368 p., Ill., P. 208, fig. 4.36.d and can be implemented, for example, on the K554CA3 microcircuit (see Digital and analog integrated circuits: Reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova, etc. Additional ed. S.V. Yakubovsky - M .: Radio and communications, 1989 - 496 p.: Silt, p. 366, Fig. 5.40).

The voltage reference module 1.2.1 shown in FIG. 9, is designed to generate the corresponding reference voltage and output it to the second information input of the comparator 1.1.1. The voltage reference module 1.2.1 is a voltage divider, described, for example, in the book: "Electrical Reference". In 3 volumes. T 1. General issues. Electrical materials commonly. ed. V.G. Gerasimova, P.G. Grudinsky, L.A. Zhukova et al. - 6th ed., Rev. and add. - M.: Energy, 1980 .-- 520 p., Ill. p. 183, fig. 5-3, b. The reference voltage module 1.2.1 consists of series-connected resistors 1.2.1.1 and 1.2.1.2, to which the reference voltage (U _op ) is supplied from a control unit not shown in the figures and not included in the inventive device. The combined outputs of the resistors are the output of the voltage reference module 1.2.1.

The voltage reference modules 1.2.2, 1.2.3, ..., 1.2.q are identical to the voltage reference module 1.2.1 shown in FIG. 9 and designed to generate the corresponding reference voltage and output it to the second information inputs of the respective comparators 1.1.2, 1.1.3, ..., 1.1.q. The voltage reference modules 1.2.2, 1.2.3, ..., 1.2.q are a voltage divider described, for example, in the book: "Electrical Reference". In 3 volumes. T 1. General issues. Electrical materials commonly. ed. V.G. Gerasimova, P.G. Grudinsky, L.A. Zhukova et al. - 6th ed., Rev. and add. - M .: Energy, 1980, - 520 p., Ill., P. 183, fig. 5-3, b. The voltage reference modules 1.2.2, 1.2.3, ..., 1.2.q consist of series-connected resistors 1.2.2.1 and 1.2.2.2, 1.2.3.1 and 1.2.3.2, ..., 1.2.q.1 and 1.2 .q.2, respectively, to which the reference voltage (U _op ) is supplied from a control unit not shown in the figures and not included in the inventive device. The connected outputs of the resistors are the outputs of the voltage reference modules 1.2.2, 1.2.3, ..., 1.2.q.

 The encoder 1.3 is designed to convert the number of the signal supplied to its senior input, in parallel binary code at its output. The encoder 1.3 can be performed, for example, on type K155IV1 microcircuits (see Digital Integrated Circuits: Ref. / M.I. Bogdanovich, I.N. Grel, V.A. Prokhorenko, V.V. Shalimo. - Mn .: Belarus, 1991 .-- 493 pp., Ill., P. 227, 228, Fig. 2.149, 2.150).

 The memory module of the discrete encoded sequence 1.4 is designed to record the character closest to the next character of the encoded sequence received at its input, and read it to the output of the block of the discrete encoded sequence. As a memory module of a discrete coded sequence 1.4, a static random access memory (RAM) can be used, the construction scheme of which is known and is given, for example, in the book: V.A. Batushev, V.N. Veniaminov et al. "Microcircuits and their application: a reference manual". - M.: Radio and Communications, 1983, p. 175, Fig. 5.12. The memory module of a discrete coded sequence 1.4 can be implemented, for example, on memory chips K537RU9 (see "Memory microchips, DACs and ADCs: Reference" -2nd ed., Stereotype / O. N. Lebedev, A. K. Marcinkevičius, E.K. Bagdansky et al .; - M .: KUBK-a, 1996 - 384 pp., Ill. P. 40-45, Fig. 2.5.d).

 The memory block of the approximating encoded sequences 2 shown in FIG. 10, is designed to store the values of previously formed approximating encoded sequences and reading them to the information input of the switch 3. The memory block of approximating encoded sequences 2 consists of a signal address generator 2.1, address storage register 2.2, multiplexer 2.3, and memory module 2.4. The write permission input (input W) of address storage register 2.2 is the input of the selection of the memory block of the approximating encoded sequences 2. The input of the signal address generator 2.1 and the control input (input S) of the multiplexer 2.3 are the first and second additional control inputs of the memory block of the approximating encoded sequences 2 The output of the signal address generator 2.1 is connected to the information input (input N) of the address storage register 2.2 and the second information input (input X2) of multiplexer 2.3. The first information input (input X1) of the multiplexer 2.3 is connected to the output of the address storage register 2.2. The output of the multiplexer 2.3 is connected to the input of the storage module 2.4, the output of the storage module 2.4 is the output of the memory block of the approximating encoded sequences 2.

 The signal address generator 2.1 is intended to generate the address of an approximating encoded sequence read from the memory module 2.4. The signal address generator 2.1 by physical nature is a counter, the circuit of which is known, is shown, for example, in the book: A.A Sikarev, O. N. Lebedev "Microelectronic devices for the formation and processing of complex signals." - M.: Radio and Communications, 1983, p. 128, Fig. 5.18, and can be implemented, for example, on the K155IE6 chip (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 137-139, Fig. 2.69).

 The address storage register 2.2 is intended to store the address of the corresponding selected approximating encoded sequence corresponding to the remaining approximating encoded sequence. The scheme of the address storage register 2.2 is known, for example, is given in the book: V. A. Batushev, V. N. Veniaminov et al. "Microcircuits and their Application: Reference Guide". - M.: Radio and Communications, 1983, p. 134, Fig. 4.34, and can be implemented, for example, on the K531IR19 chip (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 pp., Ill., P. 198, 199, Fig. 2.120).

 Multiplexer 2.3 is designed to switch the memory unit 2 from the mode of sequentially reading values of j-x, where j = 1, 2, ..., T, of the approximating encoded sequences into the reading mode of the values of the remaining approximating encoded sequences corresponding to the remaining approximating encoded sequences from the memory module 2.4. The multiplexer 2.3 scheme is known, is given in the book: L. A. Maltsev and others. "Fundamentals of digital technology." - M.: Radio and Communications, 1986, p. 52, Fig. 48, and can be implemented, for example, on the K155KP5 chip (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 pp., Ill., P. 161, 162, Fig. 2.83).

 The memory module 2.4 is designed to store the values of T approximating encoded sequences. Storage module 2.4 is a storage device, the circuit of which is known, is shown, for example, in the book: V. A. Batushev, V. N. Veniaminov et al. "Microcircuits and their application: a reference manual". - M.: Radio and Communications, 1983, p. 182, Fig. 5.17, and can be performed, for example, on memory chips of the type КР556РТ5 (see "Memory microchips, DACs and ADCs: Reference" - 2nd ed., Stereotype / O. N. Lebedev, A. K. Marcinkevičius, E. K. Baghdansky et al .; - M .: KUBK-a, 1996 - 384 p.: Ill. P. 119-124, fig. 4.4.v.).

 The switch 3 shown in FIG. 11, is designed to switch the operation of the device from the reading mode of the approximating encoded sequences from the memory block of the approximating encoded sequences 2 to the input of the identification unit 5 into the reading mode of the same sequences to the second information input of the selection unit 4 of the approximating sequence closest to the encoded one. Switch 3 comprises a first controllable switch 3.1, a second controllable switch 3.2, and an inverter 3.3. The information input of the first controllable switch 3.1 and the information input of the second controllable switch 3.2 connected to it is the information input of the switch 3. The control input of the second controllable switch 3.2 is connected to the output of the inverter 3.3. The outputs of the first controllable switch 3.1 and the second controllable switch 3.1 are, respectively, the first and second outputs of the switch 3. The control input of the first controllable switch 3.1 and the inverter 3.3 input connected to it is an additional control input of the switch 3.

 The first controllable switch 3.1 shown in FIG. 12, is designed to read the values of the approximating encoded sequences from the output of the memory block of the approximating encoded sequences 2 to the input of the identification unit 5. The first controlled switch 3.1 in physical essence is a two-position controlled switch. A controlled switch can be implemented, for example, on the K176KT1 chip (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo - Mn .: Belarus, 1991. - 493 p.: Ill., P. 322, 324, Fig. 3.41, 3.42).

 The second controlled switch 3.2 is designed to read the values of the approximating encoded sequences from the output of the memory block of the approximating encoded sequences 2 to the second information input of the selection block 4 of the approximating sequence closest to the encoded one. The circuit of the second controllable switch 3.2 is identical to the circuit of the first controllable switch 3.1 shown in FIG. 12.

 Inverter 3.3 is designed to generate a control signal supplied to the control input of the second controlled switch 3.2. Inverter 3.3 can be implemented, for example, on the K561LN2 chip (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus , 1991 - 493 p.: Ill., P. 315, Fig. 3.26).

 The selection block 4 of the approximating sequence closest to the coded sequence shown in FIG. 13 is intended for comparing the values of the approximating encoded sequences corresponding to the remaining approximating encoded sequences with the value of the encoded sequence and for choosing among the remaining approximating encoded sequences closest to the encoded sequence. The selection block 4 of the approximating sequence closest to the encoded one consists of a subtractor 4.1, an adder 4.2, a controlled switch 4.3, a comparator 4.4, a minimum storage register of 4.5, and a multiplexer 4.6.

 The first input (input A) of the subtractor 4.1 is the first information input of the selection block of the approximating sequence closest to the encoded one. The second input (input B) of the subtractor 4.1 is the second information input of the selection block 4 of the approximating sequence closest to the encoded one. The output of the subtractor 4.1 is connected to the first input (input A) of the adder 4.2. The output of the adder 4.2 is connected to the information input of the managed switch 4.3 and its own second input (input B). The control input of the controlled switch 4.3 is the first additional control input of the selection unit 4. The information output of the controlled switch 4.3 is connected to the second input (input B) of the comparator 4.4 and the first information input (input X) of the multiplexer 4.6. At the second information input (input Y) of the multiplexer 4.6 information signals of a unit value "1" are constantly supplied. The control input (input S) of the multiplexer 4.6 is the second additional control input of the selection unit 4. The output of the multiplexer 4.6 is connected to the information input (input X) of the minimum storage register 4.5. The output of the minimum amount storage register 4.5 is connected to the first input (input A) of the comparator 4.4, the output of which is connected to the control input (input W) of the minimum amount storage register 4.5, and is also the output of the selection block 4 of the approximating sequence closest to the encoded one.

 Subtractor 4.1 is designed to determine the difference between the values of the next characters of the approximating encoded sequence corresponding to the remaining approximating encoded sequence and the corresponding characters of the encoded sequence. Subtractor 4.1 is an adder operating in the subtraction mode. The subtractor circuit is known, for example, is given in the book: P. P. Maltsev et al. "Digital Integrated Circuits: A Guide". - M .: Radio and communications, 1994, p. 76, and it can, for example, be implemented on the K555IM7 microcircuit (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A Prokhorenko, V.V. Shalimo. - Minsk: Belarus, 1991. - 493 pp., Ill., Pp. 254-257, Fig. 2.178).

 Adder 4.2 is designed to summarize the differences between the values of the next characters of the approximating encoded sequence corresponding to the remaining approximating encoded sequence and the corresponding characters of the encoded sequence. The adder circuit is known, for example, is given in the book: L.A. Maltseva et al. "Fundamentals of digital technology." - M.: Radio and Communications, 1986, pp. 53-54, Fig. 51 and can be performed, for example, on the K155IM1 microcircuit (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus , 1991. - 493 pp., Ill., Pp. 249-252, Fig. 2.172).

 The controlled switch 4.3 is designed to ensure that the value of the number is read from the output of the adder 4.2 to the second input of the comparator (input B) 4.4 and to the first information input (input X) of the multiplexer 4.6 upon receipt of control signals to the control input of the control switch 4.3. In physical essence, the controllable switch 4.3 is a two-position controllable switch and is identical to the first controllable switch 3.1 shown in FIG. 12. Schemes of controlled switches are known and are given, for example, in the book: V.L. Shilo "Popular CMOS chips, Reference." - M .: Jaguar, 1993, p. 22.

 Comparator 4.4 is designed to compare the value of the number obtained from the output of the adder 4.2, and the value of the number recorded in the storage register of the minimum amount 4.5. The comparator circuit is known, for example, is given in the book: P.P. Maltsev et al. "Digital Integrated Circuits: A Guide." - M.: Radio and communications, 1994, p. 83 and can be implemented, for example, on the K555SP1 chip (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko , V.V. Shalimo .-- Mn .: Belarus, 1991 .-- 493 p.: Ill., P. 268, 272, Fig. 2.190).

 The minimum amount storage register 4.5 is designed to store the minimum value of a number from the numbers generated in the adder 4.2. The scheme of the register of storage of the minimum amount 4.5 is known and is given, for example, in the book: V. A. Batushev, V. N. Veniaminov and others. Chips and their application: Reference manual. - M.: Radio and Communications, 1983, p. 134, Fig. 4.34. and can be implemented, for example, on K555IR11A microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 185-188, Fig. 2.109).

 The multiplexer 4.6 is a two-input multiplexer, the circuit of which is known, is given, for example, in the book: L. A. Maltsev et al. "Fundamentals of digital technology." - M.: Radio and Communications, 1986, p. 52, Fig. 48, and can be implemented, for example, on the K155KP5 microcircuit (see V. L. Shilo "Popular Digital Microcircuits", - M .: Radio and Communication, 1987, p. 146).

 The identification unit 5 shown in FIG. 14, is intended to identify the value of the next symbol of the jth, where j = 1, 2, ..., T, approximating the encoded sequence with the i-th, where i = 1, 2, ..., m, with the symbol of the ordered m- egg alphabet. Identification block 5 consists of m comparators 5.1.1 - 5.1.m and m memory modules of the values of the symbols of the ordered m-ary alphabet 5.2.1 - 5.2.m.

 The first inputs of the comparators 5.1.1, 5.1.2, ..., 5.1.m are connected and are the input of the identification unit 5. The outputs of the memory modules of the values of the symbols of the ordered m-ary alphabet 5.2.1, 5.2.2, ..., 5.2. m are connected to the second inputs of the corresponding comparators 5.1.1, 5.1.2, ..., 5.1.m. Outputs of comparators 5.1.1, 5.1.2,. .., 5.1.m are combined into a single information bus, which is the output of the identification unit 5.

 Comparators 5.1.1, 5.1.2 ... 2, ..., 5.2.m. The comparator circuit is known, for example, is given in the book: P.P. Maltsev et al. "Digital Integrated Circuits: A Guide." - M.: Radio and Communications, 1994, p. 83 and can be implemented, for example, on K555SP1 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko , V.V. Shalimo - Minsk: Belarus, 1991 - 493 pp., Ill., Pp. 268, 272, Fig. 2.190).

 Modules of memory of symbol values of ordered m-ary alphabet 5.2.1, 5.2.2,. .., 5.2.m are intended for storing the values of the characters of the ordered m-ary alphabet. The memory modules of the values of the symbols of the ordered m-ary alphabet 5.2.1, 5.2.2, ..., 5.2.m are memory devices, the circuit of which is known, is shown, for example, in the book: V. A. Batushev, V. N . Veniaminov and others. "Microcircuits and their application: a reference manual." - M.: Radio and Communications, 1983, p. 182, Fig. 5.17, and can be performed, for example, on memory chips of the type КР556РТ5 (see. "Memory microchips, DACs and ADCs: Reference" - 2nd ed., Stereotype / O. N. Lebedev, A. K. Martsinkevichyus, E. A.K. Bagdansky et al .; - M .: KUBK-a, 1996 - 384 pp., Ill. P. 119-124, fig. 4.4.v.).

The statistical parameter calculation unit 6 shown in FIG. 15, is intended to calculate the statistical parameters n _{j, i} , Q _{j, i} , Q _{j, m} and N _{j of the} next character of the jth, where j = 1, 2, ..., T, which approximates the encoded sequence. The unit for calculating statistical parameters 6 consists of logical elements AND 6.1.1, 6.1.2, ..., 6.1.m, counters 6.2, 6.3.1, 6.3.2,. . . , 6.3.m, multiplexers 6.4.1, 6.4.2, ..., 6.4.k, adders 6.5.1, 6.5.2, ..., 6.5.h (where h = m-2), multiplexers 6.6. 1, 6.6.2, ..., 6.6.k, encoder 6.7, inverter 6.8.

The second inputs of the logical elements AND 6.1.1, 6.1.2, ..., 6.1.m are connected, respectively, to the inputs S1, S2, ..., Sm of the encoder 6.7, combined into a single information bus, which is the information input of the statistical calculation unit parameters 6. In addition, the mth input of the information bus is additionally connected to the input of the inverter 6.8, the output of which is the identification output of the next character of the jth approximating encoded sequence with the last character of the ordered m-ary alphabet of the unit for calculating statistical parameters 6. First in The gates of the logical elements AND 6.1.1, 6.1.2, ..., 6.1.m are combined, connected to the control input (input E) of the encoder 6.7, the counting input (input C) of the counter 6.2 and are an additional control input of the unit for calculating statistical parameters 6 The outputs 1, 2, ..., k of counter 6.2 are combined into a single information bus, which is the output of the binary number N _{j of} occurrences of all characters of the ordered m-ary alphabet, in the part of the jth approximating encoded sequence preceding the next symbol of the jth approximating coded sequence and the unit for calculating statistical parameters 6. The outputs of the logic elements AND 6.1.1, 6.1.2, ..., 6.1.m are connected to the counting inputs (inputs C) of the counters 6.3.1, 6.3.2, ..., 6.3.m , respectively. Outputs 1, 2,. . ., k of the counter 6.3.1 are connected, respectively, to the inputs A1, A2, ..., Ak of the adder 6.5.1. The outputs 1, 2, ..., k of the counter 6.3.2 are connected, respectively, to the inputs B1, B2, ..., Bk of the adder 6.5.1. The outputs 1, 2, ..., k of the counter 6.3.3 are connected, respectively, to the inputs B1, B2, ..., Bk of the adder 6.5.2. The outputs 1, 2, ..., k of the counter 6.3.m-1 are connected, respectively, to the inputs B1, B2, ..., Bk of the adder 6.5.h, where h = m-2. In addition, the outputs 1, 2, ..., k of the counter 6.3.1 are connected, respectively, with the inputs S1 of the multiplexers 6.4.1, 6.4.2, ..., 6.4.k and the inputs S2 of the multiplexers 6.6.1, 6.6. 2,. . ., 6.6.k. The outputs 1, 2, ..., k of the counter 6.3.2 are connected, respectively, with the inputs S2 of the multiplexers 6.4.1, 6.4.2, ..., 6.4.k. Outputs 1, 2, ..., k of the counter 6.3. m are connected, respectively, with the inputs of Sm multiplexers 6.4.1, 6.4.2,. . ., 6.4.k. The outputs of the multiplexers 6.4.1, 6.4.2, ..., 6.4.k are combined into a single information bus, which is the output of the binary number n _{j, i} occurrences of the next character of the jth approximating encoded sequence in the part of the jth approximating encoded sequence preceding the next symbol of the jth approximating encoded sequence of the block for calculating statistical parameters 6. The outputs S1, S2, ..., Sk of the adder 6.5.1 are connected, respectively, to the inputs A1, A2, ..., Ak of the adder 6.5.2. The outputs S1, S2, ..., Sk of the adder 6.5.2 are connected, respectively, with the inputs A1, A2, ..., Ak of the adder 6.5.3. The outputs S1, S2, ..., Sk of the adder 6.5. m-1 are connected, respectively, with the inputs A1, A2, ..., Ak of the adder 6.5. h. The outputs S1, S2, ..., Sk of adder 6.5.h are combined into a single information bus, which is the output of the sum Q _{j, m of} binary numbers of occurrences of characters of the jth approximating encoded sequence preceding the last character in the ordered m-ary alphabet in part j of the approximating encoded sequence preceding the next character of the jth approximating encoded sequence of the unit for calculating statistical parameters 6. In addition, the outputs S1, S2, ..., Sk of adder 6.5.1 are connected, respectively, to the inputs S3 of the multiplexor in 6.6.1, 6.6.2, ..., 6.6.k. Similarly, the outputs S1, S2, ..., Sk of the adder 6.5.h are connected, respectively, to the inputs of Sm of the multiplexers 6.6.1, 6.6.2, ..., 6.6.k. At the inputs S1 of multiplexers 6.6.1, 6.6.2, ..., 6.6.k, signals of the zero level "0" are constantly supplied. The outputs of the multiplexers 6.6.1, 6.6.2, ..., 6.6.k are combined into a single information bus, which is the output of the sum Q _{j, i of} occurrences of the symbols of the jth approximating encoded sequence preceding the next symbol of the jth approximating encoded sequence in the ordered m-ary alphabet in the part of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence of the unit for calculating statistical parameters 6. Control inputs (inputs A) of multiplexers 6.4.1, 6.4. 2, ..., 6.4.k and 6.6.1, 6.6.2, ..., 6.6.k are combined and connected to the output of the encoder 6.7.

Logic elements AND 6.1.1, 6.1.2, ..., 6.1.m, are intended for issuing to the counting inputs (inputs C) of counters 6.3.1, 6.3.2, ..., 6.3.m a sequence of pulses for counting values n _{i, i} when the control signal arrives at the additional control input of the unit for calculating statistical parameters 6 and the signal of the next symbol j, where j = 1, 2, ..., T, which approximates the encoded sequence. Logical elements AND 6.1.1, 6.1.2,. . ., 6.1.m can be performed, for example, on K176LI1 type microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 p .: ill., P. 313, 314, Fig. 3.21).

 Counter 6.2 is designed to count the number of pulses arriving at its counter input (input C). The counter 6.2 can be performed, for example, on type K564IE10 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991. -493 pp., Ill., P. 345, 346, Fig. 3.67).

 Counters 6.3.1, 6.3.2, ..., 6.3.m are intended for counting the number of pulses arriving at their counter inputs (inputs C). Counters 6.3.1, 6.3.2,. . ., 6.3.m can be performed, for example, on type K564IE10 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 p .: ill., P. 345, 346, Fig. 3.67).

Multiplexers 6.4.1, 6.4.2. , 6.4.k are intended for switching the output signal of one of the counters 6.3.1, 6.3.2, ..., 6.3.m, in accordance with the address code generated by the encoder 6.7, to the output of the binary number n _{j, i of} occurrences of the next character j of the approximating encoded sequence in the part of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence of the statistical parameter calculation unit 6. Multiplexers 6.4.1, 6.4,2, ..., 6.4.k can be performed, for example , on type K155KP1 microcircuits (see Digital integrated circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 - 493 pp., Ill., P. 157, 158, Fig. 2.81).

Adders 6.5.1, 6.5.2, ..., 6.5.h, where h = m-2, are designed to perform arithmetic addition of the values of statistical parameters n _{j, i} . The adder 6.5.1 is designed to calculate the sum of the values of the statistical parameters n _{j, 1} and n _{j, 2} . Adder 6.5.2 is designed to calculate the sum of the values of the statistical parameters n _{j, 1} , n _{j, 2} and n _{j, 3} ... Adder 6.5.h, where h = m-2, is used to calculate the sum of the values of the statistical parameters n _{j, 1} , n _{j, 2,.} .., n _{j, m-1} . Adders 6.5.1, 6.5.2, ..., 6.5.h, where h = m-2, can be performed, for example, on chips of the K561IM1 type (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I.N. Grel, V.A. Prokhorenko, V.V. Shalimo .-- Mn .: Belarus, 1991. - 493 pp., Ill., Pp. 381-383, Fig. 3.111).

Multiplexers 6.6.1, 6.6.2, ..., 6.6.k are intended for output switching of the sum Q _{j, i} occurrences of characters of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence in the ordered m-ary alphabet in the part of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence of the unit for calculating statistical parameters 6 of one of the following signals: a signal of the zero level supplied to the inputs S1 ultipleksorov 6.6.1, 6.6.2, ..., 6.6.k, 6.3.1 counter output signal, the output signal of one of the adders 6.5.1, 6.5.2. . . , 6.5.h, where h = m-2, in accordance with the control signal generated by the encoder 6.7. Multiplexers 6.6.1, 6.6.2, ..., 6.6.k can be performed, for example, on microcircuits of the K155KP1 type (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V.V. Shalimo - Mn .: Belarus, 1991 - 493 pp., Ill., P. 157, 158, Fig. 2.81).

 Encoder 6.7. is intended to convert the number of the next character of the jth, where j = 1, 2, ..., T, which approximates the encoded sequence arriving at only one of the inputs of the encoder 6.7, into a parallel binary code at its output. The encoder 6.7 can be performed, for example, on type K155IV1 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 pp., Ill., P. 227, 228, Fig. 2.149, 2.150).

 Inverter 6.7 is designed to invert the signal from the mth output of the information bus of the information input of the statistical parameters calculation unit 6 to its output of identifying the next character of the jth approximating encoded sequence with the last character of the ordered m-ary alphabet. Inverter 6.7 can be performed, for example, on type K561LN2 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 pp., Ill., P. 315, 316, Fig. 3.26).

The first normalization unit 7 shown in FIG. 16, is intended to form the number of γ shift digits necessary to normalize the value of the statistical parameter N _{j, i of the} next character of the jth, where j = 1, 2, ..., T, which approximates the encoded sequence. Normalization block 7 consists of registers 7.1 and 7.2, comparators 7.3 and 7.4, counter 7.5, logical element OR 7.6, register 7.7.

 Information inputs X2, X3, ..., Xz, where z = k + 1, register 7.1 are connected, respectively, with inputs X1, X2, ..., Xk of register 7.2, are combined into a single information bus, which is the information input of the normalization block 7. The first control input (input W1) of register 7.1 is connected to the first control input (input W1) of register 7.2 and is the first additional control input of the first normalization unit 7. The second control input (input W2) of register 7.1 is connected to the second control input (input W2 ) of register 7.2 and the counting input (input C) of counter 7.5 and is the second additional control input of the first normalization block 7. The output of register 7.1 is connected to input A of comparator 7.3. The output of register 7.2 is connected to input A of comparator 7.4. The coincidence output (in Fig. 16 is indicated by the symbol "=") of the comparator 7.3 is connected to the first input of the OR gate 7.6. The match output (in Fig. 16 is indicated by the symbol "=") of the comparator 7.4 is connected to the second input of the OR gate 7.6. The output of the logic element OR 7.6 is connected to the control input (input W) of the register 7.7. The output of counter 7.5 is connected to the information input (input A) of register 7.7. To the inputs X0 and X1 of the register 7.1, as well as to the input X0 of the register 7.2, zero level signals "0" are constantly supplied. The inputs Bw, ..., B3 of the comparator 7.3 are constantly supplied with signals of the zero level "0", and at its inputs B2 and B1 - signals of the unit level "1". The inputs Bw, ..., B3 and the input B1 of the comparator 7.4 are constantly supplied with signals of the zero level "0", and at its input B2 - signals of the unit level "1". The output of register 7.7 is the output of normalization block 7.

Registers 7.1 and 7.2 are intended for recording and storing the value of the statistical parameter N _{j of the} next character of the jth, where j = 1, 2, ..., T, approximating the encoded sequence and shifting in the direction of the least significant bits of this value. Registers 7.2 and 7.3 can be performed, for example, on K555IR11A microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo - Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 185-188, Fig. 2.109).

 Comparator 7.3 is intended to compare the contents of register 7.1 received at input A of comparator 7.3 with the binary sequence 000 ... 011 received at input B of this comparator. If the compared signals coincide, the output of the comparator 7.3 will generate a signal of a single level, otherwise - a signal of zero level. Comparator 7.3 can be performed, for example, on type K155IR1 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 178-180, Fig. 2.99,2.100).

 Comparator 7.4 is designed to compare the contents of register 7.2, which is input to comparator 7.4 input A with the binary sequence 000 ... 010, which goes to input B of this comparator. If the compared signals coincide, the output of the comparator 7.4 will generate a signal of a single level, otherwise - a signal of zero level. Comparator 7.4 can be performed, for example, on type K155IR1 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 178-180, Fig. 2.99,2.100).

 Counter 7.5 is designed to count the number of pulses applied to its input, which is equal to the number of γ bits of the shift and receive at the output of a binary number that displays the number of γ bits of the shift. Counter 7.5 can be performed, for example, on K155IE4 type microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 133, 135, Fig. 2.66.).

 The OR logic element 7.6 is designed to generate a unit level signal at its output if at the output of at least one of the comparators 7.3 or 7.4 a unit level signal is generated. The logical element OR 7.6 can be performed, for example, on chips of type K155LL1 (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991. - 493 p.: Ill., P. 60, 62, Fig. 2.15.).

 Register 7.7 is used to record a binary number coming from the output of counter 7.5 when a unit level signal is generated at the output of comparator 7.3 or comparator 7.4. Register 7.7 can be performed, for example, on K555IR11A microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus , 1991 .-- 493 p.: Ill., P. 185-188, Fig. 2.109).

очередного символа j-й, где j = 1, 2, ..., T, аппроксимирующей кодируемой последовательности. Первый регистр нормализующего сдвига 8 состоит из регистра 8.1, компаратора 8.2, логического элемента ИЛИ 8.3, регистра 8.4, счетчика 8.5, логического элемента И 8.6.The first normalization shift register 8 shown in FIG. 17, is intended to form a normalized value of the sum

the next character is the jth, where j = 1, 2, ..., T, which approximates the encoded sequence. The first register of the normalizing shift 8 consists of register 8.1, comparator 8.2, logical element OR 8.3, register 8.4, counter 8.5, logical element AND 8.6.

 The first information input (input X) of register 8.4 is the information input of the first register of normalizing shift 8. The information input (input X) of register 8.1 is the control input of the first register of normalizing shift 8. The control input (input W) of register 8.1 and the first control input connected to it (input W1) of register 8.4 is the first additional control input of the first register of the normalizing shift 8. The counting input (input C) of the counter 8.5 and the second input of the logical element And 8.6 connected to it is the second additional directs input of the first shift register 8. normalizing reset input (R in) counter 8.5 is the third additional control input of the first normalizing shift register 8. The output of register 8.1 is coupled to a first input (input A) of the comparator 8.2. The output of the counter 8.5 is connected to the second input (input B) of the comparator 8.2. The mismatch output (in Fig. 17 is indicated by the symbol "<") of the comparator 8.2 is connected to the first input of the OR gate 8.3. The match output (in Fig. 17 is indicated by the symbol "=") of the comparator 8.2 is connected to the second input of the OR gate 8.3. The output of the OR gate 8.3 is connected to the first input of the AND gate 8.6. The output of the logical element And 8.6 is connected to the second control input (input W2) of register 8.4. The output of register 8.4 is the output of the first register of the normalizing shift 8.

очередного символа j-й, где j = 1, 2, ..., T, аппроксимирующей кодируемой последовательности сдвигом значения статистического параметра Q_j,m очередного символа j-й, где j = 1, 2, ..., T, аппроксимирующей кодируемой последовательности, поступающего с блока нормализации
7 и выдачи сформированного значения на первый информационный вход компаратора 8.2. Регистр 8.1 может быть выполнен, например, на микросхемах К555ИР11А (см. Цифровые интегральные микросхемы: Справ./М. И. Богданович, И. Н. Грель, В. А. Прохоренко, В. В. Шалимо - Мн.: Беларусь, 1991. - 493 с.: ил., с. 185-188, Рис. 2.109).Register 8.1 is designed to store the binary value of the number γ of shift digits necessary to obtain the normalized value of the sum

of the next jth character, where j = 1, 2, ..., T, approximating the encoded sequence by shifting the value of the statistical parameter Q _{j, m of the} next jth character, where j = 1, 2, ..., T, approximating encoded sequence coming from the normalization block
7 and issuing the generated value to the first information input of the comparator 8.2. Register 8.1 can be executed, for example, on K555IR11A microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo - Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 185-188, Fig. 2.109).

 Comparator 8.2 is designed to compare the values of the numbers received at its first input (input A) and second input (input B). Comparator 8.2 can be performed, for example, on K561IP2 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo - Mn .: Belarus, 1991 .-- 493 p.: Ill., P. 382-385).

очередного символа j-й, где j = 1, 2, ..., T, аппроксимирующей кодируемой последовательности из значения статистического параметра Q_j,m очередного символа j-й, где j = 1, 2, ..., T, аппроксимирующей кодируемой последовательности. Логический элемент ИЛИ 8.3 может быть выполнен, например, на микросхемах типа К155ЛЛ1 (см. Цифровые интегральные микросхемы: Справ./М. И. Богданович, И. Н. Грель, В. А. Прохоренко, В. В. Шалимо. - Мн.: Беларусь, 1991. - 493 с.: ил., стр. 60, 62, Рис. 2.15.).The OR logic element 8.3 is designed to generate a unit-level signal in the event that the number of pulses received from the second control input is less than the value that displays the number of bits needed to obtain the normalized value of the sum

of the next jth character, where j = 1, 2, ..., T, approximating the encoded sequence from the value of the statistical parameter Q _{j, m of the} next jth character, where j = 1, 2, ..., T, approximating coded sequence. The logical element OR 8.3 can be performed, for example, on chips of the type K155LL1 (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 p.: Ill., P. 60, 62, Fig. 2.15.).

очередного символа j-й, где j = 1, 2, ..., T, аппроксимирующей кодируемой последовательности. Регистр 8.4 может быть выполнен, например, на микросхемах К555ИР11А (см. Цифровые интегральные микросхемы: Справ./М. И. Богданович, И. Н. Грель, В. А. Прохоренко, В. В. Шалимо. - Мн.: Беларусь, 1991. - 493 с.: ил., с. 185-188, Рис. 2.109).Register 8.4 is designed to write into it the values of the statistical parameter Q _{j, m of the} next character of the jth, where j = 1, 2, ..., T, approximating the encoded sequence, its sequential shift in the direction of the highest digits by γ digits and issuing the generated normalized value of the amount

the next character is the jth, where j = 1, 2, ..., T, which approximates the encoded sequence. Register 8.4 can be performed, for example, on K555IR11A microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus , 1991 .-- 493 p.: Ill., P. 185-188, Fig. 2.109).

 The counter 8.5 is designed to count the number of pulses from the second additional control input of the first register of the normalizing shift 8 to the counting input (input C) of the counter 8.5 and issuing the counted number to the second input (input B) of the comparator 8.2. The counter 8.5 can be performed, for example, on K155IE4 type microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 133, 135, Fig. 2.66.).

 The AND 8.6 logic element is designed to ensure the passage of control signals from the second additional control input of the first normalizing shift register 8 to the second control input (input W2) of register 8.4 if the output signal of the OR 8.3 logic element takes a single value. The logical element And 8.6 can be performed, for example, on microcircuits of type K176LI1 (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 p.: Ill., P. 313, 314, Fig. 3.21).

The second normalization shift register 9 is identical to the first normalization shift register 8 shown in FIG. 17, and is intended to generate the normalized value of the sum Q _{j, i of the} next character of the jth, where j = 1, 2, ..., T, approximating the encoded sequence. The second register of the normalizing shift 9 consists of register 9.1, comparator 9.2, logical element OR 9.3, register 9.4, counter 9.5, logical element AND 9.6.

 The first information input (input X) of register 9.4 is the information input of the second register of normalizing shift 9. The information input (input X) of register 9.1 is the control input of the second register of normalizing shift 9. The control input (input W) of register 9.1 and the first control input connected to it (input W1) of register 9.4, is the first additional control input of the second register of the normalizing shift 9. The counting input (input C) of the counter 9.5 and the second input of the logical element AND 9.6 connected to it are the second additional the control input of the second register of the normalizing shift 9. The reset input (input R) of the counter 9.5 is the third additional control input of the second register of the normalizing shift 9. The output of the register 9.1 is connected to the first input (input A) of the comparator 9.2. The output of the counter 9.5 is connected to the second input (input B) of the comparator 9.2. The mismatch output (in Fig. 12 is indicated by the symbol "<") of the comparator 9.2 is connected to the first input of the OR gate 9.3. The match output (in Fig. 12 is indicated by the symbol "=") of the comparator 9.2 is connected to the second input of the OR gate 9.3. The output of the OR gate 9.3 is connected to the first input of the AND gate 9.6. The output of the logic element AND 9.6 is connected to the second control input (input W2) of register 9.4. The output of register 9.4 is the output of the second register of the normalizing shift 9.

очередного символа j-й, где j = 1, 2, ..., T, аппроксимирующей кодируемой последовательности сдвигом значения статистического параметра Q_j,i очередного символа j-й, где j = 1, 2, ..., T, аппроксимирующей кодируемой последовательности, поступающего с блока нормализации 7 и выдачи сформированного значения на первый информационный вход компаратора 9.2. Регистр 9.1 может быть выполнен, например, на микросхемах К555ИР11А (см. Цифровые интегральные микросхемы: Справ. /М. И. Богданович, И. Н. Грель, В. А. Прохоренко, В. В. Шалимо - Мн.: Беларусь, 1991. - 493 с.: ил., с. 185-188, Рис. 2.109).Register 9.1 is designed to store the binary value of the number of γ shift digits necessary to obtain the normalized value of the sum

of the next jth character, where j = 1, 2, ..., T, approximating the encoded sequence by shifting the value of the statistical parameter Q _{j, i of the} next jth character, where j = 1, 2, ..., T, approximating the encoded sequence coming from the normalization unit 7 and issuing the generated value to the first information input of the comparator 9.2. Register 9.1 can be performed, for example, on K555IR11A microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo - Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 185-188, Fig. 2.109).

 Comparator 9.2 is designed to compare the values of the numbers received at its first input (input A) and second input (input B). Comparator 9.2 can be performed, for example, on K561IP2 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V Shalimo. - Mn .: Belarus, 1991 .-- 493 p.: Ill., P. 382-385).

очередного символа j-й, где j = 1, 2, ..., T, аппроксимирующей кодируемой последовательности из значения статистического параметра Q_j,i очередного символа j-й, где j = 1, 2, ..., T, аппроксимирующей кодируемой последовательности. Логический элемент ИЛИ 9.3 может быть выполнен, например, на микросхемах типа К155ЛЛ1 (см. Цифровые интегральные микросхемы: Справ./М. И. Богданович, И. Н. Грель, В. А. Прохоренко, В. В. Шалимо.- Мн.: Беларусь, 1991. - 493 с.: ил., стр. 60, 62, Рис. 2.15.).The OR 9.3 logic element is designed to generate a unit level signal in the event that the number of pulses received from the second control input is less than the value that displays the number of bits required to obtain the normalized value of the sum

of the next jth character, where j = 1, 2, ..., T, approximating the encoded sequence from the value of the statistical parameter Q _{j, i of the} next jth character, where j = 1, 2, ..., T, approximating coded sequence. The logical element OR 9.3 can be performed, for example, on type K155LL1 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo.- Mn .: Belarus, 1991 .-- 493 p.: Ill., P. 60, 62, Fig. 2.15.).

очередного символа j-й, где j = 1, 2, ..., T, аппроксимирующей кодируемой последовательности. Регистр 9.4 может быть выполнен, например, на микросхемах К555ИР11А (см. Цифровые интегральные микросхемы: Справ./М. И. Богданович, И. Н. Грель, В. А. Прохоренко, В. В. Шалимо. - Мн.: Беларусь, 1991. - 493 с.: ил., с. 185-188, Рис. 2.109).Register 9.4 is designed to write into it the values of the statistical parameter Q _{j, i of the} next character of the jth, where j = 1, 2, ..., T, approximating the encoded sequence, its sequential shift in the direction of the highest digits by γ digits and issuing the generated normalized value

the next character is the jth, where j = 1, 2, ..., T, which approximates the encoded sequence. Register 9.4 can be performed, for example, on K555IR11A microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus , 1991 .-- 493 p.: Ill., P. 185-188, Fig. 2.109).

 Counter 9.5 is intended for counting the number of pulses from the second additional control input of the second register of the normalizing shift to the counting input (input C) of the counter 9.5 and issuing the counted number to the second input (input B) of the comparator 9.2. The counter 9.5 can be performed, for example, on type K155IE4 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 133, 135, Fig. 2.66.).

 The logical element And 9.6 is designed to ensure the passage of control signals from the second additional control input of the second register of the normalizing shift 9 to the control input (input W) of the register 9.4 in the event that the output signal of the logical element OR 9.3 takes a single value. The logical element And 9.6 can be performed, for example, on chips of the type K176LI1 (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 p.: Ill., P. 313, 314, Fig. 3.21).

очередного символа j-й, где j = 1, 2, ..., T, аппроксимирующей кодируемой последовательности. Третий регистр нормализующего сдвига 10 состоит из регистра 10.1, компаратора 10.2, логического элемента ИЛИ 10.3, регистра 10.4, счетчика 10.5, логического элемента И 10.6.The third normalizing shift register 10 is identical to the normalizing shift register 8 shown in FIG. 17, and is intended to form a normalized value

the next character is the jth, where j = 1, 2, ..., T, which approximates the encoded sequence. The third register of normalizing shift 10 consists of register 10.1, comparator 10.2, logical element OR 10.3, register 10.4, counter 10.5, logical element AND 10.6.

 The first information input (input X) of the register 10.4 is the information input of the third register of the normalizing shift 10. The information input (input X) of the register 10.1 is the control input of the third register of the normalizing shift 10. The control input (input W) of the register 10.1 and the first control input connected to it (input W1) of register 10.4 is the first additional control input of the third register of the normalizing shift 10. The counting input (input C) of the counter 10.5 and the second input of the logical element And 10.6 connected to it is the second additional Yelnia control input of the third register 10. The shift normalizing reset input (input R) counter 10.5 is a third additional control input of the third normalizing shift register 10. The output of register 10.1 is connected to a first input (input A) of the comparator 10.2. The output of the counter 10.5 is connected to the second input (input B) of the comparator 10.2. The mismatch output (in Fig. 17 is indicated by the symbol "<") of the comparator 10.2 is connected to the first input of the OR gate 10.3. The match output (in Fig. 17 is indicated by the symbol "=") of the comparator 10.2 is connected to the second input of the OR gate 10.3. The output of the OR gate 10.3 is connected to the first input of the AND gate 10.6. The output of the logic element AND 10.6 is connected to the second control input (input W2) of the register 10.4. The output of register 10.4 is the output of the third register of the normalizing shift 10.

очередного символа j-й, где j = 1, 2, ..., T, аппроксимирующей кодируемой последовательности сдвигом значения статистического параметра n_j,i очередного символа j-й, где j = 1, 2, ..., T, аппроксимирующей кодируемой последовательности, поступающего с блока нормализации 7 и выдачи сформированного значения на первый информационный вход компаратора 10.2. Регистр 10.1 может быть выполнен, например, на микросхемах К555ИР11А (см. Цифровые интегральные микросхемы: Справ. /М. И. Богданович, И. Н. Грель, В. А. Прохоренко, В. В. Шалимо. - Мн.: Беларусь, 1991. - 493 с.: ил., с. 185-188, Рис. 2.109).Register 10.1 is designed to store the binary value of the number γ of shift digits necessary to obtain the normalized value of the sum

of the next jth character, where j = 1, 2, ..., T, approximating the encoded sequence by shifting the value of the statistical parameter n _{j, i of the} next jth character, where j = 1, 2, ..., T, approximating the encoded sequence coming from the normalization unit 7 and issuing the generated value to the first information input of the comparator 10.2. Register 10.1 can be performed, for example, on K555IR11A microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus , 1991 .-- 493 p.: Ill., P. 185-188, Fig. 2.109).

 Comparator 10.2 is designed to compare the values of the numbers received at its first input (input A) and second input (input B). Comparator 10.2 can be performed, for example, on K561IP2 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus , 1991 - 493 p.: Ill., P. 382-385).

очередного символа j-й, где j = 1, 2, . . . , T, аппроксимирующей кодируемой последовательности из значения статистического параметра n_j,i очередного символа j-й, где j = 1, 2, ..., T, аппроксимирующей кодируемой последовательности. Логический элемент ИЛИ 10.3 может быть выполнен, например, на микросхемах типа К155ЛЛ1 (см. Цифровые интегральные микросхемы: Справ./М. И. Богданович, И. Н. Грель, В. А. Прохоренко, В. В. Шалимо. - Мн.: Беларусь, 1991. - 493 с.: ил., стр. 60, 62, Рис. 2.15.).The OR logic element 10.3 is designed to generate a signal of a unit level if the number of pulses received from the second additional control input of the third register of the normalizing shift 10 is less than the value that displays the number of bits required to obtain the normalized value of the sum

the next character is the jth, where j = 1, 2,. . . , T, approximating the encoded sequence from the value of the statistical parameter n _{j, i of the} next character of the jth, where j = 1, 2, ..., T, approximating the encoded sequence. The OR 10.3 logic element can be performed, for example, on K155LL1 type microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991. - 493 p.: Ill., P. 60, 62, Fig. 2.15.).

очередного символа j-й, где j = 1, 2, ..., T, аппроксимирующей кодируемой последовательности. Регистр 10.4 может быть выполнен, например, на микросхемах К555ИР11А (см. Цифровые интегральные микросхемы: Справ./М. И. Богданович, И. Н. Грель, В. А. Прохоренко, В. В. Шалимо. - Мн.: Беларусь, 1991. - 493 с.: ил., с. 185-188, Рис. 2.109).Register 10.4 is designed to write into it the values of the statistical parameter n _{j, i of the} next character of the jth, where j = 1, 2, ..., T, approximating the encoded sequence, its sequential shift in the direction of the highest digits by γ digits and issuing the generated normalized value of the amount

the next character is the jth, where j = 1, 2, ..., T, which approximates the encoded sequence. Register 10.4 can be performed, for example, on K555IR11A microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus , 1991 .-- 493 pp., Ill., Pp. 185-188, Fig. 2.109).

 The counter 10.5 is designed to count the number of pulses from the second additional control input of the third register of the normalizing shift 10 to the counting input (input C) of the counter 10.5 and issuing the counted number to the second input (input B) of the comparator 10.2. The counter 10.5 can be performed, for example, on K155IE4 type microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 133, 135, Fig. 2.66.).

 The logical element And 10.6 is designed to ensure the passage of control signals from the second additional control input of the third register of the normalizing shift 10 to the second control input (input W2) of the register 10.4 in the event that the output signal of the logical element OR 10.3 takes a single value. The logical element I 10.6 can be performed, for example, on microcircuits of the type K176LI1 (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 p.: Ill., P. 313, 314, Fig. 3.21).

очередного символа j-й, где j = 1, 2, ..., T, аппроксимирующей кодируемой последовательности.The first right shift register 11 shown in FIG. 18, is intended to shift by one bit in the direction of the least significant bits of the normalized value of the sum

the next character is the jth, where j = 1, 2, ..., T, which approximates the encoded sequence.

 Register 11 can be performed, for example, on K555IR11A microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus , 1991 .-- 493 p.: Ill., P. 185-188, Fig. 2.109).

очередного символа j-й, где j = 1, 2, ..., T, аппроксимирующей кодируемой последовательности.The second right shift register 12 is identical to the first right shift register 11 shown in FIG. 18, and is intended to be shifted by one bit in the direction of the upper bits of the normalized value

the next character is the jth, where j = 1, 2, ..., T, which approximates the encoded sequence.

 The second register of the right shift 12 can be performed, for example, on K555PR11A microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 p.: Ill., P. 185-188, Fig. 2.109).

 Subtractor 13 is designed to subtract from the value of the number coming from the output of the code slot register 22 to the second input of subtractor 13, the value of the number coming from the output of the first switching unit 15 to the first input of subtracter 13. Subtractor 13 is an adder operating in the subtraction mode. The scheme of the subtractor 13 is known, for example, is given in the book: P. P. Maltsev et al. "Digital Integrated Circuits: A Guide. - M.: Radio and Communications, 1994, p. 76. It can be implemented, for example, on microcircuit K555IM7 (see VL Shilo "Popular digital microcircuits". - M .: Radio and communications, 1987, p. 159-161).

 The comparator 14 is designed to compare the value of the number coming from the output of the register of the code interval 22 to the second information input of the comparator 14, with the value of the number coming from the output of the first register of the normalizing shift 8 to the first information input of the comparator 14. If the value of the number coming to the second information input of the comparator 14, it is less than the value of the number supplied to its first information input, then at the output of the comparator 14 a zero level control signal is generated (a zero value of ennoy β). Otherwise, at the output of the comparator 14, a control signal of a unit level is formed (a unit value of the variable β is formed). The comparator circuit 14 is known, for example, is given in the book: P. P. Maltsev et al. "Digital Integrated Circuits: A Guide". - M .: Radio and communications, 1994, p. 83 and can be implemented, for example, on the chip K555SP1 (see V. L. Shilo "Popular digital circuits." - M: Radio and communications, 1987, p. 183 )

очередного символа j-й аппроксимирующей кодируемой последовательности, поступающего с выхода первого регистра правого сдвига 11 на второй информационный вход первого блока коммутации 15, при поступлении на управляющий вход первого блока коммутации 15 управляющего сигнала единичного уровня, и проключения на первый вход сумматора 19 и на первый вход вычитателя 13, соединенных с выходом первого блока коммутации 15, нормализованного значения суммы

очередного символа j-й аппроксимирующей кодируемой последовательности, поступающего с выхода второго регистра нормализующего сдвига 9 на первый информационный вход первого блока коммутации 15, при поступлении на управляющий вход первого блока коммутации 15 управляющего сигнала нулевого уровня.The first switching unit 15 shown in FIG. 19, is intended for switching to the first input of the adder 19 and to the first input of the subtractor 13, connected to the output of the first switching unit 15, shifted by one bit towards the lower bits of the normalized value of the sum

the next character of the jth approximating encoded sequence coming from the output of the first register of the right shift 11 to the second information input of the first switching unit 15, when the control signal of the first switching unit 15 receives a unit level control signal, and switching to the first input of the adder 19 and the first the input of the subtractor 13 connected to the output of the first switching unit 15, the normalized value of the sum

the next character of the jth approximating encoded sequence coming from the output of the second register of the normalizing shift 9 to the first information input of the first switching unit 15, when the control signal of the first switching unit 15 receives a zero level control signal.

 The first switching unit 15 consists of an inverter 15.1, logical elements AND 15.2.1, 15.2.2, ..., 15.2.k, logical elements AND 15.3.1, 15.3.2, ..., 15.3.k, logical elements OR 15.4.1, 15.4.2, ..., 15.4.k. The first inputs of the logic elements 15.2.1, 15.2.2, ..., 15.2.k are combined into a single information bus, which is the second information input of the first switching unit 15. The first inputs of the logical elements 15.3.1, 15.3.2, ..., 15.3.k are combined into a single information bus, which is the first information input of the first switching unit 15. The second inputs of the logic elements 15.2.1, 15.2.2, ..., 15.2.k are combined, connected to the input of the inverter 15.1 and are the control input of the first block switching 15. The second inputs of the logic elements 15.3.1, 15.3.2, ..., 15.3.k are combined and connected They are connected to the inverter output 15.1. The outputs of the logic elements AND 15.2.1, 15.2.2, ..., 15.2.k are connected, respectively, with the first inputs of the logic elements OR 15.4.1, 15.4.2,. . ., 15.4.k, the second inputs of which are connected, respectively, to the outputs of the logic elements AND 15.3.1, 15.3.2, ..., 15.3.k. The outputs of the logic elements OR 15.4.1, 15.4.2, ..., 15.4.k are combined into a single information bus, which is the output of the first switching unit 15.

 The inverter 15.1 is designed to convert a unit level signal at its input to a zero level signal at its output and to convert a zero level signal at its input to a unit level signal at its output. The inverter 15.1 can be performed, for example, on type K561LN2 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 pp., Ill., P. 315, 316, Fig. 3.26).

 The logical elements AND 15.2.1, 15.2.2, ..., 15.2.k are designed to ensure the binary signals of the second information input of the first switching unit 15 are switched on to the first inputs of the logical elements OR 15.4.1, 15.4.2,. . ., 15.4.k if there is a signal of a unit level at the control input of the first switching unit 15 and binary signals of the zero level are turned on to the first inputs of logic elements OR 15.4.1, 15.4.2, ..., 15.4.k if there is a first on the control input block switching 15 signal zero level. Logic elements I 15.2.1, 15.2.2, ..., 15.2.k can be performed, for example, on microcircuits of the type K176LI1 (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V.A. Prokhorenko, V.V. Shalimo .-- Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 313.314, Fig. 3.21).

 Logic elements AND 15.3.1, 15.3.2, ..., 15.3.k are designed to ensure the binary signals of the first information input of the first switching unit 15 are switched on to the second inputs of the logical elements OR 15.4.1, 15.4.2,. . ., 15.4.k if there is a signal of the zero level at the control input of the first switching unit 15 and the binary signals of the zero level are turned on to the first inputs of logic elements OR 15.4.1, 15.4.2, ..., 15.4.k if there is a first at the control input unit switching 15 signal of a single level. Logic elements I 15.3.1, 15.3.2, ..., 15.3.k can be performed, for example, on microcircuits of the type K176LI1 (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V.A. Prokhorenko and V.V. Shalimo .-- Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 313, 314, Fig. 3.21).

 Logic elements OR 15.4.1, 15.4.2, ..., 15.4.k are intended for the logical addition of binary signals of a single or zero level arriving at their first and second inputs. Logic Elements OR 15.4.1, 15.4.2,. . . , 15.4.k can be performed, for example, on type K155LL1 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. .: Belarus, 1991. - 493 p.: Ill., P. 60, 62, Fig. 2.15.).

очередного символа j-й аппроксимирующей кодируемой последовательности, поступающего с выхода второго регистра правого сдвига 12 на второй информационный вход второго блока коммутации 16, при поступлении на управляющий вход второго блока коммутации 16 управляющего сигнала единичного уровня, и проключения на первый информационный вход третьего блока коммутации 17, соединенного с выходом второго блока коммутации 16, нормализованного значения двоичного числа

очередного символа j-й аппроксимирующей кодируемой последовательности, поступающего с выхода третьего регистра нормализующего сдвига 10 на первый информационный вход второго блока коммутации 16, при поступлении на управляющий вход второго блока коммутации 16 управляющего сигнала нулевого уровня.The second switching unit 16 is identical to the first switching unit 15 shown in FIG. 19, and is intended for switching to the first information input of the third switching unit 17, shifted by one bit in the direction of the least significant bits of the normalized value of the binary number

the next character of the jth approximating encoded sequence, coming from the output of the second register of the right shift 12 to the second information input of the second switching unit 16, upon entering the control input of the second switching unit 16 of the control signal of a single level, and switching to the first information input of the third switching unit 17 connected to the output of the second switching unit 16, the normalized value of the binary number

the next character of the jth approximating encoded sequence coming from the output of the third register of the normalizing shift 10 to the first information input of the second switching unit 16, when the control signal of the second switching unit 16 receives a zero level control signal.

 The second switching unit 16 consists of an inverter 16.1, logical elements AND 16.2.1, 16.2.2, ..., 16.2.k, logical elements AND 16.3.1, 16.3.2, ..., 16.3.k, logical elements OR 16.4.1, 16.4.2, ..., 16.4.k. The first inputs of the logic elements 16.2.1, 16.2.2, ..., 16.2.k are combined into a single information bus, which is the second information input of the second switching unit 16. The first inputs of the logical elements 16.3.1, 16.3.2, ..., 16.3.k are combined into a single information bus, which is the first information input of the second switching unit 16. The second inputs of the logic elements 16.2.1, 16.2.2, ..., 16.2.k are combined, connected to the input of the inverter 16.1 and are the control input of the second block switching 16. The second inputs of the logic elements 16.3.1, 16.3.2, ..., 16.3.k are combined and connected Connected to the inverter output 16.1. The outputs of the logical elements AND 16.2.1, 16.2.2, ..., 16.2.k are connected, respectively, with the first inputs of the logical elements OR 16.4.1, 16.4.2,. . ., 16.4.k, the second inputs of which are connected, respectively, to the outputs of the logic elements AND 16.3.1, 16.3.2, ..., 16.3.k. The outputs of the logic elements OR 16.4.1, 16.4.2, ..., 16.4.k are combined into a single information bus, which is the output of the second switching unit 16.

 Inverter 16.1 is designed to convert a unit level signal at its input to a zero level signal at its output and to convert a zero level signal at its input to a unit level signal at its output. Inverter 16.1 can be performed, for example, on type K561LN2 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 pp., Ill., P. 315, 316, Fig. 3.26).

 Logic elements AND 16.2.1, 16.2.2, ..., 16.2.k are designed to provide the binary signals of the second information input of the second switching unit 16 to the first inputs of the OR logical elements 16.4.1, 16.4.2,. . ., 16.4.k if there is a unit level signal at the control input of the second switching unit 16 and binary signals of the zero level are turned on to the first inputs of logic elements OR 16.4.1, 16.4.2, ..., 16.4.k if there is a second block 16 switching signal zero level. Logic elements I 16.2.1, 16.2.2, ..., 16.2.k can be performed, for example, on microcircuits of the type K176LI1 (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V.A. Prokhorenko, V.V. Shalimo .-- Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 313, 314, Fig. 3.21).

 The logical elements AND 163.1, 16.3.2, ..., 16.3.k are designed to ensure the binary signals of the first information input of the second switching unit 16 are connected to the second inputs of the logical elements OR 16.4.1, 16.4.2, ..., 16.4.k if there is a zero level signal at the control input of the second switching block 16 and binary zero signals are switched to the first inputs of logic elements OR 16.4.1, 16.4.2, ..., 16.4.k if there is a single signal at the control input of the second switching block 16 level. Logic elements I 16.3.1, 16.3.2, ..., 16.3.k can be performed, for example, on microcircuits of the type K176LI1 (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V.A. Prokhorenko, V.V. Shalimo .-- Mn .: Belarus, 1991.- 493 pp., Ill., Pp. 313, 314, Fig. 3.21).

 Logic elements OR 16.4.1, 16.4.2, ..., 16.4.k are intended for the logical addition of binary signals of a single or zero level arriving at their first and second inputs. Logic Elements OR 16.4.1, 16.4.2,. . . , 16.4.k can be performed, for example, on type K155LL1 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991. - 493 p.: Ill., P. 60, 62, Fig. 2.15.).

 The third switching unit 17 is identical to the first switching unit 15 shown in FIG. 19, and is intended for switching to the information input of the second normalization block 18 and the information input of the first register of the left shift 23, connected to the output of the third switching unit 17, of a binary value coming from the output of the subtractor 13 to the second information input of the third switching unit 17 upon receipt of the control the input of the third switching unit 17 of the control signal of a single level, and switching to the information input of the second normalization unit 18 and the information input of the first register of the left shift 23, connect data with the output of the third switching unit 17, a binary value coming from the output of the second switching unit 16 to the first information input of the third switching unit 17, upon receipt of a zero level control signal at the control input of the third switching unit 17.

 The third switching unit 17 consists of an inverter 17.1, logical elements AND 17.2.1, 17.2.2, ..., 17.2.k, logical elements AND 17.3.1, 17.3.2,. . . , 17.3.k, logical elements OR 17.4.1, 17.4.2, ..., 17.4.k. The first inputs of the logic elements 17.2.1, 17.2.2, ..., 17.2.k are combined into a single information bus, which is the second information input of the third switching unit 17. The first inputs of the logic elements 17.3.1, 17.3.2, ..., 17.3.k are combined into a single information bus, which is the first information input of the third switching unit 17. The second inputs of the logic elements 17.2.1, 17.2.2, ..., 17.2.k are combined, connected to the input of the inverter 17.1 and are the control input of the third block switching 17. The second inputs of the logic elements 17.3.1, 17.3.2, ..., 17.3.k are combined and sub connected to the inverter output 17.1. The outputs of the logical elements AND 17.2.1, 17.2.2, ..., 17.2.k are connected, respectively, with the first inputs of the logical elements OR 17.4.1, 17.4.2,. . ., 17.4.k, the second inputs of which are connected, respectively, to the outputs of the logic elements AND 17.3.1, 17.3.2, ..., 17.3.k. The outputs of the logic elements OR 17.4.1, 17.4.2, ..., 17.4.k are combined into a single information bus, which is the output of the third switching unit 17.

 The inverter 17.1 is designed to convert a unit level signal at its input to a zero level signal at its output and to convert a zero level signal at its input to a unit level signal at its output. Inverter 17.1 can be performed, for example, on microcircuits of the type K561LN2 (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 pp., Ill., P. 315, 316, Fig. 3.26).

 The logical elements AND 17.2.1, 17.2.2, ..., 17.2.k are designed to ensure the binary signals of the second information input of the third switching unit 17 are switched on to the first inputs of the OR logical elements 17.4.1, 17.4.2, ..., 17.4 .k if there is a signal of a unit level at the control input of the third switching unit 17 and the binary signals of the zero level are switched on to the first inputs of logic elements OR 17.4.1, 17.4.2, ..., 17.4. k if there is a zero level signal at the control input of the third switching unit 17. Logic elements I 17.2.1, 17.2.2, ..., 17.2.k can be performed, for example, on microcircuits of the type K176LI1 (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V.A. Prokhorenko, V.V. Shalimo .-- Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 313, 314, Fig. 3.21).

 Logic elements AND 17.3.1, 17.3.2, ..., 17.3.k are designed to ensure the binary signals of the first information input of the third switching unit 17 are switched on to the second inputs of the OR logical elements 17.4.1, 17.4.2,. .., 17.4.k if there is a zero level signal at the control input of the third switching unit 17 and the binary zero level signals are turned on to the first inputs of logic elements OR 17.4.1, 17.4.2, ..., 17.4.k if there is a control input third switching unit 17 signal of a single level. Logic elements I 17.3.1, 17.3.2, ..., 17.3.k can be performed, for example, on microcircuits of the type K176LI1 (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V.A. Prokhorenko, V.V. Shalimo - Mn .: Belarus, 1991 .-- 493 p .: ill., P. 313, 314, Fig. 3.21).

 Logic elements OR 17.4.1, 17.4.2, ..., 17.4.k are intended for the logical addition of binary signals of a single or zero level arriving at their first and second inputs. Logic Elements OR 17.4.1, 17.4.2,. . . , 17.4.k can be performed, for example, on type K155LL1 microcircuits (see Digital Integrated Circuits Ref./M. I. Bogdanovich, I.N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn. : Belarus, 1991. - 493 p.: Ill., P. 60, 62, Fig. 2.15.).

The second normalization unit 18 shown in FIG. 20, is intended to determine the number α of the upper digits of the jth binary value of the lower coding boundary. The determined number α of the most significant bits of the jth binary value of the lower coding boundary can take the values 0, 1, 2, ..., log ₂ w. The second normalization block 18 consists of registers 18.1 and 18.2, comparators 18.3 and 18.4, counter 18.5, OR gate 18.6 and register 18.7.

Information inputs (inputs X1, X2, ..., Xk) of register 18.1 are connected to the corresponding information inputs (inputs X1, X2, ..., Xk) of register 18.2, combined into a single information bus, which is the information input of the second normalization block 18. The first control input (input W1) of register 18.1 connected to the first control input (input W1) of register 18.2 is the first additional control input of the second normalization unit 18. The second control input (input W2) of register 18.1 connected to the second control input (input W2 ) register 18.2 and account the input (input C) of the counter 18.5 is the second additional control input of the second normalization block 18. The outputs k and k-1 of the upper bits of register 18.1 are connected to the inputs A2 and A1 of the comparator 18.3, respectively. The outputs k and k-1 of the upper bits of the register 18.2 are connected to the inputs A2 and A1 of the comparator 18.4, respectively. The match output (in Fig. 20 is indicated by the symbol "=") of the comparator 18.3 is connected to the first input of the OR gate 18.6. The match output (in Fig. 20 is indicated by the symbol "=") of the comparator 18.4 is connected to the second input of the OR gate 18.6. The output of the OR gate 18.6 is connected to the control input (input W) of the register 18.7. The output of the counter 18.5 is connected to the information input (input A) of the register 18.7. To the input X _{k + 1 of the} register 18.2, as well as to the input B1 of the comparator 18.4, signals of the zero level "0" are constantly supplied. At the inputs B1 and B2 of the comparator 18.3, as well as at the input B2 of the comparator 18.4, signals of the unit level "1" are constantly supplied.

 Registers 18.1 and 18.2 are designed to record and store a binary value coming from the output of the third switching unit 17 to the information input of the second normalization unit 18 and a shift in the direction of the senior bits of this value. Registers 18.2 and 18.3 can be performed, for example, on K555IR11A microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn. : Belarus, 1991 .-- 493 p.: Ill., P. 185-188, Fig. 2.109).

 Comparator 18.3 is designed to compare the two high-order bits of the output signal of register 18.1, received at input A of comparator 18.3 with binary number 11, fed to input B of comparator 18.3. If the compared values coincide, the output of the comparator 18.3 generates a signal of a single level, otherwise - a signal of zero level. Comparator 18.3 can be performed, for example, on type K155IR1 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 178-180, Fig. 2.99, 2.100).

 Comparator 18.4 is designed to compare the two high-order bits of the output signal of register 18.2 received at input A of comparator 18.4 with a binary number 10 supplied to input B of comparator 18.4. When the compared values coincide, the output of the comparator 18.4 generates a signal of a single level, otherwise - a signal of zero level. Comparator 18.4 can be performed, for example, on type K155IR1 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 178-180, Fig. 2.99, 2.100).

 The counter 18.5 is designed to count the number of pulses supplied to its input, which is equal to the number α of the higher bits of the jth binary value of the lower coding boundary and the formation of its binary representation at the output of the counter 18.5. The counter 18.5 can be performed, for example, on K155IE4 type microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 - 493 pp., Ill., Pp. 133, 135, Fig. 2.66.).

 The OR 18.6 logic element is designed to generate a unit level signal at its output if at the output of at least one of the comparators 7.3 or 7.4 a unit level signal is generated. The logical element OR 18.6 can be performed, for example, on chips of type K155LL1 (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 - 493 p.: Ill., P. 60, 62, Fig. 2.15.).

 Register 18.7 is designed to record a binary number coming from the output of counter 18.5 when a unit level signal is generated at the output of one of the comparators 18.3 or 18.4. Register 18.7 can be performed, for example, on K555IR11A microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus , 1991 .-- 493 p.: Ill., P. 185-188, Fig. 2.109).

 The adder 19 is designed to summarize the binary value read from the output of the first switching unit 15 to the first input of the adder 19, and the binary value read from the output of the lower coding boundary register 25 to the second input of the adder 19. The adder 19 circuit is known, for example, is given in the book: L. A. Maltseva and others. "Fundamentals of digital technology." - M.: Radio and Communications, 1986, pp. 53-54, Fig. 51 and can be performed, for example, on the K155IM1 microcircuit (see V. L. Shilo “Popular Digital Microcircuits.” - M.: Radio and Communications, 1987, p. 156).

 The first coding parameter memory 20 is designed to store a pre-set binary value of the lower coding limit of 2w binary bits and output it to the second information input of the lower coding boundary register 25 when a control signal is supplied to the additional control input of the first coding parameter memory block 20. As the first block memory encoding parameters 20 can be used static random access memory (RAM), the construction scheme of which known and given, for example, in the book: V.A. Batushev, V.N. Veniaminov et al. "Microcircuits and their application: a reference manual". - M.: Radio and communications, 1983, p. 175, fig. 5.12. The first memory block of encoding parameters 20 can be implemented, for example, on a memory chip K537RU8 (see V. I. Korneichuk, V. P. Tarasenko "Computing devices on microcircuits: a Reference". - K .: Tekhnika, 1988, p. 85 -87).

 The second block of encoding parameter memory 21 is designed to store a preset binary value of the code interval of length w of binary digits and output it to the second information input of the code interval register 22 when a control signal is supplied to the additional control input of the second block of encoding parameter memory 21. As a second memory block coding parameters 21 can be used statistical random access memory (RAM), the construction scheme of which is known and For example, in the book: V.A. Batushev, V.N. Veniaminov et al. "Microcircuits and their application: a reference manual". - M.: Radio and Communications, 1983, p. 175, Fig. 5.12. The second block of encoding parameter memory 21 can be implemented, for example, on a K537RU8 memory microcircuit (see V.I. Korneychuk, V.P. Tarasenko, “Computing devices on microcircuits: A Reference.” - K .: Tehnika, 1988, p. 85 -87).

 The code slot register 22 shown in FIG. 21, is intended for recording a pre-set binary value of the code interval with a length w of binary bits from the output of the second block of encoding parameter memory 21, subsequent recording of the j-th binary value of the code interval from the output of the first left shift register 23, storing and issuing it to the second input of the subtractor 13 and the second information input of the comparator 14. The code slot register 22 contains a switching module 22.1 and a register 22.2. The first information input of the switching module 22.1 is the first information input of the code interval register 22. The second information input of the switching module 22.1 is the second information input of the code interval register 22. The control input of the switching module 22.1 is the second additional control input of the code interval register 22. Control input (input W ) register 22.2 is the first additional control input of the code interval register 22. The output of the switching module 22.1 is connected to information by the input (input X) of the register 22.2. The output of register 22.2 is the output of the code slot register 22.

The switching module 22.1 is identical to the first switching unit 15 shown in FIG. 19, and is intended for switching to the information input (input X) of register 22.2 of a binary value supplied to the second information input of the code interval register 22 when it receives a control signal of a single level at the second additional control input of the code interval register 22, and switching to the information input (input X) register 22.2 binary value coming
to the first information input of the code interval register 22 upon receipt of the second additional control input of the code interval register 22 of the zero level control signal.

 The switching module 22.1 consists of an inverter 22.1.1, logical elements AND 22.1.2.1, 22.1.2.2, ..., 22.1.2.k, logical elements AND 22.1.3.1, 22.1.3.2,. .., 22.1.3.k, logical elements OR 22.1.4.1, 22.1.4.2, ..., 22.1.4.k. The first inputs of the logic elements 22.1.2.1, 22.1.2.2, ..., 22.1.2. k combined into a single information bus, which is the second information input of the switching module 22.1. The first inputs of the logic elements 22.1.3.1, 22.1.3.2, ..., 22.1.3.k are combined into a single information bus, which is the first information input of the switching module 22.1. The second inputs of the logical elements AND 22.1.2.1, 22.1.2.2, ..., 22.1.2.k are combined, connected to the input of the inverter 22.1.1 and are the control input of the switching module 22.1. The second inputs of the logical elements AND 22.1.3.1, 22.1.3.2, ..., 22.1.3.k are combined and connected to the output of the inverter 22.1.1. The outputs of the logic elements AND 22.1.2.1, 22.1.2.2,. .., 22.1.2.k are connected, respectively, with the first inputs of the logic elements OR 22.1.4.1, 22.1.4.2,. .., 22.1.4.k, the second inputs of which are connected, respectively, to the outputs of the logical elements AND 22.1.3.1, 22.1.3.2, ..., 22.1.3.k. The outputs of the logical elements OR 22.1.4.1, 22.1.4.2, ..., 22.1.4.k are combined into a single information bus, which is the output of the switching module 22.1.

 The inverter 22.1.1 is intended for converting a unit level signal at its input to a zero level signal at its output and for converting a zero level signal at its input to a unit level signal at its output. The inverter 22.1.1 can be performed, for example, on type K561LN2 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 p.: Ill., P. 315, 316, Fig. 3.26).

 The logical elements AND 22.1.2.1, 22.1.2.2, ..., 22.1.2.k are designed to ensure the binary signals of the second information input of the switching module 22.1 are connected to the first inputs of the OR logical elements 22.1.4.1, 22.1.4.2, ..., 22.1.4.k if there is a unit level signal at the control input of the switching module 22.1 and the binary signals of the zero level are turned on at the first inputs of the logic elements OR 22.1.4.1, 22.1.4.2,. . . , 22.1.4.k if there is a zero level signal at the control input of the switching module 22.1. Logic elements I 22.1.2.1, 22.1.2.2, ..., 22.1.2.k can be performed, for example, on microcircuits of the type K176LI1 (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V.A. Prokhorenko, V.V. Shalimo .-- Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 313, 314, Fig. 3.21).

 The logical elements AND 22.1.3.1, 22.1.3.2, ..., 22.1.3.k are designed to ensure the binary signals of the first information input of the switching module 22.1 are connected to the second inputs of the OR logical elements 22.1.4.1, 22.1.4.2, ..., 22.1.4.k if there is a zero level signal at the control input of the switching module 22.1 and the binary zero level signals are switched on to the first inputs of OR gates 22.1.4.1, 22.1.4.2,. . . , 22.1.4.k if there is a unit level signal at the control input of the switching module 22.1. Logical elements AND 22.1.3.1, 22.1.3.2, ..., 22.1.3. k can be performed, for example, on microcircuits of type K176LI1 (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus , 1991. - 493 p.: Ill., P. 313, 314, Fig. 3.21).

 Logic elements OR 22.1.4.1, 22.1.4.2, ..., 22.1.4.k are intended for the logical addition of binary signals of a single or zero level arriving at their first and second inputs. Logic elements OR 22.1.4.1, 22.1.4.2, ..., 22.1.4.k can be performed, for example, on microcircuits of the type K155LL1 (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V.A. Prokhorenko, V.V. Shalimo. - Mn .: Belarus, 1991. - 493 pp., Ill., P. 60, 62, Fig. 2.15.).

 The register 22.2 is intended for writing a binary value into it from the output of the switching module 22.1, storing it and issuing the code interval 22 to the output of the register. Register 22.2 can be performed, for example, on K555IR11A microcircuits (see Digital Integrated Circuits: Ref./M. I Bogdanovich, I.N. Grel, V.A. Prokhorenko, V.V. Shalimo.

 The first left shift register 23 is shown in FIG. 22 and is designed to shift in the direction of the higher bits of the jth binary value of the code interval received at its information input from the output of the third switching unit 17 by the number α of the highest bits of the jth binary value of the lower coding limit, defined in the second normalization block 18. First register left shift 23 consists of register 23.1, comparator 23.2, logical element OR 23.3, register 23.4, counter 23.5, logical element AND 23.6.

 The information input (input X) of the register 23.4 is the information input of the first register of the left shift 23. The information input (input X) of the register 23.1 is the control input of the first register of the left shift 23. The control input (input W) of the register 23.1 and the first control input connected to it ( the input W1) of register 23.4 is the first additional control input of the first register of the left shift 23. The counting input (input C) of the counter 23.5 and the second input of the logical element And 23.6 connected to it is the second additional control input of the first Registers left shift counter 23. The reset input (R In) is 23.5 to third additional control input of the first left shift register 23. The output register 23.1 is connected to a first input (input A) of the comparator 23.2. The output of the counter 23.5 is connected to the second input (input B) of the comparator 23.2. The mismatch output (in Fig. 22 is indicated by the symbol "<") of the comparator 23.2 is connected to the first input of the OR gate 23.3. The output of the match (in Fig. 22 is indicated by the symbol "=") of the comparator 23.2 is connected to the second input of the OR gate 23.3. The output of the OR gate 23.3 is connected to the first input of the AND gate 23.6. The output of the logical element And 23.6 is connected to the second control input (input W2) of the register 23.4. The output of register 23.4 is the output of the first register of the left shift 23.

 Register 23.1 is intended for storing the number α of the highest bits of the jth binary value of the lower coding boundary, which is fed to the control input of the first register of the left shift 23 and the output of this number to the first information input of the comparator 23.2. Register 23.1 can be performed, for example, on K555IR11A microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus , 1991 .-- 493 p.: Ill., P. 185-188, Fig. 2.109).

 Comparator 23.2 is designed to compare the values of the numbers received at its first input (input A) and second input (input B). Comparator 23.2 can be performed, for example, on K561IP2 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus , 1991 .-- 493 p.: Ill., P. 382-385).

 The OR 23.3 logic element is designed to generate a unit level signal at its output in the event that a unit level signal is supplied to at least one of its inputs. The OR 23.3 logic element can be performed, for example, on K155LL1 type microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 p.: Ill., P. 60, 62, Fig. 2.15.).

 Register 23.4 is designed to write to it the value received at the information input of the first register of left shift 23. Register 23.4 can be performed, for example, on K555IR11A microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V.A. Prokhorenko, V.V. Shalimo .-- Mn .: Belarus, 1991 - 493 pp., Ill., Pp. 185-188, Fig. 2.109).

 The counter 23.5 is designed to count the number of pulses from the second additional control input of the first register of the left shift 23 to its counter input (input C) and output the result to the second input (input B) of the comparator 23.2. The counter 23.5 can be performed, for example, on K155IE4 type microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 - 493 pp., Ill., Pp. 133, 135, Fig. 2.66.).

 The AND 23.6 logic element is designed to ensure the passage of control signals from the second additional control input of the first left shift register 23 to the control input (input W2) of the register 23.4, when a unit level signal is generated at the output of the OR 23.3 logic element. The logic element I 23.6 can be performed, for example, on microcircuits of the type K176LI1 (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 - 493 p.: Ill., P. 313, 314, Fig. 3.21).

 The second left shift register 24 shown in FIG. 23, is intended for a shift in the direction of the high bits received at its information input from the output of the adder 19 of the jth binary value of the lower coding boundary by the number α of the high bits of the jth binary value of the lower coding boundary, defined in the second normalization block 18. The second register is left shift 24 consists of a register 24.1, a comparator 24.2, a logical element OR 24.3, a register 24.4, a counter 24.5, a logical element AND 24.6, a register 24.7 and a counter 24.8.

 The information input (input X) of register 24.4 is the information input of the second left shift register 24. The information input (input X) of register 24.1 is the control input of the second left shift register 24. The control input (input W) of register 24.1 and the first control input connected to it ( the input W1) of the register 24.4 is the first additional control input of the second register of the left shift 24. The counting input (input C) of the counter 24.5 and the second input of the logical element And 24.6 connected to it are the second additional control input of the second p left shift register 24. The reset input (input R) of the counter 24.5 and the reset input (input R) of the counter 24.8 connected to it is the third additional control input of the second register of the left shift 24. The output of the register 24.1 is connected to the first input (input A) of the comparator 24.2. The output of the counter 24.5 is connected to the second input (input B) of the comparator 24.2. The mismatch output (in Fig. 23 is indicated by the symbol "<") of the comparator 24.2 is connected to the first input of the OR gate 24.3. The match output (in Fig. 23 is indicated by the symbol "=") of the comparator 24.2 is connected to the second input of the OR gate 24.3. The output of the OR gate 24.3 is connected to the first input of the AND gate 24.6, the output of which is connected to the second control input (input W2) of the register 24.4, the control input (input W) of the register 24.7 and the counting input (input C) of the counter 24.8. The outputs 1, 2, ..., k of register 24.4 are combined into a single information bus, which is the overwrite output of the second left shift register 24, and additionally, the output k of register 24.4 is connected to the information input (input X) of register 24.7. The outputs 1, 2, ..., k of register 24.7 are combined into a single information bus, which is the output of the second left shift register entry 24. The outputs 1, 2, ..., k of counter 24.8 are combined into a single information bus, which is the counting output of the second register left shift 24.

 Register 24.1 is intended for storing the number α of the highest bits of the jth binary value of the lower coding boundary, which is fed to the control input of the second register of the left shift 24 and the output of this number to the first information input of the comparator 24.2. Register 24.1 can be performed, for example, on K555IR11A microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo - Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 185-188, Fig. 2.109).

 Comparator 24.2 is designed to compare the values of the numbers supplied to its first input (input A) and second input (input B). Comparator 24.2 can be performed, for example, on K561IP2 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus , 1991 .-- 493 p.: Ill., P. 382-385).

 The OR 24.3 logic element is designed to generate a unit level signal at its output in the event that a unit level signal is supplied to at least one of its inputs. The logical element OR 24.3 can be performed, for example, on chips of type K155LL1 (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 p.: Ill., P. 60, 62, Fig. 2.15.).

 Register 24.4 is designed to write to it the value received at the information input of the second register of the left shift 24 and the shift in the direction of the senior bits of this value by the number of bits determined in the second normalization block 18. Register 24.4 can be performed, for example, on K555IR11A microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 - 493 pp., Ill., P. 185 -188, Fig. 2.109).

 The counter 24.5 is designed to count the number of pulses from the second additional control input of the second register of the left shift 24 to its counting input (input C) and issuing the counted number to the second input (input B) of the comparator 24.2. The counter 24.5 can be performed, for example, on type K155IE4 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 133, 135, Fig. 2.66.).

 The logical element And 24.6 is designed to ensure the passage of control signals from the second additional control input of the second register of the left shift 24 to the control input (input W2) of the register 24.4 and to the control input (input W) of the register 24.7 if the output of the logical element OR 24.3 unit level signal. The logic element I 24.6 can be performed, for example, on chips of the type K176LI1 (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 p.: Ill., P. 313, 314, Fig. 3.21).

 Register 24.7 is designed to record the output value of the high-order bit of register 24.4 into it by a control signal from the output of the logical element And 24.6 and output this value to the output of the second register of the left shift. Register 24.7 can be performed, for example, on K555IR11A microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus , 1991 .-- 493 p.: Ill., P. 185-188, Fig. 2.109).

 The counter 24.8 is designed to count the number of pulses coming from the output of the logical element And 24.6 to its counting input (input C) and to issue the counted number to the counting output of the second register of the left shift 24. Counter 24.5 can be performed, for example, on type K155IE4 chips (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991. - 493 pp., Ill., P. 133, 135, Fig. 2.66.).

 The coding lower bound register 25 is identical to the code slot register 22 shown in FIG. 21, and is intended for recording a preset binary value of the lower coding limit of 2w binary bits from the output of the first coding parameter memory block 20, subsequent recording of the jth binary value of the lower coding limit from the output of the second left shift register 24, storing and issuing it to the second the adder input 19. The lower encoding register 25 contains a switching module 25.1 and a register 25.2. The first information input of the switching module 25.1 is the first information input of the lower coding boundary register 25. The second information input of the switching module 25.1 is the second information input of the lower coding boundary register 25. The control input of the switching module 25.1 is the second additional control input of the lower coding boundary register 25. Control input (input W) of register 25.2 is the first additional control input of the register of the lower coding limit 25. The output is switching of the module 25.1 is connected to data input (X) register 25.2. The output of register 25.2 is the output of the register of the lower encoding boundary 25.

 The switching module 25.1 is identical to the first switching unit 15 shown in FIG. 19, and is intended for switching to the information input (input X) of register 25.2 of a binary value supplied to the second information input of the register of the lower coding limit 25 when a lower level coding signal 25 is received at the second additional control input of the register of the control unit level signal and for switching to the information input (input X) of register 25.2 of a binary value fed to the first information input of the register of the lower coding limit 25 when it is received at the second additional control input register and the lower bound of the coding 25 of the control signal of the zero level.

 The switching module 25.1 consists of an inverter 25.1.1, logical elements AND 25.1.2.1, 25.1.2.2, ..., 25.1.2.k, logical elements AND 25.1.3.1, 25.1.3.2,. .., 25.1.3.k, logical elements OR 25.1.4.1, 25.1.4.2, ..., 25.1.4.k. The first inputs of the logic elements 25.1.2.1, 25.1.2.2, ..., 25.1.2. k combined into a single information bus, which is the second information input of the switching module 25.1. The first inputs of the logic elements 25.1.3.1, 25.1.3.2, ..., 25.1.3.k are combined into a single information bus, which is the first information input of the switching module 25.1. The second inputs of the logic elements AND 25.1.2.1, 25.1.2.2, ..., 25.1.2.k are combined, connected to the input of the inverter 25.1.1 and are the control input of the switching module 25.1. The second inputs of the logic elements AND 25.1.3.1, 25.1.3.2, ..., 25.1.3.k are combined and connected to the output of the inverter 25,1.1. The outputs of the logic elements AND 25.1.2.1, 25.1.2.2,. .., 25.1.2.k are connected, respectively, with the first inputs of the logic elements OR 25.1.4.1, 25.1.4.2,. .., 25.1.4.k, the second inputs of which are connected, respectively, to the outputs of the logic elements AND 25.1.3.1, 25.1.3.2, ..., 25.1.3.k. The outputs of the logic elements OR 25.1.4.1, 25.1.4.2, ..., 25.1.4.k are combined into a single information bus, which is the output of the switching module 25.1.

 The inverter 25.1.1 is designed to convert a unit level signal at its input to a zero level signal at its output and to convert a zero level signal at its input to a unit level signal at its output. The inverter 25.1.1 can be performed, for example, on type K561LN2 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 p.: Ill., P. 315, 316, Fig. 3.26).

 Logic elements I 25.1.2.1, 25.1.2.2, ..., 25.1.2.k are designed to ensure the binary signals of the second information input of the switching module 25.1 are switched on to the first inputs of the logical elements OR 25.1.4.1, 25.1.4.2, ..., 25.1.4.k if there is a unit level signal at the control input of the switching module 25.1 and binary signals of the zero level are turned on at the first inputs of the logic elements OR 25.1.4.1, 25.1.4.2,. . . , 25.1.4.k if there is a zero level signal at the control input of the switching module 25.1. Logic elements I 25.1.2.1, 25.1.2.2, ..., 25.1.2.k can be performed, for example, on microcircuits of the type K176LI1 (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V.A. Prokhorenko, V.V. Shalimo - Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 313, 314, Fig. 3.21).

Logic elements I 25.1.3.1, 25.1.3.2, ..., 25.1.3.k are designed to ensure the binary signals of the first information input of the switching module 25.1 are switched on to the second inputs of the logical elements OR 25.1.4.1, 25.1.4.2,. .., 25.1.4.k if there is a zero level signal at the control input of the switching module 25.1 and the binary zero level signals are switched on to the first inputs of the logic elements OR 25.1.4.1, 25.1.4.2,. . . , 25.1.4.k if there is a unit level signal at the control input of the switching module 25.1. Logic elements I 25.1.3.1, 25.1.3.2, ..., 25.1.3.k can be performed, for example, on microcircuits of type K176LI1
(see Digital Integrated Circuits; Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991. - - 493 pp., ill. , p. 313, 314, Fig. 3.21).

 Logic elements OR 25.1.4.1, 25.1.4.2, ..., 25.1.4.k are intended for the logical addition of binary signals of a single or zero level arriving at their first and second inputs. Logic elements OR 25.1.4.1, 25.1.4.2, ..., 25.1.4.k can be performed, for example, on microcircuits of the type K155LL1 (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V.A. Prokhorenko, V.V. Shalimo .-- Mn .: Belarus, 1991 .-- 493 pp., Ill., P. 60, 62, Fig. 2.15.).

 Register 25.2 is designed to write to it a binary value from the output of the switching module 25.1, store it and issue the lower coding limit register 25 to the output of the register 25. Register 25.2 can be performed, for example, on K555IR11A microcircuits (see Digital Integrated Circuits: Ref./M. I. Bogdanovich, I.N. Grel, V.A. Prokhorenko, V.V. Shalimo .-- Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 185-188, Fig. 2.109).

The memory block of the approximating encoded sequences 26 shown in FIG. 24, is intended for recording and storing j-approximating encoded sequences read from the output of the second left shift register 24 and computing the length L _{j of} each j-th approximating encoded sequence. The memory block of the approximating encoded sequences 26 consists of a counter 26.1, a decoder 26.2, switching modules 26.3 and 26.4, drives 26.5.1, 26.5.2, ..., 26.5.T, drives 26.6.1, 26.6.2, ..., 26.6.T, the first and second multiplexing modules 26.7 and 26.8. The inputs of the switching modules 26.3 and 26.4 are, respectively, the recording input and the counting input of the memory block of the approximating encoded sequences 26. The control inputs of the drives 26.5.1, 26.5.2, ..., 26.5. T, 26.6.1, 26.6.2, ..., 26.6.T are combined and are the second additional control input of the memory block of the approximating encoded sequences 26. The control input of the first multiplexing module 26.7 is the control input of the memory block of the approximating encoded sequences 26. Counting input ( the input C) of the counter 26.1 is the first additional control input of the memory block of the approximating encoded sequences 26. The output of the counter 26.1 is connected to the input of the decoder 26.2 and the selection inputs of the first and second modes multiplex hive 26.7 and 26.8. The output of the decoder 26.2 is connected to the inputs of the choice of switching modules 26.3 and 26.4. The outputs 1,2, ..., T of the switching modules 26.3 and 26.4 are connected, respectively, with the information inputs of the drives 26.5.1, 26.5.2, ..., 26.5.T and 26.6.1, 26.6.2, ... , 26.6.T. The outputs of the drives 26.5.1, 26.5.2, ..., 26.5. T are connected, respectively, with 1, 2, ..., T information inputs of the first multiplexing module, and the outputs of the drives 26.6.1, 26.6.2, ..., 26.6. T are connected, respectively, with 1,2, ..., T information inputs of the second multiplexing module. The output of the first multiplexing module 26.7 is the read output of the memory block of the approximating encoded sequences 26. The output of the second multiplexing module 26.8 is the output of the comparison of the memory block of the approximating encoded sequences 26.

 The counter 26.1 is designed to count the number of pulses arriving at the first additional control input of the memory block of the approximating encoded sequences 26 and outputting the result to the input of the decoder 26.2. The counter 26.1 can be performed, for example, on K155IE4 type microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 133, 135, Fig. 2.66.).

 The decoder 26.2 is designed to convert a binary number at its input into a binary signal of a unit level, appearing on that of its outputs, the number of which corresponds to the number of the approximating encoded sequence. The decoder 26.2 can be performed, for example, on type K155IV1 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo - Mn .: Belarus , 1991. - 493 p.: Ill., P. 227, 228, Fig. 2.149, 2.150).

 The switching module 26.3 shown in FIG. 25, is designed to switch j-approximating encoded sequences to the corresponding j-th drive 26.5.1, 26.5.2, ..., 26.5.T, in accordance with the signal received at the input of the selection of the switching module 26.3 from the decoder 26.2. Switching module 26.3 consists of logical elements AND 26.3.1.1, 26.3.1.2,. .., 26.3.1.k; 26.3.2.1, 26.3.2.2, ..., 26.3.2.k, ..., 26.3.T.1, 26.3. T. 2,. . . , 26.3.T.k. The first inputs of the logical elements AND 26.3.1.1, 26.3.1.2,. . ., 26.3.1.k, 26.3.2.1, 26.3.2.2, ..., 26.3.2.k; ..., 26.3.T.1, 26.3. T.2, ..., 26.3.T.k are combined into a single information bus, which is the information input of the switching module 26.3. The second inputs of the logical elements AND 26.3.1.1, 26.3.1.2, ..., 26.3.1.k, the logical elements AND 26.3.2.1, 26.3.2.2, ..., 26.3.2.k, ... 26.3.T.1, 26.3.T.2, ..., 26.3. T. k are connected and combined into a single information bus, which is the input of the choice of the switching module 26.3, and in addition, combined with the outputs of the logical elements AND 26.3.1.1, 26.3.1.2, ..., 26.3.1.k, logical elements AND 26.3 .2.1, 26.3.2.2, ..., 26.3.2.k, ... of logical elements AND 26.3. T. 1, 26.3.T.2, ..., 26.3.T.k into single information buses, which are, respectively, output 1, output 2, ..., output T of the switching module 26.3.

 Logical elements AND 26.3.1.1, 26.3.1.2,. .., 26.3.1.k; 26.3.2.1, 26.3.2.2,. .., 26.3.2.k; ..., 26.3.T.1, 26.3.T.2, ..., 26.3.T.k are intended for the logical multiplication of binary signals arriving at their inputs. Logical elements And 26.3.1.1, 26.3.1.2, ..., 26.3.1.k; 26.3.2.1, 26.3.2.2,. .., 26.3.2.k, ..., 26.3.T.1, 26.3.T.2, ..., 26.3.Tk can be performed, for example, on type K176LI1 microcircuits (see Digital Integrated Circuits: Ref. ./M. I. Bogdanovich, I.N. Grel, V.A. Prokhorenko, V.V. Shalimo .-- Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 313, 314, Fig. 3.21).

The switching module 26.4 is identical to the switching module 26.3 shown in FIG. 25, and is intended to switch on the binary value of the length L _{j of} each j-th approximating encoded sequence to the corresponding j-th drive 26.6.1, 26.6.2, ..., 26.6.T, in accordance with the signal received at the input of the module selection switching 26.4 from the output of the decoder 26.2. Switching module 26.3 consists of logic elements AND 26.4.1.1, 26.4.1.2, ..., 26.4.1.k; 26.4.2.1, 26.4.2.2, ..., 26.4.2.k; ..., 26.4.T.1, 26.4.T.2, ..., 24.3. T. k. The first inputs of the logical elements AND 26.4.1.1, 26.4.1.2, ..., 26.4.1. k; 26.4.2.1, 26.4.2.2, ..., 26.4.2.k; ..., 26.4.T.1, 26.4.T.2, ..., 26.4. Tk are combined into a single information bus, which is the information input of the switching module 26.4. The second inputs of the logical elements AND 26.4.1.1, 26.4.1.2,. . . , 26.4.1.k, logical elements AND 26.4.2.1, 26.4.2.2, ..., 26.4.2. k, ... of logical elements AND 26.4.T.1, 26.4.T.2, ..., 26.4.Tk are connected and combined into a single information bus, which is the input of the choice of the switching module 26.4, and in addition, combined with the outputs of the logical elements AND 26.4.1.1, 26.4.1.2, ..., 26.4.1.k, logical elements AND 26.4.2.1, 26.4.2.2, ..., 26.4.2.k, ... logical elements AND 26.4.T .1, 26.4.T.2, ..., 26.4. T. k into single information buses, which are, respectively, output 1, output 2, ..., output T of the switching module 26.4.

 Logical elements AND 26.4.1.1, 26.4.1.2,. .., 26.4.1.k; 26.4.2.1, 26.4.2.2,. .., 26.4.2.k; ..., 26.4.T.1, 26.4.T.2, ..., 26.4.T.k are intended for the logical multiplication of binary signals arriving at their inputs. Logical elements And 26.4.1.1, 26.4.1.2, ..., 26.4.1.k; 26.4.2.1, 26.4.2.2,. .., 26.4.2.k; ..., 26.4.T.1, 26.4.T.2, ..., 26.4.Tk can be performed, for example, on microcircuits of the type K176LI1 (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991. - 493 pp., Ill., P. 313, 314, Fig. 3.21).

 Drives 26.5.1, 26.5.2, ..., 26.5.T are intended for writing and storing j-approximating encoded sequences read from the output of the second left shift register 24. As drives 26.5.1, 26.5.2,. . ., 26.5.T, a register made, for example, on K555IR11A microcircuits can be used (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo - Mn .: Belarus, 1991 - 493 p.: Ill., P. 185-188, Fig. 2.109).

Drives 26.6.1, 26.6.2, ..., 26.6.T are designed to record and store the length L _{j of} each j-th approximating encoded sequence read from the counting output of the second register of the left shift 24. As drives 26.6.1, 26.6 .2, ..., 26.6.T, a register made, for example, on K555IR11A microcircuits can be used (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V.V. Shalimo .-- Mn .: Belarus, 1991 .-- 493 p .: ill., P. 185-188, Fig. 2.109).

The first multiplexing module 26.7 shown in FIG. 26, is intended to switch off the value of the jth approximating encoded sequence from the output of one of the drives 26.5.1, 26.5.2, ..., 26.5.T, in accordance with the address code coming from the output of the counter 26.1 if there is an enable signal on the control the input of the memory block of the approximating encoded sequences 26. The first multiplexing module 26.7 consists of multiplexers 26.7.1, 26.7.2, ..., 26.7.k. The inputs S1 of the multiplexers 26.7.1, 26.7.2, ..., 26.7.k are combined into a single information bus, which is the first information input of the first multiplexing module 26.7. The inputs S2 of the multiplexers 26.7.1, 26.7.2, ..., 26.7.k are combined into a single information bus, which is the second information input of the first multiplexing module 26.7. . . . The inputs S _{T of the} multiplexers 26.7.1, 26.7.2, ..., 26.7.k are combined into a single information bus, which is the T-th information input of the first multiplexing module 26.7. The permission inputs (inputs E) of the multiplexers 26.7.1, 26.7.2, ..., 26.7.k are connected and are the control input of the first multiplexing unit 26.7. The address inputs (inputs A) of the multiplexers 26.7.1, 26.7.2, ..., 26.7.k are connected and are the input of the selection of the first multiplexing unit 26.7. Outputs of multiplexers 26.7.1, 26.7.2,. . ., 26.7.k are combined into a single information bus, which is the output of the first multiplexing module 26.7.

Multiplexers 26.7.1, 26.7.2, ..., 26.7.k are designed to switch the binary signal of one of the inputs (input S1, S2, ..., S _T ) to its output, in accordance with the address code received at its address input (input A), if there is an enable signal at its enable input (input E). The scheme of multiplexers 26.7.1, 26.7.2, ..., 26.7.k is known, is given in the book: L. A. Maltsev et al. "Fundamentals of digital technology". - M.: Radio and Communications, 1986, p. 52, Fig. 48, and can be implemented, for example, on K155KP5 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 pp., Ill., P. 161, 162, Fig. 2.83).

The second multiplexing module 26.8 shown in FIG. 27, is intended to include the value of the length L _{j of} each j-th approximating encoded sequence from the output of the selected drive 26.6.1, 26.6.2,. . . , 26.6. T, in accordance with the address code coming from the output of the counter 26.1 to the comparison output of the memory block of the approximating encoded sequences 26. The second multiplexing module 26.8 consists of multiplexers 26.8.1, 26.8.2,. . ., 26.8.k. Inputs S1 of multiplexers 26.8.1, 26.8.2,. . . , 26.8.k are combined into a single information bus, which is the first information input of the second multiplexing module 26.8. The inputs S2 of the multiplexers 26.8.1, 26.8.2, ..., 26.8.k are combined into a single information bus, which is the second information input of the second multiplexing module 26.8. ... Inputs S _{T of} multiplexers 26.8.1, 26.8.2, ..., 26.8. k combined into a single information bus, which is the T-th information input of the second multiplexing module 26.8. The address inputs (inputs A) of the multiplexers 26.8.1, 26.8.2, ..., 26.8.k are connected and are the selection input of the second multiplexing unit 26.8. The outputs of the multiplexers 26.8.1, 26.8.2, ..., 26.8.k are combined into a single information bus, which is the output of the first multiplexing module 26.8.

Multiplexers 26.8.1, 26.8.2, ..., 26.8.k are designed to switch the binary signal of one of the inputs (input S1, S2, ..., S _T ) to its output, in accordance with the address code received at address input (input A). Multiplexer circuit 26.8.1, 26.8.2,. .., 26.8.k is known, is given in the book: L. A. Maltsev and others. "Fundamentals of digital technology." - M.: Radio and Communications, 1986, p. 52, Fig. 48, and can be implemented, for example, on K155KP5 microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo. - Mn .: Belarus, 1991 .-- 493 pp., Ill., P. 161, 162, Fig. 2.83).

The comparison unit 27 shown in FIG. 28, is intended to compare the value of the length L _{j of the} jth approximating encoded sequence read from the output of the comparison of the memory block of the approximating encoded sequences 26 with the value of the maximum permissible length L _pr read from the output of the memory block of the maximum permissible length 28 and issuing a resolution signal of zero value by input selection memory block approximating encoded sequences 2.

 Comparison block 27 consists of registers 27.1, 27.2 and comparator 27.3. The control inputs (W inputs) of the registers 27.1 and 27.2 are connected and are an additional control input of the comparison unit 27. The information input (input X) of the register 27.1 is the first information input of the comparison unit 27. The information input (input X) of the register 27.2 is the second information input of the comparison unit 27. The output of register 27.1 is connected to the first input (input A) of comparator 27.3, the second input of which (input B) is connected to the output of register 27.2. The output of the comparator 27.3 is the output of the comparison unit 27.

Register 27.1 is designed to write to it a binary number of length L _{j of the} jth approximating encoded sequence read from the output of the comparison of the memory block of the approximating encoded sequences 26. Register 27-1 can be performed, for example, on K555IR11A microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I. N. Grel, V. A. Prokhorenko, V. V. Shalimo .-- Mn .: Belarus, 1991 .-- 493 pp., Ill., Pp. 185-188, Fig. . 2.109).

Register 27.2 is intended for writing into it the values of the maximum permissible length L _pr , read from the output of the memory block of the maximum permissible length 28. Register 27.2 can be performed, for example, on K555IR11A microcircuits (see Digital Integrated Circuits: Ref. / M. I. Bogdanovich , I.N. Grel, V.A. Prokhorenko, V.V. Shalimo .-- Mn .: Belarus, 1991.- 493 pp .: ill., Pp. 185-188, Fig. 2.109).

 Comparator 27.3 is designed to compare the values of the numbers supplied to its inputs. The comparator circuit is known, for example, is given in the book: P.P. Maltsev et al. "Digital Integrated Circuits: A Guide. - M .: Radio and Communications, 1994, p. 83 and can be implemented, for example, on the K555SP1 chip (see. Digital Integrated Circuits: Ref. / M. I. Bogdanovich, I.N. Grel, V.A. Prokhorenko, V.V. Shalimo .-- Mn .: Belarus, 1991.- 493 pp., Ill., Pp. 268, 272, Fig. 2.190).

The memory block of the maximum permissible length 28 is designed to store the binary value of the maximum permissible length L _pr and read it to the second information input of the comparison unit 27. As a memory block of the maximum permissible length 28, a static random access memory (RAM) can be used, the construction scheme of which is known and is given, for example, in the book: V. A. Batushev, V.N. Veniaminov et al. "Microcircuits and their application: Reference manual". - M.: Radio and Communications, 1983, p. 175, Fig. 5.12. The memory block of the maximum permissible length 28 can be implemented, for example, on a memory chip K537RU8 (see V.I. Korneychuk, V.P. Tarasenko "Computing devices on microcircuits: A Reference". - K .: Tekhnika, 1988, p. 85 -87).

 The claimed device for compressing an encoded sequence from infinite alphabet characters into an encoded sequence of binary symbols works as follows.

Previously, in the first block of encoding parameter memory 20, the binary value of the lower coding boundary is written 1.00 ... 0 with a length of 2w binary bits, and in the second block of memory of encoding parameter 21 a binary value of the code interval is 0.00 ... 0 with a length w of binary bits. In the memory block of the approximating encoded sequences 2, the values of T of the pre-formed approximating encoded sequences are recorded. In the memory block of the maximum permissible length 28, the value of the predetermined maximum permissible length L _pr

 The encoded sequence of infinite alphabet characters is input to the compression device of the encoded sequence of infinite alphabet characters in the encoded binary character sequence shown in FIG. 7. and is read to the input of a block of discrete coded sequence 1.

The next symbol of the encoded sequence, with its corresponding voltage level, is supplied to the first information inputs of the comparators 1.1.1, 1.1.2, ..., 1.1.q, compared in each of them with the voltage level supplied to the second information inputs from the reference modules voltage 1.2.1, 1.2.2, ..., 1.2.q. According to the unit level control signal shown in FIG. 29 (a), each of the comparators generates an output signal of a unit level if the voltage value corresponding to the next character of the encoded sequence supplied to its first input is greater than or equal to the voltage value corresponding to the character of the ordered q-ary alphabet supplied to its second input. Otherwise, the comparator generates an output signal of zero level. The voltage level at the output of each of the reference voltage modules is selected in such a way that U _1.2.1 > U _1.2.2 >...> U _1.2.q. From the outputs of the comparators 1.1.1, 1.1.2, ..., 1.1.q, signals of the unit and zero levels are fed to the input of the encoder, which converts the number of the senior input with the unit level into a parallel binary code at its output. The obtained value of the next symbol of the discrete encoded sequence in parallel binary code is written to the memory module of the discrete encoded sequence 1.4.

 According to the zero level control signal shown in FIG. 29 (a) applied to the control input (input S) of multiplexer 4.6, which is the second control input of the selection unit 4 of the approximating sequence closest to the encoded one, the second information input (input Y) of multiplexer 4.6 is switched off and written to all memory cells the storage register of the minimum amount 4.5 of the selection block 4 of the approximating sequence closest to the encoded information signal in the form of a code combination consisting of single characters "1", which ensures the initial filling register storage minimum amount 4.5 maximum value of the stored number.

 According to the control signals received at the input of the selection of the memory block of the approximating encoded sequences 2 shown in FIG. 29 (6), from the output of the block of approximating encoded sequences 2, from each jth, where j = 1, 2, ..., T, of the approximating encoded sequence, sequentially starting from the first character to the last, read the next character j -th approximating encoded sequence to the information input of the switch 3. According to the control signal, the form of which is shown in FIG. 29 (c) applied to the additional control input of the switch 3, the key 3.1 is closed and the information input of the switch 3 is connected to its second output. The next character of the jth approximating encoded sequence is fed to the input of the identification unit 5 and simultaneously fed to the first inputs of m comparators 5.1.1, 5.1.2, ..., 5.1.m, where it is compared with the values of all the characters of the ordered m-ary alphabet, read from m memory modules 5.2.1, 5.2.2, ..., 5.2.m to the second inputs of the respective comparators.

When identifying the next character of the jth approximating encoded sequence with the i-th character of an ordered m-ary alphabet, the comparator is triggered
5.1.i and at the i-th output of the identification unit 5, a signal of a unit level is formed. At 1, 2, ..., m-th, with the exception of the i-th, the outputs of the identification block 5 remains the signal of the zero level.

According to the control signal supplied to the additional control input of the statistical parameter calculation unit 6 shown in FIG. 29 (g), the following actions are performed:
these control signals are counted by a counter 6.2, previously set to state m. The output signal of the counter 6.2, numerically equal to the value N _{j of the} next character of the jth, where j = 1, 2, ..., T, approximates the encoded sequence, which is the first output of the unit for calculating statistical parameters 6, is fed to the input of register 7.1 and the input of the register 7.2, connected in parallel (to the corresponding bits). This binary number is fed to the information input of register 7.1, starting from the third digit, and to the information input of register 7.2, it is fed, starting from the second digit (counting from the least significant bits). The inputs of the first and second digits (counting from the least significant digits), register 7.1, and the inputs of the first digit (counting from the least significant digits), register 7.2, constantly supply zero level signals "0". According to the control signal shown in FIG. 29 (e), arriving at the first additional control input of the normalization block 7, binary numbers are written to the information inputs of registers 7.1 and 7.2 in the memory cells of these registers. From the output of register 7.1, a binary number is fed to the first input (input A) of comparator 7.3, the second input of which is constantly supplied with a code combination 00 ... 0011 with a length W of binary digits. From the output of register 7.2, a binary number is fed to the first input (input A) of the comparator 7.4, the second input of which is constantly supplied with a code combination 00 ... 0010 with a length W of binary digits. At the beginning of the unit-level signal at the output of the comparator 7.3 or at the output of the comparator 7.4, when the values at the inputs coincide, the output signal of the counter 7.5 is recorded (which displays the number of γ bits of the shift and is preset to zero) in register 7.7. According to the control signal shown in FIG. 29 (e), arriving at the second control input of the first normalization unit 7, a shift is made in the direction of the least significant bits of the contents of registers 7.1 and 7.2;
at the beginning of this control unit signal, the output of the i-th logical element AND 6.1.i generates a unit-level signal, at the end of which the i-th counter 6.3.i (preset to the state 000 ... 01, the length W of the binary digits) will increase value per unit. The output signal of the adder 6.5.h, where h = m-2, numerically equal to the value of Q _{j, m of the} next character of the jth, where j = 1, 2, ..., T, approximates the encoded sequence, which is the second output of the statistical calculation unit 6, is fed to the information input (input X) of register 8.4 of the first register of the normalizing shift 8. Inverted binary signal of the second input of the logical element AND 6.1. m is the fifth output of the unit for calculating statistical parameters 6. The value of the counter 6.3.i, numerically equal to the value of the binary number n _{j, i of the} next character of the jth, where j = 1, 2, ..., T, which approximates the encoded sequence, through multiplexers 6.4.1, 6.4.2, ..., 6.4.k, where k = log ₂ m, switches to the fourth output of the unit for calculating statistical parameters 6. The output signals of the counters 6.3.1, 6.3.2, ..., 6.3. m are summed by adders 6.5.1, 6.5.2, ..., 6.5.h, where h = m-2, and through the ith inputs of the multiplexers are switched to their outputs, which are the output of the sum Q _{j, i of} occurrences of symbols tins of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence in the ordered m-ary alphabet in the part of the jth approximating encoded sequence preceding the next symbol of the jth approximating encoded sequence of the unit for calculating statistical parameters 6.

According to the control signal shown in FIG. 29 (g), coming through the first additional control input of the first register of the normalizing shift 8, the second register of the normalizing shift 9 and the third register of the normalizing shift 10, in the registers 8.1, 9.1, 10.1, respectively, the binary values Q _{j, m} , Q _{j are} recorded _{, i} , n _{j, i of the} next character of the jth, where j = 1, 2, ..., T, approximating the encoded sequence, into the corresponding blocks. The control signals shown in FIG. 29 (h) received at the second additional control inputs of the first register of the normalizing shift 8, the second register of the normalizing shift 9, the third register of the normalizing shift 10, are counted by 8.5, 9.5, 10.5, respectively. If the output signal of the binary counters 8.5, 9.5, 10.5 is less than or equal to the binary number γ of shift digits, then the output of the match (in Fig. 17 is indicated by the symbol "=") or at the output of the mismatch (in Fig. 17 is indicated by the symbol "<") of the comparator 8.2, 9.2, 10.2 a signal of a single level is formed, allowing the passage of control signals coming from the second additional control input of the first register of the normalizing shift 8, the second register of the normalizing shift 9, the third register of the normalizing shift 10, to the second control input (input W2 ) registers 8.4, 9.4, 10.4, respectively. At the beginning of each pulse entering the second control input (input W2) of the registers 8.4, 9.4, 10.4, the contents of the registers 8.4, 9.4, 10.4 are shifted, respectively, towards the lower digits. If the output signal of the binary counters 8.5, 9.5, 10.5 exceeds the binary number γ of shift bits, then the output of the match (in Fig. 17 is indicated by the symbol "=") and the output of the mismatch (in Fig. 17 is indicated by the symbol "<") of the comparator 8.2, 9.2, 10.2, respectively, zero-level signals are generated that prohibit the passage of control signals coming from the second control input of the first register of normalizing shift 8, the second register of normalizing shift 9, the third register of normalizing shift 10, to the second control input (input W2) of registers 8.4, 9.4, 10.4, respectively, through the logical elements AND 8.6, 9.6, 10.6, respectively. According to the control signal shown in FIG. 29 (and), which comes through the third additional control input of the first register of the normalizing shift 8, the second register of the normalizing shift 9, the third register of the normalizing shift 10, the binary counters 8.5, 9.5, 10.5 are set, respectively, to the zero state (reset).

The normalized value of the sum Q _{j, m} , from the output of register 8.4 of the first register of the normalizing shift 8 is supplied to the first information input of the comparator 14, the second information input of which receives the jth binary value of the code interval from the output of the code interval register 22. If the value of the number to the first input of the comparator 14, it is less than the value of the number supplied to the second input of the comparator 14, then at the output of the comparator 14 a control signal of zero level is generated (a zero value of parameter β is generated), to the control input of the first switching unit 15 and in parallel to the control input of the second switching unit 16. Otherwise, at the output of the comparator 14, a unit level control signal is generated (a unit value of parameter β is generated), which is fed to the control input of the first switching unit 15 and in parallel to the control input second switching unit 16. If the control inputs of the first switching unit 15 and the second switching unit 16 receive a signal of the zero level (zero value of the parameter β), then from the output of the inverter 15.1 and from the output of the inverter 16.1 torus to the second input of gates 15.3.1, 15.3.2, ..., 15.3.m, the second input of gates 16.3.1, 16.3.2,. .., 16.3.m, respectively, a unit-level signal will be received, and the second input of the logic elements 15.2.1, 15.2.2,. .., 15.2.m and the second input of logic elements 16.2.1, 16.2.2, ..., 16.2.m will receive a signal of the zero level and the binary value will be connected to the output of the first switching unit 15 and to the output of the second switching unit 16, arriving at the first information input of the first switching unit 15 and the second switching unit 16. Otherwise, if a unit level signal (unit value of parameter β) is supplied to the control input of the switching unit 15 and switching unit 16, then to the second input of the logic elements 15.3.1, 15.3 .2,. .., 15.3.m and to the second input of logic elements 16.3.1, 16.3.2,. .., 16.3.m, respectively, a signal of the zero level will be received, and to the second input of the logic elements 15.2.1, 15.2.2, ..., 15.2.m and to the second input of the logic elements 16.2.1, 16.2.2,. .., 16.2.m, respectively, a unit-level signal will be received and the binary value coming to their second information input from the output of the first register of the right shift 11 and from the output of the second register of the right shift 12 will be switched to the output of the switching unit 15 and the switching unit 16. According to the control signal shown in FIG. 29 (k), arriving at the first control input of the first register of the right shift 11 and the second register of the right shift 12, a record is made in the first register of the right shift 11 and the second register of the right shift, the information signal from the output of register 9.4 and register 10.4, respectively, of the second register normalizing shift 9 and the third register normalizing shift 10, respectively. According to the control signal shown in FIG. 29 (k), which is received at the second control input of the first register of the right shift 11 and the second register of the right shift 12, a shift is made in the direction of the least significant bits of the contents of the first register of the right shift 11 and the second register of the right shift 12, respectively.

 According to the control signal shown in FIG. 29 (d), which arrives at the second control input of the code interval register 22 from a control unit not included in the inventive device and not shown in the figures, a binary number is written from the output of the switching module 22.1 to register 22.2. The output of the switching module 22.1 is paired with the binary number from the output of the second memory block of the encoding parameters 21 if the control signal shown in FIG. 29 (m), arriving at the first control input of the code slot register 22 from a control unit not included in the inventive device and not shown in the figures, takes a single value. If the control signal shown in FIG. 29 (m), received at the first additional control input of the code interval register 22, takes a zero value, then the binary number from the output of the first register of the left shift 23 is switched to the output of the switching module 22.1. The binary number from the output of the register 22.2, which is the output of the code interval register 22, is fed to the second input of the subtractor 13 and to the second information input of the comparator 14. The first input of the subtractor 13 receives a binary number from the output of the first switching unit 15. The subtractor 13 generates a binary difference value numbers received at its first input and a second input, and the resulting value is supplied to the second information input of the third switching unit 17, to the first information input of which the binary value output from the switching unit 16.

 If the control input of the third switching unit 17 from the identification output of the next character of the jth approximating encoded sequence with the last character of the ordered m-ary alphabet of the unit for calculating statistical parameters 6 receives a zero level signal (i ≠ m), then the second input of the logic elements 17.2. 1, 17.2.2, ..., 17.2.m a signal of the zero level will be received, and the second input of the logic elements 17.3.1, 17.3.2, ..., 17.3. a single level signal will be received and the binary value coming to its first information input from the output of the second switching unit 16 will be switched on to the output of the switching unit 17; Otherwise, if a single level signal (i = m) is supplied to the control input of the switching unit 17, then to the second input of logic elements 17.2.1, 17.2.2, ..., 17.2. a signal of a single level is received, and a signal of the zero level is fed to the second input of logic elements 17.3.1, 17.3.2, ..., 17.3.m and a binary value is turned on to the output of the switching unit 17, which arrives at its second information input from the output of the subtractor 13 .

 The binary number from the output of the third switching unit 17, numerically equal to the jth binary value of the code interval, is fed to the input of register 18.1 and the input of register 18.2, connected in parallel and being the information input of the second normalization unit 18. According to the control signal shown in FIG. 29 (n), arriving at the first control input of the second normalization block 18, binary numbers are written to the information inputs of registers 18.1 and 18.2 in the memory cells of these registers. From the output of register 18.1, the two high order bits of the binary number written into it are fed to the first input (input A) of the comparator 18.3, the second combination of which is constantly supplied with code combination 11. From the output of register 18.2, the two high order bits of the binary number written to it are fed to the first and second the inputs (inputs A1 and A2) of the comparator 18.4, the second input of which is constantly supplied with a binary code combination 10. At the beginning of a unit-level signal at the output of the comparator 18.3 or at the output of the comparator 18.4 when the values at the inputs match, it is performed vivo Recording 18.5 counter output signal, α is numerically equal to the number of significant bits of j-th binary value encoding the bottom border and preset to zero state, to the register 18.7. According to the control signal shown in FIG. 29 (o), supplied by the second additional control input of the normalization block 18, a shift is made in the direction of the higher bits of the contents of registers 18.1 and 18.2 and the binary value at the output of the counter 18.5 is increased by a single value.

 Obtained in the second normalization block 18, the binary number α of the highest bits of the jth binary value of the lower coding boundary from the output of register 18.7 is fed to the control input of the first register of the left shift 23 and to the control input of the second register of the left shift 24.

 According to the control signal shown in FIG. 29 (p), received at the first additional control input of the first register of the left shift 23, a binary number is recorded in the register 23.1, received at the control input of the first register of the left shift 23, and a binary number is recorded at the information input of the first register in the register 23.4 left shift 23. The control signals shown in FIG. 29 (p), received at the second additional control input of the first register of the left shift 23, are counted by the counter 23.5. If the output signal of the binary counter 23.5 is less than or equal to the binary number α of the most significant bits of the jth binary value of the lower coding limit, then a unit level signal is generated at one of the outputs of the comparator 23.2, allowing the control signals to pass through the second additional control input of the first left shift register 23 to the second control input (input W2) of the register 23.4. At the beginning of each pulse entering the second control input (input W2) of the register 23.4, the contents of the register 23.4 are shifted towards the higher bits. If the output signal of the binary counter 23.5 exceeds the binary number α of the most significant bits of the jth binary value of the lower coding limit, then a zero level signal is generated at the two outputs of the comparator 8.2, which prohibits the passage of control signals from the second control input of the first register of normalizing shift 23 to the second control the input (input W2) of the register 23.4 through the logical element AND 23.6. According to the control signal shown in FIG. 29 (s), arriving at the third additional control input of the first register of the left shift 23, the binary counter 23.5 is set to zero (reset).

 According to the control signal shown in FIG. 29 (p), received at the first additional control input of the second register of the left shift 24, a binary number is written to the register 24.1, received at the control input of the second register of the left shift 24, and a binary number is written to the register 24.4, received at the information input of the second register left shift 24. The control signals shown in FIG. 29 (p), received at the second additional control input of the second register of the left shift 24, are counted by the counter 24.5. If the output signal of the binary counter 24.5 is less than or equal to the binary number α of the most significant bits of the jth binary value of the lower coding limit, then a unit level signal is generated at one of the outputs of the comparator 24.2, allowing the control signals to pass through the second additional control input of the second left shift register 24 to the second control input (input W2) of the register 24.4. At the beginning of each pulse entering the second control input (input W2) of the register 24.4, the contents of the register 24.4 are shifted to the higher bits. If the output signal of the binary counter 24.5 exceeds the binary number α of the most significant bits of the jth binary value of the lower coding limit, a zero level signal is generated at the two outputs of the comparator 24.2, which prohibits the passage of control signals received from the second control input of the second register of normalizing shift 24 to the second control the input (input W2) of the register 24.4 through the logical element AND 24.6. According to the control signal shown in FIG. 29 (s), arriving at the third additional control input of the second register of the left shift 24, the binary counter 24.5 is set to zero (reset). The counting output of the second register of the left shift 24, from the counter 24.8 receives the length value of each j-th approximating encoded sequence, which is stored in the memory block of the approximating encoded sequences in the corresponding j-th drive 26.6. j. The encoded approximating sequence, from the output of register 24.7, is written to the corresponding j-th drive 26.5.j.

Further, if it is determined in the comparison unit 27 that the value of L _{i is} less than or equal to the value of L _CR , then from the output of the comparison unit 27 to the input of the selection of the memory block of the approximating encoded sequences 2, an enable signal is received which is received at the control input (input W) of the storage register address 2.2, allows the passage of a pre-formed j-th approximating encoded sequence from the memory module 2.4 to the information input of the switch 3.

If it is determined in the comparison unit 27 that the value of L _{i is} greater than the value of L _pr , then from the output of the comparison unit 27 to the input of the selection of the memory block of the approximating encoded sequences 2, an enable signal is not received and reading is not performed from the memory module 2.4 to the information input of the switch 3. After that, the remaining approximating encoded sequences are compared with the encoded sequence and, in the selection block 4 of the approximating sequence closest to the encoded sequence, the one closest to the encoded sequence is selected from them, and the approximated encoded sequence corresponding to the selected approximated encoded sequence is taken as a coded binary sequence. The signal of a single level coming from the output of the selection block 4 of the approximating sequence closest to the encoded one to the control input of the first multiplexing module 26.7 permits reading the approximating encoded sequence corresponding to the selected approximating encoded sequence from the corresponding drive 26.5.1, 26.5.2,. .., 26.5.T, defined by a binary number at the output of the counter 26.1, to the read output of the memory block of the approximating encoded sequences 26 and to the output of the device.

Claims (11)

1. A method of compressing an encoded sequence from infinite alphabet characters into an encoded binary symbol sequence, which consists in pre-setting the binary value of the lower coding limit of 2w binary bits, where w≥2, and the binary value of the code interval with a length of w binary bits, sequentially, starting from the first to the last, read the next character of the encoded sequence consisting of k characters of the alphabet, where k≥2, sequentially, from the first to the last, read the next character of the encoded sequence, consisting of k characters of the ordered m-ary alphabet, where m≥2, and identify it with the i-th, where i = 1, 2, ..., m, with the symbol of the ordered m-ary alphabet, calculate statistical parameters of the next character of the encoded sequence, for which, in the part of the encoded sequence preceding the next character of the encoded sequence, determine the binary number n _{i of} its occurrences, the sum Q _{i of the} binary numbers of occurrences of the characters of the encoded sequence, preceding x the next character of the encoded sequence in the ordered m-ary alphabet, the sum Q _{m of} binary numbers of occurrences of characters of the encoded sequence preceding the last character in the ordered m-ary alphabet, and the binary number N of appearances of all characters of the ordered m-ary alphabet, after which the calculated statistical parameters N, n _i , Q _i and Q _{m of the} next character of the encoded sequence, and then according to the normalized values of the statistical parameters

the next character of the encoded sequence, the binary values of the lower encoding boundary and the code interval are specified, the unchanged part of the binary value of the lower encoding boundary is extracted and read into the encoded sequence, after which the read part of the binary value of the lower encoding boundary is erased, the binary value of the lower encoding limit is shifted in the direction of the higher digits the number of bits of its read part and supplement with the same number of zero binary characters the binary value of the lower gra coding from the lower digits, after clarifying the binary value of the lower coding boundary by the normalized values of statistical parameters

the last character of the encoded sequence, from the high-order bits of the binary value of the lower coding boundary, w binary symbols are sequentially read into the encoded sequence, characterized in that T, where T≤m ^k , are approximated to the encoded sequences consisting of k characters of the ordered m-ary alphabet , and for each of them set the binary value of the lower coding limit of 2w bits and the binary value of the code interval of length w of binary p ranks, sequentially, starting from the first to the last, the next character of the encoded sequence consisting of k characters of the infinite alphabet is read, compared with the characters of the ordered q-ary alphabet, where q≥m, and the closest to the next character of the encoded sequence is selected from them , which is written in a discrete coded sequence, and then from each jth, where j = 1, 2,. .., T, of the approximating encoded sequence sequentially, starting from its first character to the last, read the next character of the jth approximating encoded sequence and identify it with the i-th character of the ordered m-ary alphabet, calculate the statistical parameters N _j , n _{j , i} , Q _{j, i} and Q _{j, m of the} next character of the jth approximating encoded sequence and normalize them, and then according to the normalized values of the statistical parameters

of the next character of the jth approximating encoded sequence, the jth binary values of the lower encoding boundary and the code interval are specified, the unchanged part of the jth binary value of the lower encoding boundary is extracted and read into the jth approximating encoded sequence, after which the read part of the jth binary value of the lower coding boundary, shift the jth binary value of the lower coding boundary in the direction of the higher bits by the number of bits of its read part and supplement with the same number n of binary binary characters, the jth binary value of the lower coding boundary on the side of the least significant bits, after updating the jth binary value of the lower coding boundary on the normalized values of statistical parameters

of the last character of the jth approximating encoded sequence, w binary symbols are sequentially read from the high-order bits of the jth binary value of the lower coding boundary into the jth approximating encoded sequence, then the length L _{j of} each jth approximating encoded sequence is determined and compared given the maximum permissible length L _CR , the jth approximating encoded sequences for which the length L _{j of their} corresponding approximating encoded sequences exceed the maximum permissible length L _pr , are erased, after which the remaining approximating encoded sequences are compared with a discrete encoded sequence, the closest to a discrete encoded sequence is selected from them, and an approximated encoded sequence corresponding to the selected approximated encoded sequence is taken as a coded binary sequence.  2. The method according to claim 1, characterized in that each approximating encoded sequence is formed by choosing k characters from an ordered m-ary alphabet in a random manner.  3. The method according to claim 1, characterized in that for each approximating encoded sequence, the binary value of the lower coding limit is set to 2w binary bits, equal to the binary number 000_0.00_0, consisting of w binary bits in its whole part and from w binary bits in fractional part of it, and set the binary value of the code interval with a length w of binary bits, equal to a binary number 1.00_0 with a length of w-1 binary bits in its fractional part. 4. The method according to p. 1, characterized in that the statistical parameters N _j , n _{j, i} , Q _{j, i} and Q _{j, m of the} next character of the jth approximating encoded sequence are normalized by performing the following sequence of actions: set the normalized value

of the next character of the jth approximating encoded sequence equal to the value of the binary number N _{j of} successively shifted in the direction of the upper digits occurrences of all symbols of the ordered m-ary alphabet in the part of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence γ discharges at which the normalized value

will be in a predefined range of values, then a normalized value is set

of the next character of the jth approximating encoded sequence equal to the value of the binary digit n _{j, i} occurrences of the next character of the jth approximating encoded sequence in the part of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence, and then set the normalized value of the amount

of the next character of the jth approximating encoded sequence equal to the value of the sum of Q _{j, i} binary numbers of occurrences of the symbols of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence in the ordered m-ary alphabet, sequentially shifted in the direction of the upper digits by γ bits , in the part of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence, and set to normalized amount

of the next character of the jth approximating encoded sequence equal to the value of the sum of Q _{j, m} binary numbers of occurrences of symbols of the jth approximating encoded sequence preceding the last character in the ordered m-ary alphabet, in part of the jth the approximating encoded sequence preceding the next character of the jth approximating encoded sequence.  5. The method according to claim 4, characterized in that the lower limit of the predetermined range of values is set equal to a binary number 0.11, and the upper limit of the predetermined range of values is set smaller than the binary number 1.1. 6. The method according to p. 1, characterized in that according to the normalized values of the statistical parameters

of the next character of the jth approximating encoded sequence, the jth binary values of the lower coding boundary and the code interval are specified by the following sequence of actions: if the normalized value of the sum

the next character of the jth approximating encoded sequence is less than the jth binary value of the code interval, then the value of the variable β is set to zero, otherwise the value of the variable β is set to a single value, then if the next character of the jth approximating encoded sequence is not the last character of the ordered m-ary alphabet, then the jth binary value of the lower coding boundary is replaced by the sum of the normalized value of the sum

the next character of the jth approximating encoded sequence and the jth binary value of the lower coding boundary and the jth binary value of the code interval are replaced with the normalized value

the next character of the jth approximating encoded sequence, otherwise, if the next character of the jth approximating encoded sequence is the last character of the ordered m-ary alphabet, then the jth binary value of the lower coding boundary is replaced by the sum of the normalized value of the sum

the next character of the jth approximating encoded sequence and the jth binary value of the lower coding boundary and the jth binary value of the code interval are replaced by the difference between the jth binary value of the code interval and the normalized value of the sum

of the next character of the jth approximating encoded sequence, then, if the variable β has a unit value, then the jth binary values of the lower coding boundary and the code interval are shifted in the direction of their highest digits by one bit.  7. The method according to p. 1, characterized in that the allocation of the unchanged part of the jth binary value of the lower coding boundary is performed by determining the number α of the upper bits of the jth binary value of the lower coding boundary, in which the jth binary is sequentially shifted in the direction of the highest bits the value of the code interval will be in a predefined range of values. 8. The method according to claim 1, characterized in that the maximum permissible length L _pr set at least w + 1 binary digits.  9. The method according to claim 1, characterized in that for comparing each next character of the encoded sequence consisting of k characters of the infinite alphabet with the characters of the ordered q-ary alphabet, the value of each character of the ordered q-ary alphabet is subtracted from the value of the next character of the encoded sequence, and the symbol of the ordered q-ary alphabet with the smallest positive value of the resulting difference is selected closest to the next character of the encoded sequence.  10. The method according to claim 1, characterized in that for comparing each remaining approximating encoded sequence with a discrete encoded sequence, the value of the next symbol of a discrete encoded sequence is subtracted from the value of each subsequent character of the remaining approximating encoded sequence, the absolute values of the resulting differences are summed, and the closest discrete encoded sequence select the remaining approximate encoded sequence with the smallest it received the sum of the differences. 11. A device for compressing a coded sequence from infinite alphabet characters into a coded binary character sequence, comprising an identification unit, the output of which is connected to the information input of the statistical parameter calculation unit, the output of the binary number N _{j of} occurrences of all symbols of the ordered m-ary alphabet in the part of the jth approximating the encoded sequence preceding the next character of the jth approximating encoded sequence is connected to the information input of the first block eye of normalization, the output of the sum Q _{j, m} binary numbers of occurrences of characters of the jth approximating encoded sequence preceding the last character in the ordered m-ary alphabet in the part of the jth approximating encoded sequence preceding the next character of the jth approximating encoded sequence, the output of the sum Q _{j, i} occurrences of symbols j-th approximating encoded sequence preceding the next symbol of j-th approximating encoded sequence in an ordered m-ary alphabet in part j-th approximating encoded sequence preceding the next symbol of j-th approximating encoded sequence and output a binary number n _{j, i} occurrences of the next symbol j-th approximating encoded sequence in part j-th approximating encoded sequence preceding the next symbol of j-th approximating the encoded sequence of the unit for calculating statistical parameters are connected to the information inputs, respectively, of the first, second and third registers but formalizing shift, the control inputs of the first, second and third registers of the normalizing shift are combined and connected to the output of the first normalization block, the identification output of the next character of the jth approximating encoded sequence with the last character of the ordered m-ary alphabet of the statistical parameter calculation unit is connected to the control input of the third block switching, the output of the first register of the normalizing shift is connected to the first information input of the comparator, the outputs of the second and third reg Istr normalizing shift connected to the information inputs, respectively, of the first and second registers of the right shift and in addition to the first information inputs, respectively, of the first and second switching units, the second information inputs of the first and second switching units are connected to the outputs, respectively, of the first and second registers of the right shift, the output of the comparator is connected to the control inputs of the first and second switching units, the output of the first switching unit is connected to the first inputs of the subtractor and adder, the second input of the subtractor is connected to the second information input of the comparator and the output of the code interval register, the output of the second switching unit is connected to the first information input of the third switching unit, the second information input of which is connected to the output of the subtractor, the output of the third switching unit is connected to the information inputs of the second normalization unit and the first the left shift register, the output of the second normalization block is connected to the control inputs of the first and second left shift registers, the information input d of the second register of the left shift is connected to the output of the adder, the second input of which is connected to the output of the register of the lower coding boundary, the first information input of which is connected to the overwrite output of the second register of the left shift, the second information input of the register of the lower coding boundary is connected to the output of the first coding parameter memory, the output of the first register of the left shift is connected to the first information input of the code interval register, the second information input of which is connected to the output of the second a coding parameter memory block, wherein the statistical parameter calculation block, the first and second coding parameter memory blocks are provided with an additional control input, the first normalization block, the first and second right shift registers, the second normalization block, the code interval register and the lower coding boundary register are provided with first and second additional control inputs, and the first, second and third registers of the normalizing shift, the first and second registers of the left shift are equipped with the first, second and third additional control inputs, characterized in that a discrete encoded sequence unit is additionally introduced, the information input of which is the input of the device, and its output is connected to the first information input of the approximation sequence selection block closest to the encoded one, the second information input of which is connected to the first output of the switch, the second the output of which is connected to the input of the identification unit, the information input of the switch is connected to the output of the memory block approximating of the encoded sequences, the selection input of which is connected to the output of the comparison block, the output of the selection block of the approximating sequence closest to the encoded one is connected to the control input of the memory block of the approximating encoded sequences, the recording input and the counting input of which are connected to the recording output and the counting output, respectively, of the second register left shift, the comparison output of the memory block of the approximating encoded sequences is connected to the first information input of the comparison block, w a swarm information input which is connected to the output of the maximum permissible length memory block, the read output of the memory block of approximating encoded sequences is the information output of the device, the switch, the comparison unit and the maximum permissible length memory block having an additional control input, and the discrete encoded sequence block, the approximating memory block encoded sequences, a selection block for the approximating sequence closest to the encoded, and a memory unit approximating encoded sequences are provided first and second complementary control inputs.

Images