SU1367161A1 - Frequency-to-code converter with variable disturbance smoothing factor - Google Patents

Abstract

The invention relates to computing and can be used as a pulse-frequency signal converter into a code or as an autonomous frequency meter. The converter provides the possibility of expanding the range of a constant time that determines the smoothing qualities of the transformation, without significantly complicating its scheme, which allows expanding the range of use of the converter. P {) frequency converter - a code with a variable interference smoothing factor contains three flip-flops 1, 6 and 7, two WLT-HE elements 2 and 3, three frequency dividers 5, 8 to 9, a reversible counter of 4 pulses, two inverters 10 and 11. 1 il.

Description

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: AE 05

The invention relates to computing and can be used as a pulse-frequency signal converter into a code or as an autonomous frequency meter.

The purpose of the invention is to expand the scope of use of the transformation by expanding the range of a constant time of its filter.

The drawing shows the functional diagram of the Converter.

The converter contains the first trigger 1, the first and second elements OR-NOT 2 and 3, the reversible counter 4 pulses, the first frequency divider 5, the second and third triggers 6 and 7, the second and third dividers 8. and 9 frequencies, the first and second inverters 10 and P. In the drawing, reference numerals 12-14 denote, respectively, the clock, control and information inputs of the converter, position 15 -. converter output

The Converter operates as follows.

The next input frequency pulse received at input 14, F (t) puts the RS-flip-flop 1 into a single state, which is rewritten into the D-flip-flop 7 with the arrival of the next clock pulse 2 F at the input 12. The transition of the RS flip-flop 1 into a single state This serves as the beginning of the pulse arriving at the input of the inverter 10, and at the same time causes the P5-flip-flop 1 to transition to the zero state, which is rewritten into the D-flip-flop 7 by the next 2f pulse and causes the end of the pulse at its output. Thus, the frequency pulses F (t), which arrive at arbitrary points in time, are delayed within the interval tl / 2Fjj and become in-phase at a frequency of 2 F. For normal operation of the reversible counter 4, it is necessary that the pulses arriving at its inputs moved apart in time. This function is performed by the inverters 10 and 11, as well as the elements OR-NOT 2 and 3, which prohibit the passage to the inputs of dividers 8 and 9 of pulses that coincide in time. Since these pulses are transmitted through the summing and subtracting channels, the elements 10, 2, 3, 11 also fulfill the function of the subtracting device.

Thus, the operation of the converter in dynamics is described by the system of equations:

N

R

0

“Bjt) 4rj ((t) Fij (t)) dt,

F (t)

N, M, (t) -F

(one)

where n

; (t)

N

n output code; the number (code) defining the smoothing qualities of the converter; the number of bits of counter 4 and divider 5; feedback signal at the output of divider 5. Resha (1) and go to the operator recording form, we get

 - -; (2)

F "(t)

where t

Of

m is the number of binary digits of dividers 8 and 9;

T is the time constant determining the smoothing factor of the converter; (2) it can be seen that the smoothing qualities of the converter, determined by the time constant T, can be smoothly varied over a wide range by changing the value of N. In this case, the scale of the transformation F is variable.

remains unchanged

five

0

Claims (1)

Invention Formula Frequency converter - code with. ; variable interference smoothing factor containing the first trigger, the first and second elements OR-NOT, a reversible pulse counter, the outputs of which are connected to the first inputs of the first frequency divider and are the outputs of the converter, which are the field of use of the inverter due to the expansion of the range of the constant time of its filter, the second and third triggers, the second and third frequency dividers, the first and second inverters, whose outputs are connected to the first inputs, are entered into the converter s homonymous OR-NO elements, outputs of which are connected respectively to the first inputs of the second and third frequency dividers whose outputs are connected 3J367 respectively with the summing and subtracting inputs of the reversing pulse counter, the output of the second trigger is connected to the second input of the first de-. frequency module, the output of which is connected to the input of the second inverter and to the second input of the first element OR NOT, the output of the third flip-flop is connected to the input of the first inverter, with ten the second input of the second element OR NOT 161 and with the R input of the first trigger, the output of which is connected to the D input of the third trigger, the C input of which is combined with the input of the second trigger and is the clock input of the converter, the second inputs of the second and third frequency dividers are the control input of the converter, The S input of the first trigger is the information input of the converter.