SU1338071A1 - Phase automatic frequency control device - Google Patents

Abstract

Invention m. used in the micro-band synchronization systems, frequency synthesizers, where steady-state error is required, the phase is close to zero when there is low-frequency interference in the device. The purpose of the invention is to improve noise immunity. The device contains tunable rr (PG) 1, frequency dividers 2 and 14, phase detector 3, low pass filters (LC) 4, 11, 17 and 19, reference rr 5, difference frequency selector 6, You are OR 7 and 8, a reversible counter 9, a converter 10 digital analogue, electros AND 12 and 13, high pass filter 15, a1 large detector 16, comparators 18, 20 and 2I voltages. The device parameters choose t, obr., So that the IG tuning band on the 1st control input is less than the IG tuning band on the 2nd input. In this case, the control channel from the output of the low-pass filter 4 is called exact, and from the output of the low-pass filter it is called 11 th coarse control channel. Since the passband of the low-pass filter 19 is chosen to be very narrow, a change in the phase of PG 1, as well as the voltage on the detector code 3, does not lead to a change in the code in the counter 9. This explains the high noise immunity of the device, 1 Il. i cl 00 oo CX)

Description

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The invention relates to radio engineering and can be used in wide-range synchronization systems, frequency synthesizers, where a set-up error is required, this phase is close to zero, if there is low-frequency interference in the device.

The purpose of the invention is to increase the noise

In the drawing of an isobrgiken structural circuit the circuit of the device phase locked loop.

The device contains a tunable Mi.rfi PG 1 generator, the first divider 2 frequencies, the phase detector PD 3, the first low-pass filter 4 (LPF), supports} the first generator 5, the difference frequency selector 6, the first 7 and second 8 elements OR, reversible counter 9, converter, 10 digital analog (PCL), second LPF 11, first 12 and second 13 elements And, second frequency divider 14, high-pass filter 15 (HPF), amplitude detector 16, third LPF 17, first KONniapaTOp 18 voltages, fourth FMCh 19, second 20 and third 21 voltage comparators.

The device works as follows.

The parameters of the device are chosen so that the PG 1 tuning band at the first control input is less than the PG 1 tuning band along the second control input, while the channel from the output of the first FR1CH 4 is called exact, and from the output O (1 LF 1 1 - coarse control channel.

When the frequency of PG 1 is not splayed, the PD 3 output has a frequency beat, which, passing through the HPF 15, enters the auxiliary detector 16, the output voltage of which is filtered in the third LPF 17 is compared in the first comparator 18 with some reference. As a result of the comparison, the output of the first comparator 18 has a low signal level, which prohibits the passage of pulses from the output of the second frequency divider 14 through the first 12 and second I3 elements I.

At the same time, pulses, the period of which is equal to the difference frequency between the 6 signals compared in the difference frequency selector, are via 7 or the second 8 elements OR

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is fed to the input of the reversible counter 9 and changes the code in it in such a way that the frequency error between the compared signals in the difference frequency selector 6 is reduced. The appearance of pulses at the nerve or second outputs of the difference frequency selector 6 and their passage through the first 7 or second 8 elements OR is determined by the sign of the frequency error between the signals compared to the difference frequency selector 6.

The code from the outputs of the reversible counter 9, converted to voltage 3 of PCL 10, is fed through the second LPF 11 to the second control input of PG 1 and changes its frequency. As soon as the frequency error between the compared signals of the difference frequency selector 6 is reduced to the magnitude of the capture band f via the exact control channel, the system will become synchronized. In this case, the TO4HONry control channel will be adjusted to the accuracy

to the phase of the frequency of PG 1, and the pulses from the outputs of the selector 6 of the difference frequency are absent.

In the synchronous mode of operation, due to the absence of a beat frequency at the output of the PD 3, nothing is input to the input of the amplitude detector 16 via the HPF 15, so a high signal level is set at the output of the first comparator 18 allowing the passage of pulses from the output of the second frequency divider 14 through the first 12 or the second 13 elements I. In this mode, it is possible to adjust the frequency of PG 1 due to the action of the fourth LPF 19, the second 20 and the third 21 comparators. The bandwidth of the fourth low pass filter 19 1 ,, is selected from the condition I, d "L j,

where - the bandwidth of the highpass filter 15; I am the capture band of the device along the precise control channel.

The reference voltages in the second 20 and third 21 comparators are chosen, respectively, more and less than the fixed value at the output of the PD 3. The difference between the response thresholds of the second 20 and third 21 comparators is insensitive. After setting the synchronism mode voltage at the output PD

3 is in the dead zone of the second 20 n third 21 KONfiiapd tori. In the case of slow-moving frequency of PG 1, the voltage at the output of PD 3 changes, and as soon as this voltage exceeds the threshold of one of the comparators 20 or 21, the output of the corresponding voltage comparator (as determined by the detuning sign) causes the high signal level, allowing the passage of pulses from the output of the second divided frequency 14 through the corresponding element 12 and 13. In this case, the pulses from the output of the second frequency divider are fed to one of the inputs of the reversing counter 9 and change its code for as long as The output at the PD 3 output will not fall into the dead zone of the second 20 and third 21 comparators, whose outputs in this case establish a low level signal. Since the band I, is chosen to be very narrow, changes in the phase of PG 1, as well as the voltage at the output of PD 3, caused, for example, by the microphone effect, do not lead to a change in the code in the reversible counter 9, This explains the high noise immunity This device phase locked loop.

Claims (1)

Invention Formula A phase locked loop device containing a tunable oscillator connected in series, a first frequency divider, a phase detector and a first low-pass filter, the output of which is connected to the first control input of the tunable oscillator, the second phase input A.Cabanov Editor A.Makovska Tehred I.Popovich Editor; A. Tsko Order 4145/56 Circulation 901 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 five Q 5 o 0 five 0 The first detector is connected to the OF.rxoAOM reference oscillator, as well as the differential frequency detector, the first and second inputs of which are connected to the first and second inputs of the phase detector, the first and second elements OR, nepBi, ie, the inputs of which are connected to the outputs of the selector differential frequency, reversible counter, the first and second inputs of which are connected respectively to the outputs of the first and second elements IL1, the pythra converter is an analogue, the code-ory inputs are connected to the outputs of the reversing counter, the second low-pass filter, in Which is connected to the output of the converter digit - analog, and the output - to the second direction of the ry input of a tunable generator, characterized in that, in order to improve the noise immunity between the output of the phase detector and the second input of the first element OR the connected in series high-pass filter, the amplitude detector , the third filter of the lower frequencies, the first voltage comparator and the first element AND, between the output of the first voltage comparator and the second input of the second element OR the second element AND, between the output The reference oscillator and the second inputs of the first and second elements I included a second frequency divider, between the output of the phase detector and the third input of the first element I, a series-connected fourth low-pass filter and a second voltage comparator included, and between the output of the fourth low-pass filter and the third input of the second element And included the third voltage comparator.