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TW200535774A - Thin film transistor array substrate and repairing method thereof - Google Patents

Thin film transistor array substrate and repairing method thereof Download PDF

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Publication number
TW200535774A
TW200535774A TW93111375A TW93111375A TW200535774A TW 200535774 A TW200535774 A TW 200535774A TW 93111375 A TW93111375 A TW 93111375A TW 93111375 A TW93111375 A TW 93111375A TW 200535774 A TW200535774 A TW 200535774A
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Taiwan
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wiring
thin film
scanning
film transistor
wirings
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TW93111375A
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Chinese (zh)
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TWI270044B (en
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Han-Chung Lai
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Au Optronics Corp
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Publication of TWI270044B publication Critical patent/TWI270044B/en

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Abstract

A thin film transistor array comprising a substrate, a plurality of scan lines, a plurality of data lines, a plurality of thin film transistors, a plurality of pixel electrodes and a repair line is provided. The scan lines and the data line are disposed on the substrate to define a plurality of pixel areas. Each thin film transistor is located at one of the pixel areas respectively, and is driven by the corresponding scan line and data line. Each pixel electrode is located at one of the pixel areas respectively, and is electrically connected with the corresponding thin film transistor. A repairing method of the thin film transistor array mentioned above is also provided. The method is performed by forming a repairing line to reconnect a defect scan line. Therefore, a line defect resulted from the defect scan line can be repair as a one defect, two defects or zero defect.

Description

200535774 五、發明說明(1) 發明所屬之技術領域 本發明是有關於一種薄膜電晶體陣列基板(TFT a r r a y s u b s t r a t e )及其修補方法,且特別是有關於一種 可針對掃描配線(s c a η 1 i n e )或共通配線(c 〇 m m ο η 1 i n e )之斷線處進行修補的薄膜電晶體陣列基板及其修補方 法0 先前技術200535774 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a thin film transistor array substrate (TFT array substrate) and a method for repairing the same, and more particularly, it relates to a scanning wiring (sca η 1 ine) or Thin film transistor array substrate for repairing at the broken line of common wild line (c 0 mm ο η 1 ine) and repair method thereof 0 Previous technology

針對多媒體社會之急速進步,多半受惠於半導體元件 或顯示裝置的飛躍性進步。就顯示器而言,陰極射線管 (Cathode Ray Tube ’CRT)因具有優異的顯示品質與其 經濟性,一直獨佔近年來的顯示器市場。然而,對於個人 在桌上操作多數終端機/顯示器裝置的環境,或是以環保 的觀點切入,若以節省能源的潮流加以預測,陰極射線管 因空間利用以及能源消耗上仍存在很多問題,而對於輕、 薄、短、小以及低消耗功率的需求無法有效提供解決之 道。因此,具有高畫質、空間利用效率佳、低消耗功率、 無輻射等優越特性之薄膜電晶體液晶顯示器(Th i n F i 1 mIn response to the rapid progress of the multimedia society, most of them have benefited from the rapid progress of semiconductor components or display devices. In terms of displays, cathode ray tubes (CRTs) have been dominating the display market in recent years because of their excellent display quality and economy. However, for the environment where individuals operate most terminals / display devices on the table, or from the perspective of environmental protection, if the trend of energy saving is predicted, there are still many problems in cathode ray tubes due to space utilization and energy consumption. Demands for light, thin, short, small, and low power consumption cannot effectively provide a solution. Therefore, thin film transistor liquid crystal displays (Th i n F i 1 m) with high image quality, good space utilization efficiency, low power consumption and no radiation

Transistor Liquid Crystal Display ’TFT LCD)已逐漸 成為市場之主流。 薄膜電晶體液晶顯示器(TFT LCD )主要由薄膜電晶 體陣列基板、彩色濾光陣列基板和液晶層所構成,其中%薄 膜電晶體陣列基板是由多個以陣列排列之薄膜電晶^,以 及與每一個薄膜電晶體對應配置之晝素電極(p i二i ^ E 1 e c t r 〇 d e )所組成。而薄膜電晶體係用來作為液曰曰顯厂、Transistor Liquid Crystal Display (TFT LCD) has gradually become the mainstream of the market. A thin film transistor liquid crystal display (TFT LCD) is mainly composed of a thin film transistor array substrate, a color filter array substrate, and a liquid crystal layer. The thin film transistor array substrate is composed of a plurality of thin film transistors arranged in an array ^, and Each thin film transistor is composed of a daylight electrode (pi 2 i ^ E 1 ectr ode) arranged correspondingly. The thin film transistor system is used as a liquid crystal display plant,

200535774 五、發明說明(2) 單元的開關元件。此外,為了控制個別的晝素單元,通常 經由掃描配線(S c a η 1 i n e )與資料配線(D a t e 1 i n e )以 選取特定之晝素,並藉由施於適當的操作電壓,以顯示對 應此晝素之顯示資料。另外,通常會將上述之晝素電極的 · 部分區域覆蓋於掃描配線或是共用配線(C 〇 m m ο η 1 i n e ) . 上,而此重疊的部分即作為儲存電容(C s t ),以使薄膜 電晶體液晶顯示器中的各晝素能夠正常顯示。 值得注意的是,上述薄膜電晶體陣列基板有可能會面 臨線瑕/疵(1 i n e d e f e c t )的問題,而此線瑕疯的問題通 常是因為基板上之配線(掃描配線或共用配線)斷裂所導 致。當基板上之掃描配線發生斷裂的情形時,連接於此掃· 描配線之斷裂處之後的晝素電極將無法顯示,且形成於掃 描配線之斷裂處之後的儲存電容將無法正常顯示,進而造 成薄膜電晶體陣列基板的報廢。 發明内容 因此,本發明的目的就是在提供一種薄膜電晶體陣列 基板及其修補方法,係可針對掃描配線或共通配線之斷線 處進行修補,以避免造成薄膜電晶體陣列基板的報廢。 基於上述目的,本發明提出一種薄膜電晶體陣列基 板,主要係由一基板、多個掃描配線、多個資料配線、多 個薄膜電晶體、多個晝素電極以及一修補線路所構成。多 _ 個掃描配線配置於基板上,且多個掃描配線中包括至少一 瑕疵掃描配線,此瑕疵掃描配線具有一斷線處。多數個資 料配線配置於基板上,其中掃描配線與資料配線係區分出200535774 V. Description of the invention (2) Switching element of the unit. In addition, in order to control individual daylight units, scanning lines (Sca η 1 ine) and data lines (Date 1 ine) are usually used to select specific daylight elements, and appropriate operating voltages are applied to display corresponding responses. Display information of this day element. In addition, the partial area of the above-mentioned day element electrode is usually covered on the scanning wiring or the common wiring (C 〇mm ο η 1 ine). The overlapping portion is used as a storage capacitor (C st) so that Each day element in a thin film transistor liquid crystal display can be displayed normally. It is worth noting that the above thin film transistor array substrate may face a line defect / defect, and the line defect problem is usually caused by a break in the wiring (scanning wiring or common wiring) on the substrate. . When the scanning wiring on the substrate is broken, the daylight electrode connected to the broken portion of the scanning wiring cannot be displayed, and the storage capacitor formed after the broken portion of the scanning wiring cannot be displayed normally, which may cause Scrap of thin film transistor array substrates. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a thin film transistor array substrate and a repair method thereof, which can be repaired for broken lines of a scanning wiring or a common wild wire, so as to avoid scrapping the thin film transistor array substrate. Based on the above objectives, the present invention proposes a thin film transistor array substrate, which is mainly composed of a substrate, multiple scanning wirings, multiple data wirings, multiple thin film transistors, multiple day electrodes, and a repair circuit. The plurality of scanning wirings are arranged on the substrate, and the plurality of scanning wirings include at least one defective scanning wiring, and the defective scanning wiring has a broken line. Most of the data wiring is arranged on the substrate, and the scanning wiring is distinguished from the data wiring.

13437twf.ptd 第8頁 200535774 五、發明說明(3) 多個晝素區域。每一個薄膜電晶體係位於對應之畫素區域 内,其中薄膜電晶體係藉由掃描配線以及資料配線驅動。 每一個畫素電極係位於對應之畫素區域内,以與對應之薄 膜電晶體電性連接,且每一個晝素電極之部分區域係位於 對應之掃描配線的上方,以構成一儲存電容。修補線路位 於斷線處上方,以與斷線處兩側之瑕疵掃描配線電性連 接,其中修補線路係與晝素電極電性絕緣。 基於上述目的,本發明提出一種薄膜電晶體陣列基 板,主要係由一基板、多個掃描配線、多個資料配線、多 個薄膜電晶體、多個畫素電極以及一修補線路所構成。多 個掃描配線配置於基板上,且多個掃描配線中包括至少一 瑕疵掃描配線,此瑕疵掃描配線具有一斷線處。多數個資 料配線配置於基板上,其中掃描配線與資料配線係區分出 多個晝素區域。每一個薄膜電晶體係位於對應之畫素區域 内,其中薄膜電晶體係藉由掃描配線以及資料配線驅動。 每一個畫素電極係位於對應之晝素區域内,以與對應之薄 膜電晶體電性連接,且每一個晝素電極之部分區域係位於 對應之掃描配線的上方,以構成一儲存電容。修補線路位 於斷線處上方,其中修補線路與至少一晝素電極係同時與 斷線處兩側之瑕疵掃描配線電性連接。 基於上述目的,本發明提出一種薄膜電晶體陣列基 板,主要係由一基板、多個掃描配線、多個資料配線、多 個薄膜電晶體以及多個晝素電極所構成。多個掃描配線配 置於基板上,且多個掃描配線中包括至少一瑕庇掃描配13437twf.ptd Page 8 200535774 V. Description of the invention (3) Multiple daylight regions. Each thin film transistor system is located in a corresponding pixel region, and the thin film transistor system is driven by scanning wiring and data wiring. Each pixel electrode is located in a corresponding pixel region to be electrically connected to a corresponding thin film transistor, and a portion of each day electrode is located above a corresponding scanning wiring to form a storage capacitor. The repairing line is located above the broken line to be electrically connected to the defective scanning wiring on both sides of the broken line. The repairing line is electrically insulated from the day electrode. Based on the above object, the present invention proposes a thin film transistor array substrate, which is mainly composed of a substrate, multiple scanning wirings, multiple data wirings, multiple thin film transistors, pixel electrodes, and a repair circuit. The plurality of scanning wirings are disposed on the substrate, and the plurality of scanning wirings include at least one defective scanning wiring, and the defective scanning wiring has a broken line. Most of the data wirings are arranged on the substrate, and the scanning wirings and the data wirings distinguish a plurality of daylight regions. Each thin film transistor system is located in a corresponding pixel region, and the thin film transistor system is driven by scanning wiring and data wiring. Each pixel electrode is located in the corresponding daylight region to be electrically connected to the corresponding thin film transistor, and a part of each daylight electrode is located above the corresponding scanning wiring to form a storage capacitor. The repair line is located above the broken line, and the repair line and at least one day electrode system are electrically connected to the defective scanning wiring on both sides of the broken line at the same time. Based on the above object, the present invention proposes a thin film transistor array substrate, which is mainly composed of a substrate, multiple scanning wirings, multiple data wirings, multiple thin film transistors, and multiple day electrodes. A plurality of scanning wirings are arranged on the substrate, and the plurality of scanning wirings include at least one defective scanning wiring.

13437twf.ptd 第9頁 200535774 五、發明說明(4) 線,此瑕疵 於基板上, 域。每一個 膜電 電極 性連 配線 與斷 板, 個薄 線路 配線 數個内, 每一 膜電 晶體係 係位於 接,且 的上方 線處兩 基於上 主要係 膜電晶 所構成 配置於 畫素區 其中薄 個畫素 晶體電 一個畫素電 以構成一儲 用酉己 線處 中修 板 線,此 上方, 補線路 基於上 主要係 掃描 其中 薄膜 藉由 對應 每一 ,以 側之 述目 由一 體、 。多 基板 域。 膜電 電極 性連 極之 存電 瑕/疵 以與 係與 述目 由一 配線 掃描 電晶 掃描 之晝 個畫 構成 瑕/疵的, 基板 多個 數個上, 每一 晶體 係位 接。 部分 容, 共用 斷線 晝素的, 基板 具有一 配線與 體係位 配線以 素區域 素電極 一儲存 掃描配 本發明 、多個 晝素電 掃描配 其中掃 個薄膜 係藉由 於對應 多數個 區域係 且該些 配線具 處兩側 電極電 本發明 、多個 斷線處。 資料配線 於對應之 及資料配 内,以與 之部分區 電容。其 線電性連 提出一種 掃描配線 極、多個 線配置於 描配線與 電晶體係 掃描配線 之晝素區 共用配線 位於對應 共用配線 有一斷線 之瑕疵共 性絕緣。 提出一種 掃描配線 多數個資料 係區分出多 畫素區域内 線驅動。每 對應之薄膜 域係位於對 中至少一晝 薄膜電晶體 、多個資料 共用配線以 基板上。多 資料配線係 位於對應之 以及資料配 域内,以與 配置於基板 之共用配線 中包括至少 處。修補線 用配線電性 配線 個畫 ,其 一個 電晶 應之 素電 陣列 配線 及一 數個 區分 晝素 線驅 對應 上, 的上 一瑕 路位 連接 配置 素區 中薄 晝素 體電 掃描 極係 基 、多 修補 資料 出多 區域 動。 之薄 且每 方, 巍共 於斷 ,其 薄膜電晶體陣列 、多個資料配線 基 多13437twf.ptd Page 9 200535774 V. Description of the invention (4) This defect is on the substrate and the field. Each membrane electrode is electrically connected to the wiring board and a plurality of thin circuit wires. Each membrane transistor system is connected, and the upper line is based on the main membrane transistor. It is arranged in the pixel area. A thin pixel crystal is used to form a pixel circuit to form a middle repair line at a storage line. Above this, the supplementary circuit is mainly based on scanning the thin film by corresponding to each, and one by one. Multiple substrate domains. Membrane electrical electrodes The polarity of the electrode storage defects / defects are related to the description by a wiring scanning transistor scanning day paintings to form defects / defects, a plurality of substrates, each crystal is connected. Partially-capacitive, common substrates have a wiring and system-level wiring. The prime region is a prime electrode. A storage scan system is provided with the present invention. These wiring harnesses are provided with electrodes on both sides of the present invention, and a plurality of disconnected places. The data wiring is in the corresponding and data distribution, and part of the capacitance. The line electrical connection proposes a scanning wiring electrode, and a plurality of lines are arranged in the scanning wiring and the transistor system. The scanning wiring common area is located in the corresponding common wiring and has a broken common defect insulation. This paper proposes a scanning wiring method that distinguishes multiple lines in a multi-pixel area from line driving. Each corresponding thin-film domain is located at least one day in the center of the thin-film transistor, and multiple materials share wiring on the substrate. The multiple data wiring system is located in the corresponding and data distribution domains, and includes at least parts of the common wiring arranged on the substrate. The electrical wiring for the repair line is a picture of an element array array of a transistor and a number of daylight line drivers. The last defect position is connected to the thin daylight body scanning electrode in the prime area. Department of base, multi-repaired data and multi-regional movement. It is thin and thin on each side, and its thin-film transistor array and multiple data wiring

13437twf.ptd 第10頁 200535774 五、發明說明(5) 個薄膜電晶體、多個晝素電極、多個共用配線以及一修補 線路所構成。多數個掃描配線配置於基板上。多數個資料 配線配置於基板上,其中掃描配線與資料配線係區分出多 數個晝素區域。每一個薄膜電晶體係位於對應之晝素區域 内,其中薄膜電晶體係藉由掃描配線以及資料配線驅動。 每一個畫素電極係位於對應之晝素區域内,以與對應之薄 膜電晶體電性連接。多數個共用配線配置於基板上,且每 一個晝素電極之部分區域係位於對應之共用配線的上方, 以構成一儲存電容,且該些共用配線中包括至少一瑕疵共 用配線,此瑕疵共用配線具有一斷線處。其中修補線路與 至少一晝素電極係同時與斷線處兩側之瑕疵共用配線電性 連接。 基於上述目的,本發明提出一種薄膜電晶體陣列基 板,主要係由一基板、多個掃描配線、多個資料配線、多 個薄膜電晶體、多個畫素電極以及多個共用配線所構成。 多數個掃描配線配置於基板上。多數個資料配線配置於基 板上,其中掃描配線與資料配線係區分出多數個晝素區 域。每一個薄膜電晶體係位於對應之畫素區域内,其中薄 膜電晶體係藉由掃描配線以及資料配線驅動。每一個畫素 電極係位於對應之晝素區域内,以與對應之薄膜電晶體電 性連接。多數個共用配線配置於基板上,且每一個晝素電 極之部分區域係位於對應之共用配線的上方,以構成一儲 存電容,且該些共用配線中包括至少一瑕疵共用配線,此 瑕疵共用配線具有一斷線處。其中至少一晝素電極係與斷13437twf.ptd Page 10 200535774 V. Description of the invention (5) Thin film transistor, multiple day electrode, multiple common wiring and a repair circuit. A plurality of scan wirings are arranged on the substrate. Most of the data wirings are arranged on a substrate, and the scanning wirings and the data wirings distinguish a plurality of daylight regions. Each thin film transistor system is located in a corresponding daylight region. The thin film transistor system is driven by scanning wiring and data wiring. Each pixel electrode is located in a corresponding daylight region to be electrically connected to a corresponding thin film transistor. A plurality of common wirings are arranged on the substrate, and a part of each day element electrode is located above the corresponding common wirings to form a storage capacitor, and the common wirings include at least one defective common wiring. The defective common wiring Has a broken line. The repair circuit and the at least one element electrode are electrically connected to the defect common wiring on both sides of the disconnection at the same time. Based on the above objectives, the present invention proposes a thin film transistor array substrate, which is mainly composed of a substrate, multiple scanning wirings, multiple data wirings, multiple thin film transistors, multiple pixel electrodes, and multiple common wirings. A plurality of scan wirings are arranged on the substrate. Most of the data wirings are arranged on the substrate, and the scanning wirings and the data wirings are used to distinguish most of the daylight regions. Each thin film transistor system is located in a corresponding pixel region, and the thin film transistor system is driven by scanning wiring and data wiring. Each pixel electrode is located in a corresponding daylight region to be electrically connected to a corresponding thin film transistor. A plurality of common wirings are arranged on the substrate, and a part of each day element electrode is located above the corresponding common wirings to constitute a storage capacitor, and the common wirings include at least one defective common wiring. Has a broken line. Among them, at least one day electrode is disconnected

13437twf.ptd 第11頁 200535774 五、發明說明(6) 線處兩側之瑕疵共用配線電性連接。 基於上述目的,本發明提出一種薄膜電晶體陣列基板 的修補方法,適於對一儲存電容在閘極上(C s t 0 n G a t e ) 或儲存電容在共用配線上(Cst On Common line)之薄 膜電晶體陣列基板進行修補,此修補方法係先移除鄰近於 一掃描配線或一共用配線之斷線處之至少一晝素電極的部 份區域;接著形成一修補線路位於斷線處上方,並與斷線 處兩側之掃描配線或共用配線電性連接,且修補線路係與 畫素電極電性絕緣。 基於上述目的,本發明提出一種薄膜電晶體陣列基板 的修補方法,適於對一儲存電容在閘極上或儲存電容在共 用配線上之薄膜電晶體陣列基板進行修補,此修補方法為 移除鄰近於一掃描配線或一共用配線之斷線處之至少一畫 素電極的部份區域,以使部分晝素電極與斷線處兩側之掃 描配線或共用配線電性連接。 基於上述目的,本發明提出一種薄膜電晶體陣列基板 的修補方法,適於對一儲存電容在閘極上或儲存電容在共 用配線上之薄膜電晶體陣列基板進行修補,此修補方法為 將鄰近於一掃描配線或一共用配線之斷線處之至少一晝素 電極與斷線處兩側之掃描配線或共用配線電性連接。 本發明主要是當薄膜電晶體陣列基板上之掃描配線或 共用配線發生斷線時,藉由形成一修補線路,並將此修補 線路與斷線處兩側之掃描配線或共用配線電性連接,以達 到修補此瑕疵掃描配線或瑕疵共用配線的目的。此外,亦13437twf.ptd Page 11 200535774 V. Description of the Invention (6) Defects on both sides of the wire share the electrical connection of the wiring. Based on the above objectives, the present invention provides a method for repairing a thin film transistor array substrate, which is suitable for a thin film capacitor having a storage capacitor on a gate (C st 0 n Gate) or a storage capacitor on a common wiring (Cst On Common line). The crystal array substrate is repaired. This repair method first removes a part of at least one day electrode adjacent to the disconnection of a scanning wiring or a common wiring; then, a repair circuit is formed above the disconnection, and The scanning wiring or common wiring on both sides of the disconnection is electrically connected, and the repairing circuit is electrically insulated from the pixel electrode. Based on the above objectives, the present invention provides a method for repairing a thin film transistor array substrate, which is suitable for repairing a thin film transistor array substrate having a storage capacitor on a gate electrode or a storage capacitor on a common wiring. A partial area of at least one pixel electrode of a scanning wiring or a common wiring, so that a part of the day electrode is electrically connected to the scanning wiring or the common wiring on both sides of the broken wiring. Based on the above objectives, the present invention provides a method for repairing a thin film transistor array substrate, which is suitable for repairing a thin film transistor array substrate with a storage capacitor on a gate or a storage capacitor on a common wiring. At least one day electrode at the break of the scanning wiring or a common wiring is electrically connected to the scanning wiring or the common wiring on both sides of the breaking wiring. The present invention mainly forms a repair line when the scanning wiring or the common wiring on the thin film transistor array substrate is disconnected, and electrically connects this repairing circuit to the scanning wiring or the common wiring on both sides of the disconnection. To achieve the purpose of repairing the defective scanning wiring or the defective common wiring. In addition, also

13437twf.ptd 第12頁 200535774 五、發明說明(7) 可將位於斷線處上方之晝素電極直接與斷線處兩側之掃描 配線或共用配線電性連接,以同樣達到修補此瑕疵掃描配 線或瑕疵共用配線的目的。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂,下文特舉數個較佳實施例,並配合所附圖式,作詳 細說明如下。 實施方式 圖1繪示為依照一種儲存電容在閘極上之薄膜電晶體 陣列基板的結構示意圖。請參照圖1 ,薄膜電晶體陣列基 板主要係由一基板1 0 0、多個掃描配線1 1 0、多個資料配線 1 2 0、多個薄膜電晶體1 3 0以及多個晝素電極1 4 0所構成。 多個掃描配線1 1 0與多個資料配線1 2 0配置於基板1 0 0 上,且這些掃描配線1 1 0與這些資料配線1 2 0係區分出多個 畫素區域1 2 2。每一個薄膜電晶體1 3 0係位於對應之晝素區 域1 2 2内,且薄膜電晶體1 3 0係藉由掃描配線1 1 0以及資料 配線1 2 0驅動。每一個畫素電極1 4 0係位於對應之畫素區域 1 2 2内,以與對應之薄膜電晶體1 3 0電性連接。此外,每一 個晝素電極1 4 0之部分區域位於對應之掃描配線1 1 0的上 方,以構成一儲存電容。承上述,儲存電容係由掃描配線 1 1 0與其上之晝素電極1 4 0相互耦合而構成,掃描配線1 1 0 與晝素電極1 4 0之間通常會以一介電層(閘極絕緣層及/或 保護層)相隔。 值得注意的是,因製程的瑕疵或其他因素,掃描配線 1 1 0中很有可能會出現至少一條之瑕疵掃描配線1 1 0 a,瑕13437twf.ptd Page 12 200535774 V. Description of the invention (7) The daylight electrode above the disconnection can be directly connected to the scanning wiring or common wiring on both sides of the disconnection, so as to repair the defective scanning wiring. Or the purpose of the defective common wiring. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, several preferred embodiments are exemplified below, and described in detail with the accompanying drawings. Embodiment FIG. 1 is a schematic structural diagram of a thin film transistor array substrate with a storage capacitor on a gate. Please refer to FIG. 1, the thin film transistor array substrate is mainly composed of a substrate 100, a plurality of scanning wirings 1 10, a plurality of data wirings 1 2 0, a plurality of thin film transistors 1 3 0, and a plurality of day electrode 1 4 0. A plurality of scanning wirings 1 10 and a plurality of data wirings 1 2 0 are arranged on the substrate 100, and the scanning wirings 1 10 and the data wirings 1 2 0 distinguish a plurality of pixel regions 1 2 2. Each thin film transistor 130 is located in the corresponding daylight region 1 22, and the thin film transistor 130 is driven by the scanning wiring 1 10 and the data wiring 120. Each pixel electrode 140 is located in a corresponding pixel region 1 2 2 to be electrically connected to a corresponding thin film transistor 130. In addition, a partial area of each day element electrode 140 is located above the corresponding scanning wiring 110 to form a storage capacitor. In accordance with the above, the storage capacitor is formed by coupling the scanning wiring 1 1 0 with the day element electrode 1 40 thereon. The scanning line 1 1 0 and the day element electrode 1 4 0 are usually separated by a dielectric layer (gate Insulation and / or protective layer). It is worth noting that, due to process defects or other factors, at least one defect in scanning wiring 1 1 0 is likely to occur. Scanning wiring 1 1 0 a, defective

13437twf.ptd 第13頁 20053577413437twf.ptd Page 13 200535774

五、發明說明(8) 疫掃描配線1 1 〇 a具有至 具有瑕疵掃描配線丨丨〇a時,疵,而當掃描配線1 10中 所連接的畫素電極140將益法正1 \描配線之斷線處後 下文中將針對瑕疵掃描配線11〇a/不。因此,本發明於 料配線12〇之間或位於任一條 %處A位於任二條資 補“掃描配線,之修補、二二 掃描補示月之修補方法將圖1中的# 方法例如係先將斷線處A上方之;:J :二描配線二〇 Ξ中其=方法例如是以雷射-移== 口 142,m晝素電極140的部分區域移除以形成一開 路150例如以+ ^開口 l42中形成一修補線路150。修補線 屮 运射化學氣相沈積(L a s e r C V D )的方式形 i的上述之修補線路150例如係以雷射炼 、,”,線處Α兩側之瑕疵掃描配線1 1 〇 a電性連接。 位热ϊ ϊ,ί參照圖2B,當瑕庇掃描配線1 1 0a之斷線處A 11〇!二1: 料配線120的下方時,修補瑕庇掃描配線 部八,Ϊ ΐ ί係先將與斷線處A相鄰之兩畫素電極14〇的 ^ ί /移除㈤方法例如係、以雷射移㈣方式進 以分別$:? ,例如係將兩畫素電極14 〇的邊緣處移除 刀別形成一缺口144。接著,形成一修補線路丨50於缺口V. Description of the invention (8) When the scanning wiring 1 1 〇a has a defective scanning wiring 丨 丨 a, the pixel electrode 140 connected to the scanning wiring 1 10 will be positive and accurate. After the disconnection, the wiring will be scanned 11a / no for defects. Therefore, the present invention is located between 120% of the material wiring or at any%. A is located at any of the two supplementary "scanning wiring, repairing, and second and second scanning supplementary repair methods. The # method in Fig. 1 is, for example, Above the broken line A :: J: In the second trace wiring 20 二, its = method is, for example, laser-shift == mouth 142, a part of the m-day element electrode 140 is removed to form an open circuit 150, for example, + ^ A repairing line 150 is formed in the opening l42. The repairing line 150 is formed by laser vapor deposition (Laser CVD). The repairing line 150 described above is formed by laser, for example. The defective scanning wiring 1 1 〇a is electrically connected. Bit hot ϊ ί, 参照 Referring to FIG. 2B, when the broken scanning wiring 1 1 0a breaks A 11〇! 2: 1: under the wiring 120, repair the defective scanning wiring section 8, Ϊ ΐ ί The method of removing / removing the two pixel electrodes 14 o adjacent to the broken line A is, for example, a laser shifting method to separate $:?, For example, the edge of the two pixel electrodes 14 o The knife is removed to form a gap 144. Next, a repair line is formed 50 in the gap

200535774 五、發明說明(9) 144内以跨過資料配線120,其中修補線路15〇例如係以雷 射化學氣相沈積的方式形成。值得注意的是,上述之修補 線路1 50例如係以雷射熔接的方式與斷線處a兩側之瑕疵掃 描配線1 1 0 a電性連接。200535774 V. Description of the invention (9) 144 is to cross the data wiring 120, and the repairing circuit 15 is formed by, for example, laser chemical vapor deposition. It is worth noting that the repair line 150 mentioned above is electrically connected to the defect scanning lines 1 1 0 a on both sides of the broken line a by, for example, laser welding.

承上所述,由圖2A〜2B中所揭露之修補方式可知,因 修補線路15〇與經過雷射處理之晝素電極14〇係彼此電性絕 緣,所^經雷射修補後之畫素電極14〇仍能夠正常顯示。 接著,a月參照圖2 C,當瑕疵掃描配線】i &之斷線處A 穴,ΐ中一條資料ί線12 〇的下方時,修補瑕庇掃描配線 110a的方法例如係先將與斷線處a相鄰之兩晝素電極14〇分 割為一顯示部分140a及一修補部分u〇b,以 HOa與修補部分14〇b電性絕緣。本實施 極14〇的方式例如係以雷射移除的方式。接著,形成一一修 補線路150於斷線處A上方,以使得修補 性連接。值仟注思的疋,修補線路15〇例如係以雷射熔接 的方式同時與斷線處Α兩側之瑕疵共用配 部分1 4 0 b電性連接。 〇 β以及仏補 接著,請參照圖2 D,當瑕疵掃描配線 位於任二條資料配線1 20之間時,修補 Ua之斷線處八 的方法例如係先將斷線處A上方之畫素描^配線11“ 示部分1 4 0 a及一被顯示部分1 4 0 a環繞之修°、 0分割為一顯 使顯示部分1 4 0 a與修補部分1 4 0 b電性絕^彳。部分1 4 0 b ’此 分割晝素電極1 40的方式例如係以雷射蒋本實施例中’ 陈的方式。接As mentioned above, it can be known from the repairing methods disclosed in FIGS. 2A to 2B that the repaired circuit 15 and the laser-treated day electrode 14 14 are electrically insulated from each other, so the pixels after laser repair The electrode 14o can still display normally. Next, referring to FIG. 2C in a month, when the defect scanning wiring] i & breaks the hole A, below one of the data ίline 120, the method of repairing the defective scanning wiring 110a is to first disconnect the The two element electrodes 14a adjacent to the line a are divided into a display portion 140a and a repair portion u0b, and HOa is electrically insulated from the repair portion 14b. The method of the present embodiment is, for example, a laser removal method. Next, a one-to-one repair line 150 is formed above the broken line A to make a repair connection. It is worth noting that the repairing circuit 15 is electrically connected to the defect sharing part 14 on both sides of the line A at the same time by means of laser welding, for example. 〇β and fill in the next, please refer to Figure 2D, when the defective scanning wiring is located between any two data wiring 120, the method of repairing the broken line eight of Ua is, for example, first drawing a sketch above the broken line A ^ Wiring 11 "Display part 1 4 0 a and a display part 1 4 0 a surround the repair °, 0 is divided into a display so that the display part 1 4 0 a and the repair part 1 4 0 b are electrically isolated. Part 1 4 0 b 'The method of dividing the day element electrode 1 40 is, for example, the method of Chen in this embodiment.

13437twf.ptd 第15頁 200535774 發明說明(10) 著,再將修補部*140b與斷線處A兩側 noa電性連接。本實施例中,修補部分14心二〜配線 側之瑕疲掃描配線11〇a的電性連接 雷兩 式達成 所述,由圖2C及圖2D中所揭露 承—’ 〜 一 ^ 一一 θ。以τ尸坏揭露之修 藉由將鄰近於斷線處Α之晝素電極丨4〇 万式了知 兩側之瑕疵掃描配線110a電性連接,即可達修補 值得注意的是,由於畫素電極丨40之顯示部分14〇a盘修補 部分140b係彼此電性絕緣,故晝素電極14〇之顯示部分 1 4 0 a仍能夠正常顯示,不會受到修補製程的影響。 接著,,參照圖2 E,當瑕疵掃描配線丨丨〇 a之斷線處a 位於任兩條貢料配線1 2 0之間時,修補瑕疵掃描配線丨丨〇 a 的方法例如係以雷射溶接的方式直接將斷線處A上方之晝 素電極1 4 0與斷線處A兩側之瑕疵掃描配線丨丨〇 a電性連接t 此情況下,由於瑕疵掃描配線丨1〇a係藉由斷線處A上方的 晝素電極1 4 0而達到修補的目的,因此可將原本的線瑕疵 (line defect)改善為早點瑕疫(〇ne defect) 接著’請參照圖2 F,當瑕疲掃描配線1 1 〇 a之斷線處A 位於其中一條資料配線1 2 〇的下方時,修補瑕藏掃描配線 1 1 0 a的方法例如係在斷線處a的上方形成一修補線路1 5 0 c 本實施例中修補線路1 5 〇例如係以雷射化學氣相沈積的方 式形成。值得注意的是,修補線路丨5 〇例如係以雷射熔接 的方式同時與斷線處A兩側之瑕疵共用配線1 1 〇 a以及位於13437twf.ptd Page 15 200535774 Description of the invention (10), then the repair part * 140b is electrically connected to the noa on both sides of the disconnection A. In this embodiment, the repair of the part 14 and the wiring on the side of the wiring side scan the electrical connection of the wiring 110a, as described above, as disclosed in FIG. 2C and FIG. 2D— '~~ ^^ . The repair of τ corpse exposure is performed by electrically connecting the celestial electrode adjacent to the broken line A with the 400,000-type defect scanning wiring 110a on both sides, which can be repaired. It is worth noting that due to the pixels The display portion 140a and the disk repair portion 140b of the electrode 丨 40 are electrically insulated from each other, so the display portion 140a of the day element electrode 140 can still display normally without being affected by the repair process. Next, referring to FIG. 2E, when the broken line a of the defective scanning wiring 丨 丨 a is located between any two of the material wirings 120, the method of repairing the defective scanning wiring 丨 〇a is, for example, laser. The welding method directly connects the daytime electrode 1 40 above the broken line A with the defective scanning wiring on both sides of the broken line 丨 丨 a. In this case, because the defective scanning wiring 丨 10a is borrowed The repair is achieved by the day element electrode 1 40 above the broken line A. Therefore, the original line defect can be improved to an early defect. Then, please refer to FIG. 2F. When the defect When the broken line A of the scan line 1 1 〇a is located below one of the data lines 1 2 0, the method of repairing the defective scan line 1 1 0 a is to form a repair line 1 5 above the broken line a 0 c The repairing circuit 150 in this embodiment is formed by, for example, a laser chemical vapor deposition method. It is worth noting that the repair line 丨 5 〇, for example, by laser welding at the same time with the flaws on both sides of the broken line A 1 1 〇 a and located at

13437twf.ptd 第16頁 200535774 五、發明說明(11) 斷線處A兩側之晝素電極1 4 0電性連接。 承上所述,由圖2 E及圖2 F中所揭露之修補方式可知, 藉由直接以晝素電極1 4 0與斷線處A兩側之瑕疵掃描配線 1 1 0 a電性連接的方式同樣可達到修補線瑕疵之目的。 · 承上所述,上述之實施例皆針對瑕疵掃描配線的斷 _ 線處進行修補予以詳細之說明,任何熟悉該項技藝者應 知,本發明之修補方法並不侷限於修補瑕疵掃描配線,亦 可針對配置於薄膜電晶體陣列基板上之瑕疵共用配線 (defect common line)進行修補。由於共用配線通常係 設計在每兩條相鄰之掃描配線之間,而晝素電極之局部區 域會覆蓋住共用配線以形成共用配線上儲存電容結構(C s t _ on common ),因此當共用配線中之瑕巍共用配線發生斷線 時,同樣會有線瑕疵的問題產生。據此,本發明提出另外 一種修補方法,以針對瑕疵共用配線進行修補。 圖3 A〜3 F,繪示為以本發明之修補方法針對瑕疵共用 配線進行修補的示意圖。其中圖3 A〜3 F中之薄膜電晶體陣 列基板為儲存電容在共用配線上(Cst on Common line) 之薄膜電晶體陣列基板,其主要結構與圖2 A〜2F相同,故 僅針對技術相異點進行詳細之說明如下。 在共用配線上儲存電容(Cst on common)的架構中, 基板1 0 0上除了配置有多條掃描配線1 1 0之外,任兩條相鄰 · 之掃描配線1 1 0之間尚配置有共用配線1 6 0。每一個畫素中 的儲存電容係由晝素電極140的部分區域與其上方之共用 配線1 6 0所構成。同樣地,共用配線1 6 0與晝素電極1 4 0之13437twf.ptd Page 16 200535774 V. Description of the invention (11) The celestial electrodes 14 on both sides of the broken line are electrically connected. As mentioned above, from the repair methods disclosed in Fig. 2E and Fig. 2F, it can be known that by directly scanning the wiring 1 1 0 a with defects on both sides of the broken line A 1 on the day electrode 1 4 0 The method can also achieve the purpose of repairing line defects. · As mentioned above, the above-mentioned embodiments all describe repairing broken lines of defective scanning wiring in detail. Anyone familiar with the art should know that the repair method of the present invention is not limited to repairing defective scanning wiring. Defect common lines disposed on the thin film transistor array substrate may also be repaired. Because the common wiring is usually designed between every two adjacent scanning wirings, and the local area of the day element electrode will cover the common wiring to form a storage capacitor structure (C st _ on common) on the common wiring, so when the common wiring In the case of disconnection of the Zhongweiwei common wiring, there will also be problems of wire defects. Based on this, the present invention proposes another repair method for repairing defective common wiring. Figures 3A to 3F are schematic diagrams showing the repair of defective common wiring by the repair method of the present invention. Among them, the thin-film transistor array substrate in FIGS. 3A to 3F is a thin-film transistor array substrate with storage capacitors on a common line (Cst on Common line). Its main structure is the same as that in FIGS. 2A to 2F, so it is only for the technical phase. The differences are explained in detail below. In the architecture of storage capacitors on the common wiring (Cst on common), in addition to a plurality of scanning wirings 1 1 0 arranged on the substrate 100, there are two scanning wirings 1 1 0 adjacent to each other. Common wiring 1 6 0. The storage capacitor in each pixel is composed of a partial area of the day electrode 140 and the common wiring 160 above it. Similarly, between the common wiring 16 0 and the day electrode 1 40

13437twf.ptd 第17頁 200535774 五、發明說明(12) 間通常會以一介電声(閱士 不可避免的,共用^線丨6 〇°絕緣層及/或保護層)相隔。 疵共用配線160a,而瑕疵共义有可能會出現至少一條之瑕 請參照圖3 A,當瑕疲& 配線1 6 〇 a具有一斷線處B。 兩條資料配線1 2 0之間時,/、其用灰配線1 6 0 a之斷線處B位於任 處B上方之畫素電極"Ο的部^八> 補、之方法例如係先將斷線 1 4 2,接著再於開口丨4 2中形二^域移除,以形成一開口 補線路150與斷線處b兩側^瑕;一修補線路150,以使得修 進而達到修補瑕龜共用配線1 6 共用配線1 6 0 a電性連接, 請參照圖3B,本發明亦可a =目的。 極1 4 0的部分區域移除,以分 將斷線^處B上方之晝素電 示區1 4 0 a電性絕緣之修補區^ 4°〇出一顯示區1 4 0 a及一與顯 斷線處B兩側之瑕疵共用配線16〇a’接著再將修補區140b與 請參照圖3C,本發明亦可將斷., 14 0直接藉由雷射熔接的方式與斷線$ 方之畫素電極 線160a電性連接。 所線處B兩側之瑕疵共用配 接著請參照圖3D,當瑕疵共用配線丨 於其中一條資料配線120下方時,1修福令a之斷線處B位 移牙、斷線處Β所相W之兩畫素電極丨4 〇的部, 畫素電極140的邊緣處分別形成一缺口 ° ; 跨過資料配線1 20之修補線路15 〇、,、接著再形成一 佈於缺口 144内,同時修補線路15〇 &盥線路15〇係分 庇共用配線16〇a電性連接。ϋ係與斷線處B兩側之瑕 請參照圖3Ε,本發明亦可先移除斷線處β所相鄰之兩13437twf.ptd Page 17 200535774 V. Description of the invention (12) Usually a dielectric sound is used (reader is unavoidable, shared ^ wire 丨 60 ° insulation layer and / or protective layer). Defect common wiring 160a, and at least one defect may appear in the defect common sense. Please refer to FIG. 3A, when the defect & wiring 16a has a broken line B. When the two data wirings 1 2 0, /, the gray wire 1 6 0 a of the broken line B is located above any of the pixel electrodes " 〇 的 部 ^ 八 > Remove the broken line 1 4 2 first, and then remove the middle area 2 in the opening 丨 2 2 to form an opening to repair the line 150 and the two sides of the broken line ^ defect; repair the line 150 so that the repair can reach The common wiring for repairing the tortoise 1 6 is connected to the common wiring 16 0 a electrically. Please refer to FIG. 3B. The partial area of the pole 1 40 is removed to divide the daylight electrical display area 1 4 0 a above the B line. The electrical insulation repair area ^ 4 ° 〇 a display area 1 4 0 a and a Defective common wiring 16a 'on both sides of the broken line B, and then the repair area 140b and please refer to FIG. 3C, the present invention can also be broken., 14 0 is directly connected to the broken line by laser welding. The pixel electrode lines 160a are electrically connected. Defective common distribution on both sides of line B. Please refer to FIG. 3D. When the defective common wiring 丨 is under one of the data wiring 120, the broken line B of 1 repair order a is displaced, and the broken line B is related to W In the two pixel electrodes 丨 4 〇, a gap is formed at the edge of the pixel electrode 140 respectively; a repair line 15 across the data wiring 120 is formed, and then a cloth is formed in the gap 144 and repaired at the same time Line 15 & bathroom line 150 is electrically connected to the sheltered common wiring 16a. The defect is on the two sides of the broken line B. Please refer to FIG. 3E. In the present invention, the two adjacent lines of the broken line β can also be removed first.

13437twf.ptd 第18頁 200535774 五、發明說明(13) 晝素電極1 4 0的部分區域,以分割出一顯示區1 4 0 a及與一 顯示區1 4 0 a電性絕緣之修補區1 4 0 b,接著再形成一跨過資 料配線1 2 0之修補線路1 5 0,同時將修補線路1 5 0及修補區 1 4 0 b與斷線處B兩側之瑕疵共用配線1 6 0 a電性連接。 請參照圖3 F,本發明亦可直接形成一跨過資料配線 1 2 0之修補線路1 5 0,並藉由雷射熔接的方式將修補線路 1 5 0與斷線處B兩側之瑕疵共用配線1 6 0 a電性連接。 綜上所述,本發明之修補方法主要具有下列優點: 1 .本發明之修補方法可輕易的地將掃描配線或是共用 配線斷線所導致的線瑕疵修補,實用性高。 2 ·本發明之修補方法可將線瑕疵修補為二點瑕疵(two _ defects)、單點瑕疵(one defect),甚至無瑕藏(zero defect),以大幅增進良率。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此技藝者,在不脫離本發明之精神 和範圍内,當可作些許之更動與潤飾,因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。13437twf.ptd Page 18 200535774 V. Description of the invention (13) Partial area of day element electrode 1 40 to divide a display area 1 4 0 a and a repair area 1 electrically insulated from a display area 1 4 0 a 4 0 b, and then form a repair line 15 0 across the data wiring 1 2 0, and at the same time, repair the repair line 15 and repair area 1 4 0 b and the defect on both sides of the broken line B 1 6 0 a Electrical connection. Please refer to FIG. 3F, the present invention can also directly form a repair line 150 that crosses the data wiring 120, and repair the defects on both sides of the repair line 150 and the broken line B by laser welding. The common wiring is electrically connected. In summary, the repair method of the present invention mainly has the following advantages: 1. The repair method of the present invention can easily repair line defects caused by disconnection of scanning wiring or common wiring, and has high practicability. 2 · The repair method of the present invention can repair line defects into two defects, one defect, or even zero defect, so as to greatly improve the yield. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

13437twf.ptd 第19頁 200535774 圖式簡單說明 圖1繪示為依照一種儲存電容在閘極上之薄膜電晶體 陣列基板的結構不意圖。 圖2 A〜2 F繪示為以本發明之修補方法將圖1中的瑕疵 掃描配線進行修補的示意圖。 圖3 A〜3 F繪示為以本發明之修補方法針對瑕疵共用配 線進行修補的示意圖。 【圖式標示說明】 1 0 0 :基板13437twf.ptd Page 19 200535774 Brief Description of Drawings Figure 1 shows the structure of a thin film transistor array substrate with a storage capacitor on the gate, which is not intended. 2A to 2F are schematic diagrams of repairing the defective scanning wiring in FIG. 1 by the repair method of the present invention. 3A to 3F are schematic diagrams of repairing a defect common wiring by the repair method of the present invention. [Schematic description] 1 0 0: Substrate

1 10 1 10a 120 122 130 140 140a 140b 142 144 150 160 160a A ^ B 掃描配線 :瑕疵掃描配線 資料配線 晝素區域 薄膜電晶體 晝素電極 .顯不區 :修補區 開口 缺口 修補線路 共用配線 :瑕疵共用配線 斷線處1 10 1 10a 120 122 130 140 140a 140b 142 144 150 160 160a A ^ B Scanning Wiring: Defect Scanning Wiring Information Wiring Element Area Thin Film Transistor Electrode. Display Area: Repair Area Opening Gap Repair Line Common Wiring: Defect Common wiring break

13437twf.ptd 第20頁13437twf.ptd Page 20

Claims (1)

200535774 六、申請專利範圍 1 . 一種薄膜電晶體陣列基板,包括: 一基板; 多數個掃描配線,配置於該基板上,該些掃描配線中 包括至少一瑕疵掃描配線,該瑕疵掃描配線具有一斷線 · 處; . 多數個資料配線,配置於該基板上,其中該些掃描配 線與該些資料配線係區分出多數個晝素區域; 多數個薄膜電晶體,每一該些薄膜電晶體係位於該些 畫素區域其中之一内,其中該些薄膜電晶體係藉由該些掃 描配線以及該些資料配線驅動, 多數個晝素電極,每一該些畫素電極係位於該些畫素® 區域其中之一内,以與對應之該些薄膜電晶體其中之一電 性連接,且每一該些晝素電極之部分區域係位於對應之該 些掃描配線其中之一的上方,以構成一儲存電容;以及 一修補線路,位於該斷線處上方,以與該斷線處兩側 之該瑕疵掃描配線電性連接,其中該修補線路係與該些晝 素電極電性絕緣。 2. 如申請專利範圍第1項所述之薄膜電晶體陣列基 板,當該瑕疵掃描配線之該斷線處位於該些資料配線其中 之二之間時,該些晝素電極其中之一具有一與該斷線處對 應之開口,且該修補線路位於該開口中,以與該些晝素電 鲁 極其中之一電性絕緣。 3. 如申請專利範圍第1項所述之薄膜電晶體陣列基 板,當該瑕疵掃描配線之該斷線處位於該些資料配線其中200535774 VI. Scope of patent application 1. A thin film transistor array substrate comprising: a substrate; a plurality of scanning wirings arranged on the substrate, the scanning wirings including at least one defective scanning wiring, the defective scanning wiring having a break Lines;. A plurality of data wirings are arranged on the substrate, wherein the scanning wirings and the data wirings distinguish a plurality of daylight regions; a plurality of thin film transistors, each of which is located in a thin film transistor system. Within one of the pixel regions, where the thin film transistor systems are driven by the scanning wirings and the data wirings, a plurality of pixel electrodes, each of the pixel electrodes are located in the pixels® One of the regions is electrically connected to one of the corresponding thin film transistors, and a part of each of the celestial electrodes is located above one of the corresponding scanning wirings to form a A storage capacitor; and a repair line located above the disconnection to be electrically connected to the defective scanning wiring on both sides of the disconnection, wherein the repair The supplementary line is electrically insulated from the day electrodes. 2. According to the thin film transistor array substrate described in item 1 of the scope of the patent application, when the broken line of the defective scanning wiring is located between two of the data wirings, one of the daylight electrodes has a An opening corresponding to the broken line, and the repairing line is located in the opening, so as to be electrically insulated from one of the celestial electrodes. 3. According to the thin film transistor array substrate described in item 1 of the scope of patent application, when the broken line of the defective scanning wiring is located in the data wirings 13437twf.ptd 第21頁 200535774 六、申請專利範圍 之一的下方時,與該斷線處相鄰之二晝素電極的邊緣處具 有一缺口 ,其中該修補線路係跨過該些資料配線其中之 一,且分佈該些缺口内,以與該些晝素電極電性絕緣。 4. 一種薄膜電晶體陣列基板,包括: 一基板; 多數個掃描配線,配置於該基板上,該些掃描配線中 包括至少一瑕疵掃描配線,該瑕疵掃描配線具有一斷線 處, 多數個資料配線,配置於該基板上,其中該些掃描配 線與該些資料配線係區分出多數個晝素區域; 多數個薄膜電晶體,每一該些薄膜電晶體係位於該些 晝素區域其中之一内,其中該些薄膜電晶體係藉由該些掃 描配線以及該些資料配線驅動; 多數個畫素電極,每一該些晝素電極係位於該些晝素 區域其中之一内,以與對應之該些薄膜電晶體其中之一電 性連接,且每一該些晝素電極之部分區域係位於對應之該 些掃描配線其中之一的上方,以構成一儲存電容;以及 一修補線路,位於該斷線處上方,其中該修補線路與 該些晝素電極至少其中之一係同時與該斷線處兩側之該瑕 疵掃描配線電性連接。 5. 如申請專利範圍第4項所述之薄膜電晶體陣列基 板,當該瑕疵掃描配線之該斷線處位於該些資料配線其中 之一的下方時,與該瑕疵掃描配線之該斷線處相鄰之二畫 素電極分別包括:13437twf.ptd Page 21 200535774 VI. When one of the patent application scopes is below, there is a gap at the edge of the diurnal electrode adjacent to the broken line, where the repair line crosses one of the data wirings. One, and is distributed in the gaps to be electrically insulated from the day electrodes. 4. A thin-film transistor array substrate comprising: a substrate; a plurality of scanning wirings disposed on the substrate, the scanning wirings including at least one defective scanning wiring, the defective scanning wiring having a broken line, and most data Wiring is arranged on the substrate, wherein the scanning wirings and the data wirings distinguish a plurality of celestial regions; a plurality of thin film transistors, each of which is located in one of the celestial regions The thin film transistor system is driven by the scanning wirings and the data wirings; a plurality of pixel electrodes, each of which is located in one of the daylight regions to correspond to One of the thin film transistors is electrically connected, and a partial area of each of the daylight electrodes is located above one of the corresponding scanning wirings to form a storage capacitor; and a repair circuit is located at Above the disconnection, the repair line and at least one of the day electrodes are simultaneously electrically connected to the defective scanning wiring on both sides of the disconnection. connection. 5. According to the thin film transistor array substrate described in item 4 of the scope of patent application, when the broken line of the defective scanning wiring is located under one of the data wirings, the broken line of the defective scanning wiring The two adjacent pixel electrodes include: 13437twf.ptd 第22頁 200535774 六、申請專利範圍 一顯示部分;以及 一修補部分,與該顯示部分電性絕緣,其中該修補線 路以及該修補部分係同時與該斷線處兩側之該瑕疵掃描配 線電性連接。 6. —種薄膜電晶體陣列基板,包括: 一基板; 多數個掃描配線,配置於該基板上,該些掃描配線中 包括至少一瑕疵掃描配線,該瑕疵掃描配線具有一斷線 處, 多數個資料配線,配置於該基板上,其中該些掃描配 線與該些資料配線係區分出多數個晝素區域; 多數個薄膜電晶體,每一該些薄膜電晶體係位於該些 畫素區域其中之一内,其中該些薄膜電晶體係藉由該些掃 描配線以及該些資料配線驅動;以及 多數個晝素電極,每一該些畫素電極係位於該些畫素 區域其中之一内,以與對應之該些薄膜電晶體其中之一電 性連接,且每一該些畫素電極之部分區域係位於對應之該 些掃描配線其中之一的上方,以構成一儲存電容,其中該 些晝素電極至少其中之一係與該斷線處兩側之該瑕疵掃描 配線電性連接。 7. 如申請專利範圍第6項所述之薄膜電晶體陣列基 板,當該瑕疵掃描配線之該斷線處位於該些資料配線其中 之二之間時,該些晝素電極其中之一包括: 一顯示部分;以及13437twf.ptd Page 22 200535774 VI. Application scope: a display part; and a repair part, which is electrically insulated from the display part, wherein the repair line and the repair part are scanned simultaneously with the defects on both sides of the broken line Wiring is electrically connected. 6. A thin film transistor array substrate comprising: a substrate; a plurality of scanning wirings arranged on the substrate, the scanning wirings including at least one defective scanning wiring, the defective scanning wiring having a broken line, a plurality of The data wirings are arranged on the substrate, wherein the scanning wirings and the data wirings distinguish a plurality of daylight regions; a plurality of thin film transistors, each of which is located in one of the pixel regions. In one, the thin film transistor systems are driven by the scanning wirings and the data wirings; and a plurality of pixel electrodes, each of the pixel electrodes is located in one of the pixel regions to It is electrically connected to one of the corresponding thin film transistors, and a part of each of the pixel electrodes is located above one of the corresponding scanning wirings to form a storage capacitor. At least one of the element electrodes is electrically connected to the defective scanning wiring on both sides of the disconnection. 7. According to the thin film transistor array substrate described in item 6 of the scope of patent application, when the broken line of the defective scanning wiring is located between two of the data wirings, one of the daylight electrodes includes: A display section; and 13437twf.ptd 第23頁 200535774 六、申請專利範圍 路以及 線電性8. 板,當 部分,與該顯示部分電性絕緣,其中該修補線 補部分係同時與該斷線處兩側之該瑕疵掃描配 修補 該修 連接 如申 該瑕 下方 修補 該修 請專利範圍 疵掃描配線 時,更包括 線路,該修 補配線、該 線處兩側之該瑕疵掃描 薄膜電晶體 之一的 且 多 多 線與該 多 畫素區 描配線 多 區域其 性連接 多 電極之 方,以 藏共用 9 · 一種 一基板 數個 數個 些資 數個 域其 以及 數個 中之 掃描配線, 資料配線, 料配線係區 薄膜電晶體 中之一内, 該些資料配 畫素電極’ 内 以與 第6項所述之薄膜電晶體陣列基 之該斷線處位於該些資料配線其中 補線路係跨過該些資料配線其中之 斷線處相鄰之二晝素電極以及該斷 配線係彼此電性連接。 陣列基板,包括: 配置於該基板上; 配置於該基板上,其中該些掃描配 分出多數個晝素區域; ,每一該些薄膜電晶體係位於該些 其中該些薄膜電晶體係藉由該些掃 線驅動; 每一該些畫素電極係位於該些畫素 對應之該些薄膜電晶體其中之一電 數個共用配線,配置於該基板上,且每一該些畫素 部分區域係位於對應之該些共用配線其中之一的上 構成一儲存電容,且該些共用配線中包括至少一瑕 配線,該瑕疵共用配線具有一斷線處;以及13437twf.ptd Page 23 200535774 VI. Patent application scope Road and line electrical 8. Board, when part, is electrically insulated from the display part, where the repair line repair part is simultaneously with the defect on both sides of the broken line Scanning and repairing the repair connection. If the defect is repaired under the patent claim, the repair patent coverage defect includes wiring, the repairing wiring, one of the defect scanning film transistors on both sides of the line, and many lines and the Multi-pixel area drawing wiring, multi-area connection of multiple electrodes, to share 9 · a kind of a substrate, a number of fields, a number of fields, and a number of scanning wiring, data wiring, material wiring system film Within one of the transistors, the data distribution pixel electrodes' are located within the data wiring with the disconnection of the thin-film transistor array base described in item 6, and the supplementary wiring is across the data wiring. The adjacent two dielectrolyte electrodes at the broken line and the broken wiring are electrically connected to each other. An array substrate includes: disposed on the substrate; disposed on the substrate, wherein the scans allocate a plurality of daylight regions; and each of the thin film transistor systems is located in the thin film transistor systems by The scanning lines are driven; each of the pixel electrodes is located on one of the thin film transistors corresponding to the pixels, and a plurality of common wirings are arranged on the substrate, and each of the pixel partial areas A storage capacitor is formed on the corresponding one of the common wirings, and the common wirings include at least one defective wiring, the defective common wiring has a broken line; and 13437twf.ptd 第24頁 200535774 六、申請專利範圍 一修補線路,位於該斷線處上方,以與該斷線處兩側 之該瑕疵掃描配線電性連接,其中該修補線路係與該些畫 素電極電性絕緣。 1 0.如申請專利範圍第9項所述之薄膜電晶體陣列基 板,當該瑕疵共用配線之該斷線處位於該些資料配線其中 之二之間時,該些晝素電極其中之一具有一與該斷線處對 應之開口,且該修補線路位於該開口中,以與該些晝素電 極其中之一電性絕緣。 Π .如申請專利範圍第9項所述之薄膜電晶體陣列基 板,當該瑕疵共用配線之該斷線處位於該些資料配線其中 之一的下方時,與該斷線處相鄰之二畫素電極的邊緣處具 有一缺口,其中該修補線路係跨過該些資料配線其中之 一,且分佈該些缺口内,以與該些畫素電極電性絕緣。 1 2. —種薄膜電晶體陣列基板,包括: 一基板; 多數個掃描配線,配置於該基板上; 多數個資料配線,配置於該基板上,其中該些掃描配 線與該些資料配線係區分出多數個晝素區域; 多數個薄膜電晶體,每一該些薄膜電晶體係位於該些 晝素區域其中之一内,其中該些薄膜電晶體係藉由該些掃 描配線以及該些資料配線驅動; 多數個畫素電極,每一該些晝素電極係位於該些畫素 區域其中之一内,以與對應之該些薄膜電晶體其中之一電 性連接;13437twf.ptd Page 24 200535774 VI. Patent application scope A repair line is located above the broken line to be electrically connected to the defective scanning wiring on both sides of the broken line, where the repair line is connected to the pixels The electrodes are electrically insulated. 10. According to the thin film transistor array substrate described in item 9 of the scope of patent application, when the broken line of the defective common wiring is located between two of the data wirings, one of the daylight electrodes has An opening corresponding to the broken line, and the repair line is located in the opening to be electrically insulated from one of the day electrodes. Π. According to the thin film transistor array substrate described in item 9 of the scope of the patent application, when the disconnection of the defective common wiring is below one of the data wirings, the two adjacent to the disconnection are drawn There is a gap at the edge of the pixel electrode, wherein the repairing line crosses one of the data wirings and is distributed in the gaps so as to be electrically insulated from the pixel electrodes. 1 2. A thin film transistor array substrate comprising: a substrate; a plurality of scanning wirings arranged on the substrate; a plurality of data wirings arranged on the substrate, wherein the scanning wirings are distinguished from the data wirings A plurality of thin film transistors, each of the thin film transistor systems is located in one of the plurality of thin film regions, wherein the thin film transistor systems are provided by the scanning wirings and the data wirings Driving; a plurality of pixel electrodes, each of which is located in one of the pixel regions so as to be electrically connected to one of the corresponding thin film transistors; 13437twf.ptd 第25頁 200535774 六、申請專利範圍 多數個共用配線,配置於該基板上,且每一該些晝素 電極之部分區域係位於對應之該些共用配線其中之一的上 方,以構成一儲存電容,且該些共用配線中包括至少一瑕 疵共用配線,該瑕疵共用配線具有一斷線處;以及 一修補線路,位於該斷線處上方,其中該修補線路與 該些晝素電極至少其中之一係同時與該斷線處兩側之該瑕 疵共用配線電性連接。 1 3.如申請專利範圍第1 2項所述之薄膜電晶體陣列基 板,當該瑕疵共用配線之該斷線處位於該些資料配線其中 之一的下方時,與該瑕疵共用配線之該斷線處相鄰之二畫 素電極分別包括: 一顯示部分;以及 一修補部分,與該顯示部分電性絕緣,其中該修補線 路以及該修補部分係同時與該斷線處兩側之該瑕疵共用配 線電性連接。 1 4. 一種薄膜電晶體陣列基板,包括: 一基板; 多數個掃描配線,配置於該基板上; 多數個資料配線,配置於該基板上,其中該些掃描配 線與該些資料配線係區分出多數個晝素區域; 多數個薄膜電晶體,每一該些薄膜電晶體係位於該些 晝素區域其中之一内,其中該些薄膜電晶體係藉由該些掃 描配線以及該些資料配線驅動; 多數個晝素電極,每一該些晝素電極係位於該些畫素13437twf.ptd Page 25 200535774 VI. The scope of patent application Most common wiring is arranged on the substrate, and a part of each of the daylight electrodes is located above one of the corresponding common wirings to constitute A storage capacitor, and the common wirings include at least one defective common wiring, the defective common wiring has a broken line; and a repair line located above the broken line, wherein the repair line and the daylight electrodes are at least One of them is electrically connected to the defective common wiring on both sides of the disconnection at the same time. 1 3. According to the thin film transistor array substrate described in Item 12 of the scope of the patent application, when the disconnection of the defective common wiring is below one of the data wirings, the interruption of the common wiring with the defective The two adjacent pixel electrodes at the line respectively include: a display portion; and a repair portion electrically insulated from the display portion, wherein the repair line and the repair portion are shared with the defects on both sides of the disconnection at the same time Wiring is electrically connected. 1 4. A thin film transistor array substrate comprising: a substrate; a plurality of scanning wirings arranged on the substrate; a plurality of data wirings arranged on the substrate, wherein the scanning wirings are distinguished from the data wirings A plurality of thin film transistors; each of the thin film transistor systems is located in one of the plurality of thin film transistors, wherein the thin film transistor systems are driven by the scanning wirings and the data wirings ; A plurality of celestial electrodes, each of which is located at the pixels 13437twf.ptd 第26頁 200535774 六、申請專利範圍 區域其中之一内,以與對應之該些薄膜電晶體其中之一電 性連接;以及 多數個共用配線,配置於該基板上,且每一該些晝素 電極之部分區域係位於對應之該些共用配線其中之一的上 方,以構成一儲存電容,且該些共用配線中包括至少一瑕 疵共用配線,該瑕疵共用配線具有一斷線處,其中該些畫 素電極至少其中之一係與該斷線處兩側之該瑕疵共用配線 電性連接。 1 5.如申請專利範圍第1 4項所述之薄膜電晶體陣列基 板,當該瑕疵共用配線之該斷線處位於該些資料配線其中 之二之間時,該些晝素電極其中之一包括: 一顯示部分;以及 一修補部分,與該顯示部分電性絕緣,其中該修補線 路以及該修補部分係同時與該斷線處兩側之該瑕疵共用配 線電性連接。 1 6.如申請專利範圍第1 4項所述之薄膜電晶體陣列基 板,當該瑕疵共用配線之該斷線處位於該些資料配線其中 之一的下方時,更包括: 一修補線路,該修補線路係跨過該些資料配線其中之 一,且該修補配線、該斷線處相鄰之二晝素電極以及該斷 線處兩側之該瑕疵共用配線係彼此電性連接。 1 7. —種薄膜電晶體陣列基板的修補方法,適於對一 儲存電容在閘極上(Cst on gate)或儲存電容在共用配線 (C s t ο n c 〇 m m ο η )上之薄膜電晶體陣列基板進行修補,該13437twf.ptd Page 26 200535774 6. One of the patent application areas is electrically connected to one of the corresponding thin film transistors; and a plurality of common wirings are arranged on the substrate, and each of the Some regions of the day electrode are located above one of the corresponding common wirings to constitute a storage capacitor, and the common wirings include at least one defective common wiring having a broken line, At least one of the pixel electrodes is electrically connected to the defective common wiring on both sides of the disconnection. 1 5. According to the thin film transistor array substrate described in item 14 of the scope of patent application, when the disconnection of the defective common wiring is between two of the data wirings, one of the daylight electrodes It includes: a display part; and a repair part, which is electrically insulated from the display part, wherein the repair line and the repair part are electrically connected to the defective common wiring on both sides of the disconnection at the same time. 16. According to the thin film transistor array substrate described in item 14 of the scope of the patent application, when the broken line of the defective common wiring is located under one of the data wirings, it further includes: a repair line, the The repairing line crosses one of the data wirings, and the repairing wiring, the diurnal electrode adjacent to the broken line, and the defective common wiring on both sides of the broken line are electrically connected to each other. 1 7. A method for repairing a thin film transistor array substrate, suitable for a thin film transistor array having a storage capacitor on a gate (Cst on gate) or a storage capacitor on a common wiring (C st ο nc 〇mm ο η) Substrate repair, the 13437twf.ptd 第27頁 200535774 六、申請專利範圍 修補方法包括: 移除鄰近於一掃描配線或一共用配線之一斷線處之至 少一晝素電極的部份區域;以及 形成一修補線路於該斷線處上方,以使該修補線路與 該斷線處兩側之掃描配線或共用配線電性連接,其中該修 補線路係與該晝素電極電性絕緣。 1 8.如申請專利範圍第1 7項所述之薄膜電晶體陣列基 板的修補方法,當該掃描配線或該共用配線之該斷線處位 於二資料配線之間時,其中移除該晝素電極的部分區域之 步驟包括: 在該晝素電極中形成一與該斷線處對應之開口,其中 該修補線路係位於該開口中,而與該斷線處兩側之該掃描 配線或該共用配線電性連接。 1 9.如申請專利範圍第1 7項所述之薄膜電晶體陣列基 板的修補方法,當該掃描配線或該共用配線之該斷線處位 於一資料配線的下方時,其中移除該晝素電極的部分區域 之步驟包括: 在與斷線處相鄰之二晝素電極的邊緣處分別形成一缺 口 ,而該修補線路係跨過該資料配線,其中該修補線路係 分佈於該些缺口内。 2 〇.如申請專利範圍第1 7項所述之薄膜電晶體陣列基 板的修補方法,其中移除鄰該晝素電極的部份區域之方法 包括雷射移除。 2 1 .如申請專利範圍第1 7項所述之薄膜電晶體陣列基13437twf.ptd Page 27 200535774 VI. Patent application repair method includes: removing a part of at least one day electrode adjacent to a broken line of a scanning wiring or a common wiring; and forming a repairing line in the Above the broken line, the repair line is electrically connected with the scanning wiring or the common wiring on both sides of the broken line, wherein the repair line is electrically insulated from the day electrode. 1 8. According to the method for repairing the thin film transistor array substrate described in item 17 of the scope of patent application, when the disconnection of the scanning wiring or the common wiring is between two data wirings, the daylight element is removed. The step of a part of the electrode includes: forming an opening in the day electrode corresponding to the broken line, wherein the repair line is located in the opening and is shared with the scanning wiring or the two sides of the broken line Wiring is electrically connected. 1 9. According to the method for repairing a thin film transistor array substrate described in item 17 of the scope of patent application, when the disconnection of the scanning wiring or the common wiring is below a data wiring, the day element is removed therefrom. The steps of the partial area of the electrode include: forming a gap at the edge of the diuretic electrode adjacent to the broken line, and the repair line is across the data wiring, wherein the repair line is distributed in the gaps . 20. The method for repairing a thin film transistor array substrate according to item 17 of the scope of the patent application, wherein the method for removing a part of the region adjacent to the day electrode includes laser removal. 2 1. The thin film transistor array substrate as described in item 17 of the scope of patent application 13437twf.ptd 第28頁 200535774 六、申請專利範圍 板的修補方法,其中形成該修補線路之方法包括雷射化學 氣相沈積。 2 2. —種薄膜電晶體陣列基板的修補方法,適於對一 儲存電容在閘極上或儲存電容在共用配線上之薄膜電晶體 陣列基板進行修補,該修補方法包括: 移除鄰近於一掃描配線或一共用配線之一斷線處之至 少一畫素電極的部份區域,以使部分該晝素電極與該斷線 處兩側之該掃描配線或該共用線路電性連接。 2 3.如申請專利範圍第2 2項所述之薄膜電晶體陣列基 板的修補方法,當該掃描配線或該共用配線之該斷線處位 於二資料配線之間時,其中移除畫素電極的部分區域之步 驟包括: 切割該晝素電極以使該晝素電極分為一顯示部分及一 修補部分,其中該顯示部分與該修補部分電性絕緣,而該 修補部分係與該斷線處兩側之該掃描配線或該共用配線電 性連接。 2 4.如申請專利範圍第22項所述之薄膜電晶體陣列基 板的修補方法,當該掃描配線或該共用配線之該斷線處位 於一資料配線的下方時,其中移除晝素電極的部分區域之 步驟包括: 切割該晝素電極以使該晝素電極分為一顯示部分及一 修補部分,其中該顯示部分與該修補部分電性絕緣;以及 形成一修補線路於斷線處上方,該修補線路以及該修 補部分係同時與斷線處兩側之該掃描配線或該共用配線電13437twf.ptd Page 28 200535774 6. Scope of Patent Application The method for repairing the board, wherein the method for forming the repair circuit includes laser chemical vapor deposition. 2 2. A method for repairing a thin film transistor array substrate, which is suitable for repairing a thin film transistor array substrate having a storage capacitor on a gate electrode or a storage capacitor on a common wiring. The repair method includes: A portion of the wiring or at least one pixel electrode at a disconnection of a common wiring so that part of the day electrode is electrically connected to the scanning wiring or the common wiring at both sides of the disconnection. 2 3. According to the method for repairing the thin film transistor array substrate described in item 22 of the scope of the patent application, when the disconnection of the scanning wiring or the common wiring is between the two data wirings, the pixel electrode is removed. The steps of a partial area include: cutting the day element electrode so that the day element electrode is divided into a display portion and a repair portion, wherein the display portion is electrically insulated from the repair portion, and the repair portion is connected to the broken line The scanning wiring or the common wiring on both sides is electrically connected. 2 4. The method for repairing the thin film transistor array substrate according to item 22 of the scope of the patent application, when the disconnection of the scanning wiring or the common wiring is below a data wiring, the daylight electrode is removed. The steps of the partial region include: cutting the day element electrode to divide the day element electrode into a display portion and a repair portion, wherein the display portion is electrically insulated from the repair portion; and forming a repair line above the disconnection, The repairing line and the repairing portion are simultaneously connected to the scanning wiring or the common wiring on both sides of the disconnection. 13437twf.ptd 第29頁 200535774 六、申請專利範圍 性連接。 2 5.如申請專利範圍第2 2項所述之薄膜電晶體陣列基 板的修補方法,其中移除鄰該畫素電極的部份區域之方法 包括雷射移除。 2 6.如申請專利範圍第2 2項所述之薄膜電晶體陣列基 板的修補方法,其中形成該修補線路之方法包括雷射化學 氣相沈積。 2 7. —種薄膜電晶體陣列基板的修補方法,適於對一 儲存電容在閘極上或儲存電容在共用配線上之薄膜電晶體 陣列基板進行修補,該修補方法包括: 將鄰近於一掃描配線或一共用配線之一斷線處之至少 一晝素電極與該斷線處兩側之該掃描配線或共用配線電性 連接。 2 8.如申請專利範圍第2 7項所述之薄膜電晶體陣列基 板的修補方法,當該掃描配線或該共用配線之斷線處位於 一資料配線的下方時,更包括: 形成一修補線路於該斷線處上方,該修補線路以及與 該斷線處相鄰之二畫素電極係同時與該斷線處兩側之該掃 描配線或該共用配線電性連接。 2 9.如申請專利範圍第2 7項所述之薄膜電晶體陣列基 板的修補方法,其中與該斷線處兩側之該掃描配線或共用 配線電性連接之方式包括雷射熔接。13437twf.ptd Page 29 200535774 VI. Patent Application Scope Connection. 25. The method for repairing a thin film transistor array substrate according to item 22 of the scope of the patent application, wherein the method of removing a part of the area adjacent to the pixel electrode includes laser removal. 2 6. The method for repairing a thin film transistor array substrate according to item 22 of the scope of the patent application, wherein the method for forming the repair circuit includes laser chemical vapor deposition. 2 7. —A method for repairing a thin film transistor array substrate, which is suitable for repairing a thin film transistor array substrate with a storage capacitor on a gate or a storage capacitor on a common wiring. The repair method includes: Or at least one day electrode at a disconnection of a common wiring is electrically connected to the scanning wiring or the common wiring on both sides of the disconnection. 2 8. The method for repairing the thin film transistor array substrate according to item 27 of the scope of the patent application, when the disconnection of the scanning wiring or the common wiring is below a data wiring, it further includes: forming a repairing circuit Above the broken line, the repair line and two pixel electrodes adjacent to the broken line are simultaneously electrically connected to the scanning wiring or the common wiring on both sides of the broken line. 2 9. The method for repairing the thin film transistor array substrate according to item 27 of the scope of the patent application, wherein the method of electrically connecting the scanning wiring or the common wiring on both sides of the disconnection includes laser welding. 13437twf.ptd 第30頁13437twf.ptd Page 30
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