201112384 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置， 将別係有關於一種無線 弧之多晶片堆疊構造及其製造方法。 【先前技術】 業微小化與高處理速度 晶片模組化（Multi-Chip 或兩個以上之半導體晶 減整體封裝體積，並提 堆疊方法來增加單一封201112384 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and relates to a multi-wafer stack structure of a wireless arc and a method of fabricating the same. [Prior Art] Industry miniaturization and high processing speed Chip modularization (Multi-Chip or more than two semiconductor crystals reduce the overall package volume, and stacking methods to add a single
為了符合現今對於半導體產 的需求，半導體封裝結構已將多 Module)作為一趨勢。藉由將兩個 片組合在單一封裝結構中，以縮 升電性功能。近年來常使用多層 裝結構中的晶片數量 之設計與打線製程而 字堆疊。In order to meet the demand for semiconductor products today, semiconductor package structures have taken multiple modules as a trend. The electrical function is reduced by combining the two sheets in a single package structure. In recent years, the number of wafers in a multi-layer structure and the wire bonding process have often been used for word stacking.
，其堆疊的方式必須按照本身晶片 有所不同，例如：階梯狀堆疊、Z 傳統的打線機在面對多層晶片“單層晶片結構 時’需要先在上下層晶片的紹墊上打線方式種植金球(或 • 稱結線凸塊），作為線頭，然後再依照不同的需求，將金 線向後拉伸轉折做出理想的弧形。然:而，傳統的打線方 式’運用在產品上時常常會面臨許多問題。 如第！圖所示，一種習知的多晶片堆疊構造1〇〇，其 係主要包含一基板110、一上晶片12〇、一下晶片、 複數個銲線15卜152以及一封膠體17〇β以該下晶片13〇 之背面黏合至該基板110之上表面，該上晶片12〇係設 置於該下晶片130之主動面131上’而顯露該下晶片ι3〇 之銲墊132,以形成階梯狀之多晶片堆疊結構。在一打 201112384 線製程中’銲線151連接該上晶片120之銲墊122至該 下晶片130之銲墊132。再以打線方式，使銲線152壓 合至先形成銲線151在該下晶片120之銲墊122上之尾 端至該基板110之接指111，以完成整體的電性連接。 為了避免銲線151之尾端的沾不黏或者是銲墊122的破 裂’在下晶片120之銲墊122上應預先打上一獨立金球 153 ’以增加结合力與緩衝保護。該封膠體17〇係設置於 鲁 該基板11〇之上表面’以包覆該上晶片120、該下晶片 130與該些銲線140 »然而，在形成該封膠體17〇時，必 須要考慮到該些銲線140在該上晶片120之主動面121 上所產生的懸空線弧之高度，故無法有效地降低整體的 封裝高度。 由於傳統的多晶片之間與晶片與基板之間皆是利用 該些銲線140達到電性連接，在後續的多晶片堆疊製程 中會衍生出許多各種可能的封裝缺陷。例如，關於銲墊 ® 部分會有金球不黏（NSOP)、銲墊破裂（pad crack)問題， 關於銲線部分會有頸傷（neckdamage)、弧高不穩、甩線、 弧尚範圍受限、歪線（wire sweep after m〇ding)等問題， 關於接指部分，會有尾線不黏（NS〇L)、接指太小導致在 多層晶片堆疊無法打入太多銲線的問題。 【發明内容】 為了解決上述之問題，本發明之主要目的係在於提供 -種無線弧之多晶片堆疊構造’不會有超過上層晶片之 主動面的懸空線弧，能消除習知線弧造成的封裝缺陷？ 201112384 本發明之次一目的係在於提供一種無線弧之多晶片 堆疊構造，在製造過程中皆不需要作拉線弧與植球的動 作，除了可大幅地提升產能，亦無銲點不黏之情形並 能達到良好的晶片電性互連》 本發明之再一目的係在於提供一種無線弧之多晶片 堆疊構k，金線筆可隨意依照不同的線圖需求而改變晝 線路徑，亦能將金線換成其他任何金屬材質，以降低成 本。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示一種無線弧之多晶片堆疊構 造’主要包含一基板、一第一晶片、一第二晶片、一对 熱絕緣膠片以及複數個塗畫導線。該第一晶片係設置於 該基板上’該第一晶片係具有一遠離該基板之第一主動 面以及在該第一主動面上之複數個第一銲墊。該第二晶 片係設置於該第一晶片之第一主動面上但不完全覆蓋該 第一主動面’以顯露該些第一銲墊，該第二晶片係具有 一遠離該基板之第二主動面以及在該第二主動面上之複 數個第二銲墊。該耐熱絕緣膠片係彎曲地貼附至該第一 主動面與該第二主動面，並在該第一主動面與該第二主 動面之間提供一可塗畫斜坡。該些塗畫導線係熔附於該 耐熱絕緣膠片上，該些塗畫導線係順著該可塗晝斜坡以 連接該些第一銲墊與對應之該些第二銲墊。本發明另揭 示該無線弧之多晶片堆疊構造之製造方法。 本發明的目的及解決其技術問題還可採用以下技 201112384 措施進一步實現。 在則述之無線弧之多晶片堆疊構造中， 係可由一金線筆塗畫形成。 在刖述之無線弧之多晶片堆疊構造中， 片係可具有複數個第一開孔與第二開孔， 些第一銲塾與該些第二銲墊。 在則述之無線弧之多晶片堆疊構造中， 係可延伸至該些第一開孔與該些第二開孔 於該些第一銲墊與該些第二銲墊。 在前述之無線弧之多晶片堆疊構造中， 片係可更延伸至該基板，並在該第/主動 間提供一第二可塗畫斜坡。 在前述之無線弧之多晶片堆疊構造中， 係可順著該第二可塗畫斜坡以連接該些第 板之複數個接指。 在前述之無線弧之多晶片堆疊構造中， 個打線形成之銲線，係電性連接該些第一 之複數個接指。 在前述之無線弧之多晶片堆疊構造中， 一打線形成之跨接銲線，係連接該呰第一: 一與對應之第二銲墊，並在俯視圖中與該彳 至少一個構成電絕緣性交錯。 在前述之無線弧之多晶片堆疊構造中，Έ 充材，係形成於該耐熱絕緣膠月與該第二邊 該些塗畫導線 該耐熱絕緣膠 以分別顯露該 該些塗畫導線 ，以分別熔附 該耐熱絕緣膠 面與該基板之 該些塗畫導線 一銲塾與該基 可另包含複數 銲墊與該基板 可另包含至少 痒墊之其中之 昏塗畫導線之 Γ另包含一填 ;片側的空障:。:Ί 6 201112384 内 在前述之無線弧之多晶片堆疊構造中，可另包含一封 裝體’係形成於马r立4^ 風於该基板上，以密封該第一晶片與該第二 晶片。 在剛述之無線弧之多晶片堆疊構造中，可另包含至少 第一曰曰片，係設置於該第二晶片之第二主動面上但不 凡全覆蓋該第_主動面，以顯露該些第二銲墊，該第三 晶片係具有一遠離該基板之第三主動面以及在該第三主 動面上之複數個第三銲墊並且該耐熱絕緣膠月係更延 伸至該第三晶片之第三主動面並在該第三主動面與該 第二主動面之間提供另一可塗畫斜坡並且該些塗畫導 線係順著所述另—可塗晝斜坡以連接該些第三銲塾斑該 第三銲墊。 ^ 在别述之無線弧之多晶片堆疊構造中，該第一晶片、 該第二晶片與該第三晶片係可為階梯狀堆疊。 在前述之無線弧之多晶片堆疊構造中 一晶片組，係設置於該第二曰片夕笛 匕3主夕 部壓附至該耐熱絕緣膠，\ 主動面上，並局 …字堆:緣膠片，而與該第-晶片與該第二晶 由以上技術方案可以看出，本發 堆疊構造，有以下優點與功效：無線弧之多晶片 一、二由耐：緣心舆塗畫導線之特定組合關係作 马其中一技術手段，由於耐埶 附$筮 ’、’、、緣膠片係彎曲地貼 附至第-主動面與第二主動 从^供可塗晝斜ί 201112384 坡並且塗晝導線係順著可塗晝斜坡以連接第一銲 鲁與對應之第二銲塾。因此，不會有超過第二晶片 之第二主動面的懸空線弧，能消除習知線弧造成的 封裝缺陷。The stacking method must be different according to the chip itself. For example, the stepped stacking, Z traditional wire bonding machine needs to first lay the golden ball on the upper and lower wafers in the face of the multi-layer wafer "single-layer wafer structure". (or • Weigh the line bumps) as the thread head, and then according to different needs, the gold wire is stretched back to make the ideal arc shape. However: the traditional wire-laying method is often used when it is applied to the product. There are many problems faced. As shown in the figure, a conventional multi-wafer stack structure includes a substrate 110, an upper wafer 12, a lower wafer, a plurality of bonding wires 15 and 152, and a The colloid 17 〇β is bonded to the upper surface of the substrate 110 by the back surface of the lower wafer 13 , and the upper wafer 12 is disposed on the active surface 131 of the lower wafer 130 to expose the solder pad 132 of the lower wafer ι3 To form a multi-wafer stack structure in a stepped manner. In a dozen 201112384 wire process, the wire bond 151 connects the pad 122 of the upper wafer 120 to the pad 132 of the lower wafer 130. The wire bond 152 is further wired. Press-fit to the shape The bonding wire 151 is on the tail end of the pad 122 of the lower wafer 120 to the finger 111 of the substrate 110 to complete the overall electrical connection. In order to avoid the sticking of the tail end of the bonding wire 151 or the pad 122 The crack ruptures should be pre-applied with a separate gold ball 153' on the pad 122 of the lower wafer 120 to increase the bonding force and the buffer protection. The sealant 17 is disposed on the upper surface of the substrate 11 以 to cover the rupture The wafer 120, the lower wafer 130 and the bonding wires 140. However, in forming the sealing body 17, the flying line arc generated by the bonding wires 140 on the active surface 121 of the upper wafer 120 must be considered. The height of the package cannot effectively reduce the overall package height. Since the conventional multi-wafers and the wafers and the substrates are electrically connected by the bonding wires 140, they are derived in the subsequent multi-wafer stacking process. There are many possible package defects. For example, there are gold ball non-stick (NSOP) and pad crack problems in the solder pad®. Neckdamage, arc height instability, and wire arc instability甩 line, arc is still limited, 歪Wire sweep after m〇ding and other issues. Regarding the finger part, there is a problem that the tail wire is not sticky (NS〇L), and the finger is too small, so that too many wire bonds cannot be inserted in the multilayer wafer stack. In order to solve the above problems, the main object of the present invention is to provide a multi-wafer stack structure of a wireless arc that does not have a flying-line arc exceeding the active surface of the upper wafer, and can eliminate package defects caused by conventional arcs. 201112384 The second object of the present invention is to provide a multi-wafer stack structure of a wireless arc, which does not require the action of pulling arc and ball-planting in the manufacturing process, except that the productivity can be greatly improved, and no solder joints are adhered. A further object of the present invention is to provide a multi-wafer stack structure of a wireless arc, and the gold line pen can change the twist line path according to different line drawing requirements. Can replace the gold wire with any other metal material to reduce costs. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses a wireless arc multi-wafer stack structure 'mainly comprising a substrate, a first wafer, a second wafer, a pair of thermally insulating films, and a plurality of painted wires. The first wafer is disposed on the substrate. The first wafer has a first active surface away from the substrate and a plurality of first pads on the first active surface. The second wafer is disposed on the first active surface of the first wafer but does not completely cover the first active surface ′ to expose the first pads, and the second wafer has a second active away from the substrate And a plurality of second pads on the second active surface. The heat resistant insulating film is flexibly attached to the first active surface and the second active surface, and a paintable slope is provided between the first active surface and the second active surface. The painted wires are fused to the heat-resistant insulating film, and the painted wires are followed by the applicable slope to connect the first pads and the corresponding second pads. The present invention further discloses a method of fabricating a multi-wafer stack configuration of the wireless arc. The object of the present invention and solving the technical problems thereof can be further realized by the following measures 201112384. In the multi-wafer stack construction of the wireless arc described above, it can be formed by painting a gold line pen. In the multi-wafer stack configuration of the wireless arc described above, the film system may have a plurality of first openings and second openings, and the first solder pads and the second pads. In the multi-wafer stack structure of the wireless arc described above, the first opening and the second opening may extend to the first pad and the second pads. In the aforementioned wireless arc multi-wafer stack configuration, the wafer system can extend further to the substrate and provide a second paintable ramp between the first/active regions. In the aforementioned multi-wafer stack configuration of the wireless arc, the second drawable ramp can be followed to connect the plurality of fingers of the plurality of first plates. In the above-described wireless arc multi-wafer stack structure, the bonding wires formed by the bonding wires are electrically connected to the first plurality of fingers. In the above-described wireless arc multi-wafer stack structure, a jumper wire formed by a single wire is connected to the first wire: a corresponding second pad, and is electrically insulated from at least one of the wires in a plan view. staggered. In the above-mentioned wireless arc multi-wafer stack structure, the ruthenium material is formed on the heat-resistant insulating rubber month and the second side of the painted conductive heat-insulating adhesive to respectively expose the painted wires to respectively The heat-resistant insulating rubber surface is welded to the painted wires of the substrate, and the substrate may further comprise a plurality of solder pads, and the substrate may further comprise at least a faintly drawn wire of the itch pad, and further comprising a filling ; air barrier on the side of the film: : Ί 6 201112384 In the above-described wireless arc multi-wafer stack structure, an additional package body may be further formed on the substrate to seal the first wafer and the second wafer. In the multi-wafer stack configuration of the wireless arc just described, at least a first die may be further disposed on the second active surface of the second wafer but cover the first active surface to cover the first active surface. a second bonding pad, the third wafer has a third active surface away from the substrate and a plurality of third pads on the third active surface and the heat resistant insulating resin extends to the third wafer a third active surface and providing another paintable slope between the third active surface and the second active surface and the painted wires are along the other-applicable slope to connect the third welds Freckle the third pad. In the multi-wafer stack configuration of the wireless arc, which is not described, the first wafer, the second wafer, and the third wafer system may be stepped stacked. In the above-mentioned wireless arc multi-wafer stack structure, a chip set is disposed on the second 夕 夕 夕 匕 主 主 压 压 压 压 压 压 压 压 压 压 压 压 压 字 字 字 字 字 字 字 字 字 字 字 字The film, and the first wafer and the second crystal can be seen from the above technical solution, the stacked structure of the present invention has the following advantages and effects: the multi-wafer of the wireless arc, the second and the second are made of the wire: The specific combination relationship is one of the technical means of the horse, because the 埶 埶 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 The wire is routed along the applicable ramp to connect the first weld to the corresponding second weld. Therefore, there is no flying line arc exceeding the second active surface of the second wafer, which eliminates the package defects caused by the conventional line arc.
可藉由耐熱絕緣膠片與塗畫導線之特定組合關係作 為其中一技術手段，由於耐熱絕緣膠片係具有第一 與第二開孔，以分別顯露第一與第二銲墊並且塗 畫導線係延伸至第一與第二開孔，分別熔附於第一 與第二銲墊。因此’不會發生銲點不黏之情形，並 能達到良好的晶片電性互連。 可藉由耐熱絕緣膠片與塗畫導線之特定組合關係作 為其中一技術手段，由於塗畫導線係由金線筆塗晝 形成，再藉由耐熱絕緣膠片之隔離，使得塗畫導線 可隨意依照不同的線圖需求而改變畫線路徑。此 外，更能將金線換成其他任何金屬材質，以降低成 可藉由对熱絕緣膠片與塗畫導線之特定組合關係作 為其中一技術手段，在製造過程中皆不需要作拉線 弧與植球的動作，故能大幅地提升產能，更適用於 多層晶月堆疊的結構。 可藉由耐熱絕緣膠月與銲線之特定組合關係作為其 中一技術手段，藉由銲線電性連接第一銲墊與基板 之接指，使得耐熱絕緣膠片可不必延伸至基板，減 少塗畫導線的塗畫長度，並降低因晶片與基板間靡。 201112384 力影響而導致耐熱絕緣膠片的坡度改變。 【實施方式】 以下將配合所附圖示詳細說明本發明之實施例，然應 注意的是，該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法，故僅顯示與本案 有關之件與組合關係，圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 φ 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設計，詳細之元件佈局可能更為複雜。 依據本發明之第一具體實施例，一種無線弧之多晶片 堆疊構造舉例說明於第2圖之截面示意圖與第3圖未封 裝别之立體不意圖。該無線弧之多晶片堆疊構造2〇〇係 主要包含一基板210、一第一晶片22〇、一第二晶片23〇、 一耐熱絕緣膠片240以及複數個塗畫導線25〇。在本實 籲 施例中，該基板210係可具有複數個接指211。該些接 才曰211係可設置於該基板21〇的上表面之同一侧邊。詳 細而言’通常該基板210係可為一印刷電路板、一電路 薄膜或各種晶片載板。 請參閱第2圖所示，該第一晶片22〇係設置於該基板 210上，該第一晶片220係具有一遠離該基板21〇之第 一主動面221以及在該第一主動面221上之複數個第一 銲墊222。也就是說，該第一晶片22〇之該第一主動面 221並非貼附於該基板210之上表面，以使該些第一样 201112384 墊222朝上設置。此外，該第二晶片23〇係設置於該第 一晶片220之第一主動面221上但不完全覆蓋該第一主 動面221，以顯露該些第一銲墊222。該第二晶片23〇 係具有一遠離該基板21〇之第二主動面231以及在該第 一主動面231上之複數個第二銲墊23 2。在一較佳實施 例中，該些第一銲墊222與該些第二銲墊232係鄰近於 該基板2 1 0之該些接指2丨丨，以縮短晶片之間連接線路 之長度而降低訊號延遲與存取時間。該笫一晶片220與 該第二晶片230可為實質相同之晶片，而具有相同積體 電路功能、尺寸與銲墊分佈。該第一晶片220與該第二 晶片230之間的堆疊可為階梯狀。 請再參閱第2與3圖所示，該耐熱絕緣膠片240係彎 曲地貼附至該第一主動面221與該第二主動面231，並 在該第一主動面221與該第二主動面231之間提供一可 塗晝斜坡241。更進一步地’該耐熱絕緣膠片240係可 更延伸至該基板210，並在該第一主動面221與該基板 2 1 0之間提供一第二可塗畫斜坡244。在本實施例中，該 耐熱絕緣膠片240係可具有複數個第一開孔242與第二 開孔243，以分別顯露該些第一銲墊222與該些第二薛 墊232 »詳細而言，由於該耐熱絕緣膠片240提供了該 可塗畫斜坡241，而非完全緊貼於該第二晶片230之側 面，故會在該耐熱絕緣膠片240與該第二晶片230側之 間會產生空隙。較佳地’可另包含一填充材260，係形 成於該对熱絕緣膠片2 4 0與該第一晶片2 3 0侧的空隙 r 10 201112384 内，能加強該耐熱絕緣膠片240與該第二晶片no之黏 著強度，更可用以支撐該对熱絕緣膠片240，以維持該 可塗畫斜坡241之平整度與坡度。此外，倘若該耐熱絕 緣膠片240與該第一晶片220側形成空隙，亦可在封裝 前利用該填充材260填補’能強化整體結構，以避免該 耐熱絕緣膠片24〇斷折或變形。在一較佳實施例中，該 耐熱絕緣膠片240係可為預型片（pref〇rm)，本身具有黏 性，可省略一黏著層，並能依照不同需求而改變該耐熱 絕緣膠片240之尺寸，以符合各種不同的晶片堆疊結 構’例如：階梯狀堆疊、Z字堆疊。 再請參閱第2與3圖所示，該些塗晝導線25〇係熔附 於該耐熱絕緣膠片240上，該些塗畫導線25〇係順著該 可塗晝斜坡241以連接該些第一銲墊222與對應之該些 第二銲墊232。在本實施例中，該些塗畫導線25〇係可 由一金線筆50塗畫形成.在另一變化實施例中，可將該 籲 金線筆5〇更換為其他任何金屬材質，例如：鋁、銅等價 格較為便宜之材質，以降低製造成本。詳細而言，該金 線筆50係預先加熱至可使該些塗畫導線25〇成融熔態的 /m度其加熱方式可採用尖端加熱或放電方式，以減少 能源消耗。在本實施例中，該些塗畫導線250係可延伸 至該些第一開孔242與該些第二開孔243，以分別熔附 於該些第一銲墊222與該些第二銲墊232。由於該些塗 畫導線250係在融熔態時與該些銲墊結合故在冷卻之 後能達到最佳共晶狀態，而不會發生銲點不黏之情形。 201112384 更進一步地，該些塗畫導線25〇係可順著該第二可塗畫 斜坡244以連接該些第一銲墊222與該基板210之該些 接指211。此外’可另包含一封裝體27〇，係形成於該基 板210上’以密封該第一晶片22〇與該第二晶片23〇。 由於該些塗畫導線250係平貼於該耐熱絕緣膠片24〇 上，並不會形成線弧，故能有效地降低該封裝體27〇之 南度。The specific combination relationship between the heat-resistant insulating film and the painted wire can be used as one of the technical means, since the heat-resistant insulating film has first and second openings to respectively expose the first and second pads and to draw the wire extension The first and second openings are respectively fused to the first and second pads. Therefore, there is no possibility that the solder joints will not stick and a good electrical interconnection of the wafer can be achieved. The specific combination relationship between the heat-resistant insulating film and the painted wire can be used as one of the technical means. Since the painted wire is formed by the gold pen, and then separated by the heat-resistant insulating film, the painted wire can be freely adapted. The line graph needs to change the line path. In addition, it is better to replace the gold wire with any other metal material to reduce the specific combination relationship between the heat insulating film and the painted wire as one of the technical means, and no arcing is required in the manufacturing process. The ball-planting action can greatly increase the productivity, and is more suitable for the structure of multi-layer crystal moon stacking. The specific combination of the heat-resistant insulating rubber and the bonding wire can be used as one of the technical means, and the bonding wire of the first bonding pad and the substrate is electrically connected by the bonding wire, so that the heat-resistant insulating film does not need to extend to the substrate, and the painting is reduced. The length of the wire is painted and reduced due to flaws between the wafer and the substrate. 201112384 The influence of the force causes the slope of the heat-resistant insulating film to change. The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which Therefore, only the parts and combinations related to the case are displayed. The components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios φ are proportional to other related sizes or are exaggerated or simplified. To provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. In accordance with a first embodiment of the present invention, a multi-wafer stack configuration of a wireless arc is illustrated in the cross-sectional view of Fig. 2 and the unsealed view of Fig. 3 unenclosed. The wireless arc multi-wafer stack structure 2 mainly comprises a substrate 210, a first wafer 22, a second wafer 23, a heat-resistant insulating film 240, and a plurality of painted wires 25A. In the present embodiment, the substrate 210 can have a plurality of fingers 211. The plurality of contacts 211 can be disposed on the same side of the upper surface of the substrate 21A. DETAILED DESCRIPTION Generally, the substrate 210 can be a printed circuit board, a circuit film, or various wafer carriers. As shown in FIG. 2 , the first wafer 22 is disposed on the substrate 210 , and the first wafer 220 has a first active surface 221 away from the substrate 21 and on the first active surface 221 . A plurality of first pads 222. That is, the first active surface 221 of the first wafer 22 is not attached to the upper surface of the substrate 210, so that the first 201112384 pads 222 are disposed upward. In addition, the second wafer 23 is disposed on the first active surface 221 of the first wafer 220 but does not completely cover the first active surface 221 to expose the first pads 222. The second wafer 23 has a second active surface 231 remote from the substrate 21 and a plurality of second pads 23 2 on the first active surface 231. In a preferred embodiment, the first pads 222 and the second pads 232 are adjacent to the contacts 2 of the substrate 210 to shorten the length of the connection between the wafers. Reduce signal delay and access time. The first wafer 220 and the second wafer 230 can be substantially identical wafers having the same integrated circuit function, size and pad distribution. The stack between the first wafer 220 and the second wafer 230 may be stepped. Referring to FIGS. 2 and 3, the heat-resistant insulating film 240 is flexibly attached to the first active surface 221 and the second active surface 231, and the first active surface 221 and the second active surface are A smear ramp 241 is provided between 231. Further, the heat resistant insulating film 240 can be extended to the substrate 210, and a second paintable slope 244 is provided between the first active surface 221 and the substrate 210. In this embodiment, the heat-resistant insulating film 240 can have a plurality of first openings 242 and second openings 243 to respectively expose the first pads 222 and the second pads 232 » in detail Since the heat-resistant insulating film 240 provides the drawable slope 241 instead of being completely in contact with the side of the second wafer 230, a gap is formed between the heat-resistant insulating film 240 and the second wafer 230 side. . Preferably, a filler 260 is further included in the gap between the pair of thermal insulation film 240 and the first wafer 203 side, r 10 201112384, to strengthen the heat-resistant insulating film 240 and the second The adhesion strength of the wafer no can be used to support the pair of thermal insulation films 240 to maintain the flatness and slope of the paintable slope 241. In addition, if the heat-resistant insulating film 240 forms a gap with the first wafer 220 side, it can be filled with the filler 260 before packaging to strengthen the overall structure to prevent the heat-resistant insulating film 24 from being broken or deformed. In a preferred embodiment, the heat-resistant insulating film 240 can be a pre-formed film, which has adhesiveness, can omit an adhesive layer, and can change the size of the heat-resistant insulating film 240 according to different needs. To conform to a variety of different wafer stack structures 'eg, stepped stacking, zigzag stacking. Referring to FIGS. 2 and 3, the coated wires 25 are fused to the heat-resistant insulating film 240, and the painted wires 25 are attached to the coatable slopes 241 to connect the first A pad 222 corresponds to the second pads 232. In this embodiment, the painted wires 25 can be formed by painting a gold pen 50. In another variant, the ring pen 5 can be replaced with any other metal material, for example: Aluminum, copper and other cheaper materials to reduce manufacturing costs. In detail, the gold pen 50 is preheated to a /m degree at which the painted wires 25 can be melted. The heating method can be a tip heating or discharging method to reduce energy consumption. In this embodiment, the painted wires 250 extend to the first openings 242 and the second openings 243 to be respectively fused to the first pads 222 and the second pads. Pad 232. Since the painted wires 250 are combined with the pads in the molten state, the optimum eutectic state can be achieved after cooling, and the solder joints do not stick. Further, the painted wires 25 can follow the second drawable slope 244 to connect the first pads 222 and the fingers 211 of the substrate 210. Further, a package 27 is formed on the substrate 210 to seal the first wafer 22 and the second wafer 23A. Since the painted wires 250 are flatly attached to the heat-resistant insulating film 24, and no line arc is formed, the south of the package 27 can be effectively reduced.
在本發明中，利用該耐熱絕緣膠片240彎曲地貼附至 該第一主動面221與該第二主動面231與該些塗畫導線 250順著該可塗畫斜坡241以連接該第一銲墊與對 應之第二銲墊232之特定組合關係，故不會有超過該第 一"晶片 2 3 0 之該第二 Φ tC» Ο 〇 1 AL· βΑ 一主動面23 1的懸空線弧，能消除習 知線弧造成的封裝缺陷，例如晶片銲墊上金球不黏、銲 墊破裂等問題、銲線的頸傷、弧高不穩、甩線、弧高範 圍受限、歪線（或稱沖線）等問題、接指的尾線不黏無 法使連接多層晶片堆疊之多條銲線打在同—較小接指上 等問題。並且’藉由該耐妖铒鏠 J热絕緣膠片240之隔離，使該 金線筆50可隨意依照不同的 久土 綠圖需未而改變該些塗畫 導線250之路徑。因此，該盔 …線孤之多晶片堆疊構造200 毋須設置有習知的銲線，在劁 长製&過程中不需做線弧或植 球的動作，能夠省略以往的 ^/ 刃打線製程，以大幅地提升產 月匕（Urm Per Hour，UPH)與產品良率。 本發明還揭示該無線弧之吝 、 <多晶片堆疊構造之製造方 法舉例說明於第4A至4H圄 > -从 70件截面示意圖。詳細典Ί 12 201112384 驟說明如下所示》 首先’如第4A圖所示，提供一基板210。該基板210 係可具有複數個接指211，該些接指211係設置於該基 板210的上表面之同一側邊。在本實施例中，通常該基 板210係可為一印刷電路板、一電路薄膜或各種晶片載 板0 再如第4B圖所示，設置一第一晶片220於該基板210 鲁 上’該第一晶片220係具有一遠離該基板210之第一主 動面221以及在該第一主動面221上之複數個第一銲墊 222。也就是說’在設置該第一晶片220時，係將該第一 主動面221朝上設置，並以該第一晶片220之背面貼附 至該基板210之上表面》 接著’如第4C圖所示，設置一第二晶片23〇於該第 一晶片220之第一主動面221上但不完全覆蓋該第一主 動面221，以顯露該些第一銲墊222，該第二晶片230 # 係具有一遠離該基板21〇之第二主動面23 1以及在該第 二主動面231上之複數個第二銲墊232。更具體地，在 設置該第一晶片220與該第二晶片230時，使該些第一 銲墊222與該些第二銲墊232鄰近於該基板21〇之該些 接指211’故能縮短晶片間連接線路之長度而降低訊號 延遲與存取時間。 如第4D圖所示，提供一耐熱絕緣膠片24〇。在本實 施例中’該耐熱絕緣膠片240係可具有複數個第一開孔 242與第二開孔243。接著，如第4E圖所示，彎曲地貼 13 201112384 附該耐熱絕緣膠片240至該第一主動面221與該第二主 • 動面231’並在該第一主動面221與該第二主動面231 之間提供一可塗畫斜坡241。此外，該耐熱絕緣膠片240 係可更延伸至該基板210，並在該第一主動面221與該 基板210之間提供一第二可塗晝斜坡244。較佳地，藉 由該可塗畫斜坡241與該第二可塗畫斜坡244,使得該 耐熱絕緣膠片240能更平順地貼附於所覆蓋的區域。在 鲁 貼附該耐熱絕緣膠片240之後，該些第一開孔242與該 些第二開孔243係分別顯露該些第一銲墊222與該些第 二銲塾23 2，以利後續步驟之進行。 如第4F至4H圖所示，執行一畫線操作，以形成複 數個塗晝導線250’其係熔附於該耐熱絕緣膠片240上。 在本實施例中’該些塗晝導線250係可由一金線筆50 提供’其材質可包含鋁、銅或其它可共晶化金屬。首先， 如第4F圖所示’加熱該金線筆5〇，使其溫度提升至可 • 使該些塗畫導線250轉化成融熔態，並填入對應的第二 開孔243 ’以接合至對應第二銲墊232 ^在此步驟中，其 加熱方式係可採尖端加熱或放電形式達成，以減少能源 消耗。可利用少量能源消耗便能使電燈泡將中心鎢絲快 速加熱至攝氏千度。接著，如第4G圖所示，移動該金 線筆50 ’使該些塗畫導線25〇順著該可塗晝斜坡241以 連接該些第一銲墊222與對應之該些第二銲墊232。在 本實施例中，該些塗畫導線25〇係可延伸至該些第一開 孔242與該些第二開孔243，以分別熔附於該些第一 14 201112384 墊222與該些第一銲墊232。此外，由該金線筆5〇畫出 導線路徑的該些塗畫導線25〇係平貼於該耐熱絕緣膠片 240,故不會產生任何線弧。再如第4H圖所示，在本實 施例中，可繼續移動該金線筆50，使該些塗畫導線25〇 順著該第二可塗畫斜坡244以連接該些第一銲塾222與 該基板210之該些接指211 ’以完成電性連接。在此步 驟中，由於該些塗晝導線250係在融熔狀態下以塗畫方In the present invention, the heat-resistant insulating film 240 is flexibly attached to the first active surface 221 and the second active surface 231 and the painted wires 250 along the drawable slope 241 to connect the first solder. The specific combination of the pad and the corresponding second pad 232 does not exceed the dangling line arc of the second Φ tC» Ο AL1 AL· β Α an active surface 23 1 of the first "wafer 2 3 0 It can eliminate the package defects caused by the conventional arc, such as the problem that the gold ball on the wafer pad is not sticky, the pad is broken, the neck of the wire, the arc height is unstable, the twist line, the arc height is limited, and the line is Or the problem of the rushing line), the tail line of the finger is not sticky, and the problem that multiple wire bonding wires connected to the multilayer wafer stack are placed on the same-small connecting finger. And by the isolation of the tamper-resistant J thermal insulation film 240, the gold pen 50 can freely change the path of the painted wires 250 according to different long-term green maps. Therefore, the helmet-lined multi-chip stack structure 200 does not need to be provided with a conventional bonding wire, and does not need to perform a line arc or a ball-planting operation in the process of the lengthening process, and can omit the conventional ^/blade wire-making process. To significantly increase Urm Per Hour (UPH) and product yield. The present invention also discloses that the method of manufacturing the wireless arc and <multi-wafer stacking structure is illustrated in Figs. 4A to 4H圄> Detailed Description 12 201112384 The following description shows the following: First, as shown in Fig. 4A, a substrate 210 is provided. The substrate 210 can have a plurality of fingers 211 disposed on the same side of the upper surface of the substrate 210. In this embodiment, the substrate 210 can be a printed circuit board, a circuit film, or various wafer carriers. As shown in FIG. 4B, a first wafer 220 is disposed on the substrate 210. A wafer 220 has a first active surface 221 away from the substrate 210 and a plurality of first pads 222 on the first active surface 221. That is, when the first wafer 220 is disposed, the first active surface 221 is disposed upward, and the back surface of the first wafer 220 is attached to the upper surface of the substrate 210. Next, as shown in FIG. 4C As shown, a second wafer 23 is disposed on the first active surface 221 of the first wafer 220 but does not completely cover the first active surface 221 to expose the first pads 222. The second wafer 230 # There is a second active surface 23 1 away from the substrate 21 and a plurality of second pads 232 on the second active surface 231 . More specifically, when the first wafer 220 and the second wafer 230 are disposed, the first pads 222 and the second pads 232 are adjacent to the fingers 211 ′ of the substrate 21 Shorten the length of the connection line between chips to reduce signal delay and access time. As shown in Fig. 4D, a heat resistant insulating film 24 is provided. In the present embodiment, the heat-resistant insulating film 240 may have a plurality of first openings 242 and second openings 243. Next, as shown in FIG. 4E, the heat-resistant insulating film 240 is attached to the first active surface 221 and the second main moving surface 231', and the first active surface 221 and the second active surface are attached. A drawable ramp 241 is provided between faces 231. In addition, the heat-resistant insulating film 240 can extend further to the substrate 210, and a second applicable slope 244 is provided between the first active surface 221 and the substrate 210. Preferably, the heat-resistant insulating film 240 can be attached to the covered area more smoothly by the paintable slope 241 and the second paintable slope 244. After the heat-insulating insulating film 240 is attached, the first opening 242 and the second opening 243 respectively expose the first bonding pads 222 and the second bonding pads 23 2 to facilitate subsequent steps. Go on. As shown in Figs. 4F to 4H, a line drawing operation is performed to form a plurality of coated wires 250' which are attached to the heat-resistant insulating film 240. In the present embodiment, the coated wires 250 may be provided by a gold pen 50. The material may comprise aluminum, copper or other eutectic metal. First, as shown in FIG. 4F, 'heating the gold pen 5 〇 to raise the temperature to • convert the painted wires 250 into a molten state, and fill the corresponding second opening 243 ′ to engage To correspond to the second pad 232 ^ In this step, the heating mode can be achieved by adopting a tip heating or discharging form to reduce energy consumption. With a small amount of energy consumption, the bulb can quickly heat the central tungsten wire to a thousand degrees Celsius. Then, as shown in FIG. 4G, the gold pen 50' is moved to cause the painted wires 25 to follow the applicable slope 241 to connect the first pads 222 and the corresponding second pads. 232. In this embodiment, the painted wires 25 can extend to the first openings 242 and the second openings 243 to be respectively fused to the first 14 201112384 pads 222 and the first A solder pad 232. Further, the painted wires 25 drawn by the gold pen 5's wire path are affixed to the heat-resistant insulating film 240, so that no line arc is generated. As shown in FIG. 4H, in the embodiment, the gold pen 50 can be further moved to cause the painted wires 25 to follow the second drawable slope 244 to connect the first pads 222. The fingers 211' of the substrate 210 are electrically connected. In this step, since the coated wires 250 are in a molten state to be painted
式與該些第一銲墊222、該些第二銲墊232以及該些接 指211產生接合，在冷卻之後，能達到最佳共晶狀態， 故不會發生習知打線銲點沾不黏與銲墊破裂之情形。在 一較佳實施例中，可另形成一填充材26〇於該耐熱絕緣 膠片240之底面與該第二晶片23〇的側面的空隙内以 填補前述之空隙。最後，可另形成一封裝體270於該基 板21〇上，以密封該第一晶片22〇與該第二晶片23〇(如 第2圖所示）。因為不會有突出該第二晶片23〇之該第二 主動面23 i之懸空線弧，在形成該封裝體27〇時能盡 可能地貼近於該第二主動面231，以降低整體的封裝高 度0 依據本發明之第二具體實施例，另一種無線弧之多晶 片堆疊構造舉例說明於第5圖之截面示意圖。該無線弧 之多晶片堆疊構造300係主要包含一基板31〇、一第一 b曰片220、一第二晶片23〇、一耐熱絕緣膠片以及複 數個塗晝導$ 250。其中與第—實施例相同的主要元件 將以相同符號標示’不再詳予贅述。在本實施例中，^The first bonding pad 222, the second bonding pads 232 and the connecting fingers 211 are joined to each other, and after cooling, the optimal eutectic state can be achieved, so that the known soldering joints do not stick to each other. The situation with the rupture of the pad. In a preferred embodiment, a filler 26 may be formed in the gap between the bottom surface of the heat-resistant insulating film 240 and the side surface of the second wafer 23A to fill the gap. Finally, a package 270 may be further formed on the substrate 21 to seal the first wafer 22 and the second wafer 23 (as shown in Fig. 2). Since there is no flying-line arc protruding from the second active surface 23 i of the second wafer 23 , the second active surface 231 can be as close as possible when the package 27 is formed to reduce the overall package. Height 0 In accordance with a second embodiment of the present invention, another wireless arc multi-wafer stack configuration is illustrated in cross-section of Figure 5. The multi-wafer stack structure 300 of the wireless arc mainly comprises a substrate 31, a first b-plate 220, a second wafer 23, a heat-resistant insulating film, and a plurality of coatings $250. The same elements as those of the first embodiment will be denoted by the same reference numerals and will not be described in detail. In this embodiment, ^
ί S 15 201112384 包含更多晶片。 請參閱第5圖所示，可另包含至少一第三晶片38〇, 係設置於該第二晶片230之第二主動面23 1上但不完全 覆蓋該第二主動面231，以顯露該些第二銲墊232,該第 三晶片380係具有一遠離該基板310之第三主動面381 以及在該第三主動面381上之複數個第三銲墊382,並 且該对熱絕緣膠片240係更延伸至該第三晶片380之第 三主動面3 81’並在該第三主動面381與該第二主動面 231之間提供另一可塗畫斜坡341，並且該些塗晝導線 250係順著所述另一可塗晝斜坡341以連接該些第二銲 些232與該第三銲墊382。在本實施例中該第一晶片 220、該第二晶片23〇與該第三晶片38〇係可為階梯狀堆 疊。在一變化實施例中，可依照產品需求增加該第三晶 片3 80之堆疊數量，以增加整體的運作性能◊此外，該 基板310係可因應該第三晶片38〇之堆疊數量而適當改 變尺寸，以提供足夠的封裝空間。由於該些塗畫導線25〇 係平貼於該时熱絕緣膠片24〇上，而不會產生有任何懸 工線弧，即使在因應需求而增加該第三晶片之堆疊 數量之Jf況下，亦能完全排除以往打線製程後.，習知的 錄線所產生的隸高度，以有效地降低整體封裝高度。 依據本發明之第三具體實施例，另一種多晶片堆疊構 造舉例說明於第6圖之截面示意圖。該多晶片堆疊構造 400係主要包含基板21〇、一第一晶片220、一第二晶 片230、一封熱絕緣膠片24〇以及複數個塗晝導線25〇。— 16 201112384 其中與第一實施例相同的主要元件將以相同符號標示， 不再詳予贅述。 請參閱第6圖所示，可另包含至少一晶片組49〇，係 設置於該第二晶片230之第二主動面231上，並局部壓 附至該耐熱絕緣膠片240，而與該第一晶片22〇與該第 二晶片230為Z字堆疊。詳細而言，該晶片組490係由 複數個B曰片所組成’其中該些晶片、該第一晶片220與 該第二晶片230係可為實質相同，而具有相同尺寸與功 鲁 能之半導體晶片。該晶片組490的晶片堆疊方式可與該 第一晶片220與該第二晶片230的階梯狀堆疊方式相 同。在本實施例中，該耐熱絕緣膠片240係可彎曲地貼 附至該些晶片之主動面，並藉由該些塗畫導線250完成 該些晶片之間的電性連接。更進一步地，該晶片組49〇 係可藉由一黏著層491黏合至該第二晶片230之該第二 主動面231上。此外，可另包含複數個打線形成之銲線 φ 441與442,其中該些銲線441係電性連接該些第一銲塾 222與該基板210之複數個接指21卜該些銲線442係可 電性連接該晶片組490之銲墊與該些接指211。因此， 該耐熱絕緣膠片240可不必延伸至該基板2 1 0，能減少 該些塗畫導線250的塗晝長度，每一晶片組所使用的耐 熱絕緣膠片可具有相同長度，並且每一晶片組能先完成 晶片堆疊與塗畫出導線之後，再電性連接至該基板 210»此外，能避免因晶片與基板間應力影響而導致該耐 熱絕緣膠片240的坡度改變。 17 201112384 依據本發明之第四具體實施例，另一種多晶片堆疊構 造舉例說明於第7圖之戴面示意圖。該多晶片堆疊構造 500係主要包含—基板21〇、一第一晶片220、一第二晶 片230、―对熱絕緣膠片240以及複數個塗畫導線250。 其中與第一實施例相同的主要元件將以相同符號標示， 不再詳予贅述。 請參閱第7圖所示，可另包含至少一打線形成之跨接 銲線541，係連接該些第一銲墊222之其中之一與對應 之第一銲墊232，並在俯視圖中與該些塗畫導線25〇之 ’個構成電絕緣性交錯，無銲線沖線（wire sweep) 的短路問題。因此，可提供雙（多）層式晶片間電性連接， 不會產生以往銲線交錯而短路之問題。在一較佳實施例 中’ 一鲜線542係可電性連接該第二銲墊232與對應之 接札211，古無跨越該些塗晝導線25〇的必要，則能以 另一塗畫導線取代該銲線542。在另一變化實施例中， 亦可和用該些塗晝導線2s〇順著該第二可塗畫斜坡244 以連接該第二録替232與對應之接指2ιι。也就是說， 在本實施例中，可藉由該跨接銲線54ι與該塗畫導線 組α依照實際產品需求而選擇與變更適當的電性連 接方式，以達到最佳的電性連接品質。 以上所述，僅是本發明的較佳實施例而已並非對本 p作任何形式上的限制’㈣本發明已以較佳實施例 露如上’然而並非用以限定本發明任何熟悉本項技 者’在不脫離本發明之技術範圍内，所作的任何簡單 18 201112384 修改 内。 等效性變化與修_ 均仍屬於本發明的技術範圍 【圖式簡單說明】 第1圖：為習知的一種有綠 線弧之多晶片堆疊構造之截面 示意圖。 第2圖：依據本發明之第一且触 具體實施例的一種無線弧之 多晶片堆疊構造之截面示意圖。S S 15 201112384 contains more chips. Referring to FIG. 5 , at least one third chip 38 可 may be further disposed on the second active surface 23 1 of the second wafer 230 but not completely covering the second active surface 231 to reveal the a second pad 232 having a third active surface 381 away from the substrate 310 and a plurality of third pads 382 on the third active surface 381, and the pair of thermal insulating films 240 Further extending to the third active surface 381' of the third wafer 380 and providing another paintable slope 341 between the third active surface 381 and the second active surface 231, and the coated wires 250 are The other solderable lands 341 are connected along the other solderable lands 341 to connect the second solder pads 232 and the third solder pads 382. In this embodiment, the first wafer 220, the second wafer 23, and the third wafer 38 may be stepped. In a variant embodiment, the number of stacks of the third wafers 380 can be increased according to product requirements to increase overall operational performance. Furthermore, the substrate 310 can be appropriately sized according to the number of stacks of the third wafers 38 To provide enough packaging space. Since the painted wires 25 are affixed to the thermal insulating film 24 at the time, without any hanging line arc, even if the number of stacked third chips is increased according to the demand, It can also completely eliminate the height of the conventional recording line after the previous wire-making process, in order to effectively reduce the overall package height. In accordance with a third embodiment of the present invention, another multi-wafer stack configuration is illustrated in cross-section of Figure 6. The multi-wafer stack structure 400 mainly includes a substrate 21A, a first wafer 220, a second wafer 230, a thermal insulating film 24A, and a plurality of coated wires 25A. — 16 201112384 The same main elements as those in the first embodiment will be denoted by the same reference numerals and will not be described in detail. Referring to FIG. 6 , at least one chip set 49 is further disposed on the second active surface 231 of the second wafer 230 and partially pressed to the heat resistant insulating film 240, and the first The wafer 22 and the second wafer 230 are stacked in a zigzag. In detail, the chip set 490 is composed of a plurality of B-chips, wherein the wafers, the first wafer 220 and the second wafer 230 can be substantially identical, and the semiconductor wafers of the same size and work can be used. . The wafer stacking of the wafer set 490 can be the same as that of the first wafer 220 and the second wafer 230. In this embodiment, the heat-resistant insulating film 240 is bendably attached to the active faces of the wafers, and the electrical connections between the wafers are completed by the painted wires 250. Further, the chip set 49 can be bonded to the second active surface 231 of the second wafer 230 by an adhesive layer 491. In addition, a plurality of bonding wires φ 441 and 442 formed by a plurality of wires may be further included, wherein the bonding wires 441 are electrically connected to the plurality of fingers 21 of the first bonding pads 222 and the substrate 210, and the bonding wires 442 The pads of the wafer set 490 and the fingers 211 are electrically connected. Therefore, the heat-resistant insulating film 240 does not have to be extended to the substrate 210, and the coating length of the painted wires 250 can be reduced. The heat-resistant insulating film used for each wafer group can have the same length, and each wafer group After the wafer is stacked and the wire is drawn, the substrate is electrically connected to the substrate 210. In addition, the slope of the heat-resistant insulating film 240 can be prevented from being changed due to the influence of stress between the wafer and the substrate. 17 201112384 In accordance with a fourth embodiment of the present invention, another multi-wafer stack configuration is illustrated in the schematic view of the wear surface of Figure 7. The multi-wafer stack structure 500 mainly includes a substrate 21, a first wafer 220, a second wafer 230, a pair of thermally insulating film 240, and a plurality of painted wires 250. The same elements as those in the first embodiment will be designated by the same reference numerals and will not be described in detail. Referring to FIG. 7 , the jumper wire 541 formed by at least one wire may be further connected to one of the first pads 222 and the corresponding first pad 232, and the top view is Some of the painted wires 25 are electrically insulated and have a short circuit problem with wire sweep. Therefore, it is possible to provide a double (multiple) layer type inter-wafer electrical connection without causing the problem that the conventional bonding wires are staggered and short-circuited. In a preferred embodiment, a fresh line 542 can be electrically connected to the second bonding pad 232 and the corresponding receiving 211. If it is necessary to cross the coated wires 25, it can be painted with another The wire replaces the wire 542. In another variant embodiment, the second drawable ramp 244 can also be used in conjunction with the coated wire 2s to connect the second record 232 with the corresponding finger 2ι. That is to say, in this embodiment, the bridging wire 54 and the painted wire group α can be selected and changed according to actual product requirements to achieve an optimal electrical connection quality. . The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. (4) The present invention has been described above in terms of preferred embodiments, but is not intended to limit the invention to any skilled person. Any simple 18 201112384 modifications made without departing from the technical scope of the present invention. Equivalence change and repair are still within the technical scope of the present invention. [Simplified description of the drawings] Fig. 1 is a schematic cross-sectional view showing a conventional wafer stack structure having a green line arc. Figure 2 is a cross-sectional view showing a multi-wafer stack configuration of a wireless arc in accordance with a first and specific embodiment of the present invention.
第3圖：依據本發明之第一具體實施例的無線弧之多 片堆疊構造未封裝前之立體示意圖。 第4A至则：依據本發明之第—具體實施例的無線狐 之多晶片堆疊構造在製造過程中之元件截面示 意圖。 第5圖：依據本發明之第二具體 避貫施例的另一種無線狐 之多晶片堆疊構造之截面示意圖。 第6圖 依據本發明之第三具體實施例的另-種多晶片 堆疊構造之截面示意圖。 依據本發明之第四具體實施例的另一種多晶片 堆疊構造之立體示意圖。 【主要元件符號說明】 5 〇 金線筆 100 習知的多 晶片堆疊構造 110 基板 120 上晶片 121 主動面 130 下晶片 131 主動面 111接指 122 銲墊 132銲墊 19 201112384 1 5 3 獨立金球 151 銲線 152銲線 170封膠體 200無線弧之多晶片堆疊構造 210基板 211接指 222 第一銲墊 232 第二銲墊 243第二開孔 270封裝體 220 第一晶片 221第一主動面 230 第二晶片 231 第二主動面 240耐熱絕緣膠片 241 可塗畫斜坡 242第一開孔 244第二可塗晝斜坡 250塗晝導線 260填充材 300無線弧之多晶片堆疊構造 3 10基板 311接指 341 可塗畫斜坡 382 第三銲墊 380第三晶片 381第三主動面 400多晶片堆疊構造 441 銲線 442銲線 490 晶片組 491黏著層 500多晶片堆疊構造 541 跨接銲線 542銲線 20Fig. 3 is a perspective view showing the multi-chip stack structure of the wireless arc according to the first embodiment of the present invention before being packaged. 4A to 3: A cross-sectional view of an element in a manufacturing process of a multi-wafer stack configuration of a wireless fox according to a first embodiment of the present invention. Figure 5 is a cross-sectional view showing another multi-wafer stack configuration of a wireless fox in accordance with a second specific embodiment of the present invention. Figure 6 is a schematic cross-sectional view showing another multi-wafer stack configuration in accordance with a third embodiment of the present invention. Another perspective view of another multi-wafer stack configuration in accordance with a fourth embodiment of the present invention. [Main component symbol description] 5 线金线笔 100 Conventional multi-wafer stack structure 110 substrate 120 upper wafer 121 active surface 130 lower wafer 131 active surface 111 finger 122 solder pad 132 pad 19 201112384 1 5 3 independent golden ball 151 welding wire 152 welding wire 170 sealing body 200 wireless arc multi-chip stacking structure 210 substrate 211 finger 222 first bonding pad 232 second bonding pad 243 second opening 270 package 220 first wafer 221 first active surface 230 Second wafer 231 second active surface 240 heat-resistant insulating film 241 can be painted ramp 242 first opening 244 second coatable ramp 250 coated wire 260 filler 300 wireless arc multi-wafer stack structure 3 10 substrate 311 finger 341 can be painted ramp 382 third pad 380 third wafer 381 third active surface 400 multi-wafer stack structure 441 wire 442 wire bond 490 chip set 491 adhesive layer 500 multi-chip stack structure 541 jumper wire 542 bond wire 20