TW201445624A - A method for forming a MESA structure on a semiconductor substrate - Google Patents

Abstract

A method for forming a MESA structure on the semiconductor substrate. First, determine the layout of a plurality of predetermined split-lines on the semiconductor substrate for determining the predetermined cutting positions, wherein the predetermined split-lines are arranged to split the semiconductor substrate into a plurality of semiconductor chips. Next, determine a predetermined cutting depth, which is longer than the distance between the PN junction of the semiconductor substrate and the surface of that. Then, according to the predetermined cutting positions and the predetermined cutting depth, scribe the surface of the semiconductor substrate by a cutter, so as to form a plurality of grooves. Finally, polish the bottom of the grooves.

Description

Plateau structure forming method of semiconductor substrate

The present invention relates to a semiconductor structure, and more particularly to a method for forming a plateau structure of a semiconductor substrate.

At present, the high-altitude (MESA) structure of power semiconductor wafers is formed by a photomask process combined with low-temperature mixed acid etching. However, this mask process requires specific equipment and chemicals, which will lead to increased manufacturing costs and drug recovery. For example, the development and consumption of reticle, the consumption of photoresist and developer and fixer, the cost of subsequent photoresist removal process, and investment in yellow light equipment.

When a mixed acid is used for the deep etching of the plateau structure, a sufficient wafer area is planned due to the effect of the lateral etching of the mixed acid. Furthermore, since the mixed acid etching releases a large amount of heat, an intense etching reaction will result in extremely poor etching uniformity.

Therefore, the wafer design must relax the process width requirements to meet the actual process conditions, resulting in wafer miniaturization difficulties.

As shown in FIG. 1A and FIG. 1B, the single-groove glass passivated rectifier diode (GPP) design is taken as an example, and the mask width L1 is designed to be about 0.006 inches, that is, the opening of the trench. The width is about 6 mils, which is equivalent to about 152.4 micrometers, and the etch depth is about 120 microns to 130 microns.

However, the actually etched trench has an opening width L2 of about 22 mils (about 558.8 micrometers) and a trench depth of between about 118 micrometers and 141 micrometers. The width of the protective layer is designed to be as large as 24 mils (approximately 609.6 microns), excluding the 6 mil (about 152.4 micrometers) scribe line. If applied on a 50 mil wafer, the scribe line plus the protective layer is used for 30 mils, which is equivalent to 60%, and the actual working area is only 40% of the total wafer.

Therefore, how to effectively consider the cost and quality in the semiconductor manufacturing process and to make the semiconductor have good characteristics is an issue that the inventors of the present invention and those skilled in the related art are eager to improve.

In view of the above, the present invention provides a method for forming a plateau structure of a semiconductor substrate, comprising: determining a layout of a plurality of predetermined split lines on a surface of a semiconductor substrate, wherein the predetermined split lines are used to split the semiconductor substrate into a plurality of semiconductor wafers, and Determining a plurality of predetermined cutting positions according to the layout of the predetermined splitting lines, and then determining a predetermined cutting depth such that the predetermined cutting depth is greater than a distance between the semiconductor junction of the semiconductor substrate and the surface of the semiconductor substrate, and finally, according to the predetermined cutting positions And scheduled cutting depth The cutter cuts the surface of the semiconductor substrate to form a plurality of grooves, and polishes the bottoms of the grooves.

The semiconductor substrate of the present invention utilizes a predetermined split line layout of the predetermined semiconductor wafer to lay the trenches, and then repeatedly cuts the surface of the semiconductor substrate by a dicing blade to form a trench, so that the trench can produce a more precise opening width and depth. Here, the method of fabricating the trench is reduced by a yellow light process, and the accuracy of the opening and depth of the trench is improved. Wherein, the bottom of the trench is arc-shaped to slow down the electric field tip effect (also known as the positive angle effect or the electric field effect), so that the wafer can withstand higher voltage, and the semi-insulation can be omitted due to the increase in withstand voltage. Process of polycrystalline germanium (SIPOS).

Moreover, after the trench is formed on the semiconductor substrate, the bottom of the trench is microetched, so that a large amount of or/or high-strength acid solution is not required, and the tip effect of the electric field can be avoided after polishing the bottom of the trench, thereby improving the semiconductor. Features, reduced costs, and reduced contamination from chemicals handling acid solutions while protecting the environment.

The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art.

L1‧‧‧Width

L2‧‧‧Width

10‧‧‧Semiconductor substrate

101‧‧‧P ⁺ layer

102‧‧‧N-type layer

103‧‧‧N ⁺ layer

11‧‧‧Semiconductor wafer

12‧‧‧ trench

13‧‧‧Connected

14‧‧‧Connected

15‧‧‧ surface

110‧‧‧Local

L‧‧‧Predetermined split line

D‧‧‧During cutting depth

W‧‧‧ spacing

A-A’‧‧‧ hatching

Θ1‧‧‧ angle

Θ2‧‧‧ angle

S20‧‧‧ determines the layout of the plurality of predetermined split lines on the surface of the semiconductor substrate, the predetermined split line for splitting the semiconductor substrate into a plurality of semiconductor wafers

S21‧‧‧Determining the predetermined cut position according to the layout of the predetermined split line

S22‧‧‧determines a predetermined depth of cut such that the predetermined depth of cut is greater than the distance between the semiconductor junction of the semiconductor substrate and the surface of the semiconductor substrate

S23‧‧‧Cutting the surface of the semiconductor substrate with a cutter according to the predetermined cutting position and the predetermined cutting depth to form a plurality of grooves

S24‧‧‧ polishing the bottom of these grooves

Figure 1A is a schematic representation of a prior art plateau structure.

Fig. 1B is an enlarged view of a portion A of the plateau structure of Fig. 1A.

Fig. 2 is a plan view showing a semiconductor substrate according to an embodiment of the present invention.

Fig. 2A is an enlarged view of a portion 110 of the semiconductor substrate of Fig. 2.

Fig. 2B is a cross-sectional view taken along line AA' in Fig. 2A.

Fig. 3A is a schematic view showing the plateau structure of the semiconductor substrate of the first embodiment of the present invention.

Fig. 3B is a cross-sectional view taken along line AA' in Fig. 3A.

Fig. 4A is a schematic view showing the plateau structure of the semiconductor substrate of the second embodiment of the present invention.

Fig. 4B is a cross-sectional view taken along line AA' in Fig. 4A.

Fig. 5 is an enlarged view of a portion B in Fig. 4B.

Fig. 6 is a flow chart showing a method of forming a plateau structure of the semiconductor substrate of the present invention.

2 is a plan view of a semiconductor substrate according to an embodiment of the present invention; FIG. 2A is a partial enlarged view of the semiconductor substrate of the present invention; FIG. 2B is a cross-sectional view taken along line AA' of FIG. 2A; A flow chart of a method for forming a plateau structure of a semiconductor substrate of the invention.

Referring to FIG. 2, FIG. 2A and FIG. 6, first, the layout of the plurality of predetermined splitting lines L on the surface of the semiconductor substrate 10 is determined, and the plurality of predetermined splitting lines L may be alternately arranged in a staggered manner with each other. The predetermined split line L is preset as a portion where the semiconductor substrate 10 is split. Therefore, the semiconductor process is completed Thereafter, the semiconductor substrate 10 is split along the predetermined split lines L to form a plurality of semiconductor wafers 11 (step S20). In other words, the semiconductor wafer 11 can be formed by the semiconductor substrate 10 being split according to a predetermined split line L.

Here, the predetermined splitting line L is not limited to the layout in which the first splitting lines L are interlaced, and the angle at which the two predetermined splitting lines L are staggered may be any angle other than 180 degrees. Alternatively, the predetermined split line L may be staggered with respect to each other in two or more extension angles. Thereby, the semiconductor wafer 11 having a geometric shape such as a square, a diamond, a triangle, and a hexagon can be formed.

The plateau structure forming method of the embodiment of the present invention is applied to the semiconductor substrate 10 that has not been split into a plurality of semiconductor wafers 11. In one embodiment, the semiconductor substrate 10 can be a germanium wafer.

Referring to FIG. 2B, in the embodiment, the semiconductor substrate 10 is an N-type substrate, and the upper and lower surfaces thereof are respectively diffusion doped to form a P ⁺ -type layer 101 and an N ⁺ -type layer 103, and in the P ⁺ type. An N-type layer 102 is between the layer 101 and the N ⁺ -type layer 103. Here, the first semiconductor junction 13 is a heterojunction between the P ⁺ -type layer 101 and the N-type layer 103, and the second semiconductor junction 14 is a homojunction between the N-type layer 102 and the N ⁺ -type layer 103. However, the semiconductor substrate 10 of the embodiment of the present invention is not limited to have a heterojunction and a homojunction, and the composition of the semiconductor substrate 10 and its junction can be adjusted according to requirements. For example, the semiconductor substrate 10 may have only one heterojunction (ie, a PN junction).

Next, after step S20, a plurality of predetermined cutting positions are determined in accordance with the layout of the predetermined split line L (step S21). That is, after determining the predetermined split line L of the semiconductor substrate 10, each semiconductor crystal can be planned. The position and size of the sheet 11 and the position of the plateau structure of each semiconductor wafer 11 are determined accordingly. Based on the position of the plateau structure, the predetermined cutting position of the groove 12 can be determined. The positions of the two types of plateau structures will be described in the first and second embodiments, respectively.

After step S21, a predetermined cutting depth D is determined, which is greater than a distance between the first semiconductor junction 13 of the semiconductor substrate 10 and the surface 15 of the semiconductor substrate 10 (here, the surface of the P ⁺ -type layer 101) ( Step S22). Thereby, the groove 12 can be formed at a predetermined cutting position of the semiconductor substrate 10 in accordance with the predetermined cutting depth D (as shown in FIGS. 3B and 4B). Here, the predetermined cutting depth D is the depth of the groove 12 formed in the subsequent step.

Based on this, the semiconductor substrate 10 is formed by cutting the surface 15 of the semiconductor substrate 10 with a cutter according to a predetermined cutting position and a predetermined cutting depth D, that is, forming a plurality of grooves 12 (step S23), thereby forming a plateau structure of the semiconductor substrate 10. Here, the trench 12 is formed to pass through the upper P ⁺ -type layer 101 and the first semiconductor junction 13 , and the bottom of the trench 12 is located in the N-type layer 102 . In an embodiment, the bottom of the trench 12 can be located in the N ⁺ -type layer 103.

The bottom of the trench 12 is polished after step S23 so that the inner wall of the trench 12 is uniformly smooth and the bottom of the trench 12 is arcuate (step S24). The circular arc-shaped groove 12 can alleviate the electric field tip effect (also called the positive angle effect or the electric field effect), and can increase the withstand voltage of the semiconductor wafer 11.

In some implementations, the tool can be a diamond knife or a wheel cutter. The diamond knife has a circular body, and the opposite surfaces of the circular body are provided with a plurality of diamond particles adjacent to the outer circumference and the cutting surface. The wheel cutter has a round blade and The circular blade has a rollable axis, and the circumference of the circular blade is a sharp cutting portion. Since diamond knives and/or wheel knives are well known to those skilled in the art, no further details are provided herein.

A tool according to an embodiment of the invention refers to a tip having a small radius. The surface 15 of the semiconductor substrate 10 (ie, the specific block of the semiconductor substrate 10 is repeatedly polished) is repeatedly cut at the tip of the tool corresponding to each predetermined cutting position, and the upper and lower narrow grooves 12 (ie, the trench 12) can be formed. The width of the bottom is smaller than the width of the opening of the trench 12).

In some embodiments, the plurality of semiconductor wafers 11 may be a regular hexagonal wafer or a square wafer, wherein the semiconductor substrate 10 determines a plurality of predetermined cutting positions according to a layout of the predetermined splitting line L, and the semiconductor wafer 11 is determined accordingly. Plateau structure location.

Fig. 3A is a schematic view showing the plateau structure of the semiconductor substrate of the first embodiment of the present invention. Fig. 3B is a cross-sectional view taken along line AA' in Fig. 3A.

Please refer to FIG. 3A for an example of a double trench glass passivated rectifier diode (GPP). Each of the semiconductor wafers 11 has two trenches 12, and the trenches 12 have a spacing W between the predetermined splitting lines L of the two ends, respectively. The predetermined depth of cut D is about 120 microns to 130 microns (i.e., the depth required for the trenches of GPP).

Therefore, in the foregoing steps S21 and S22, the cutting position of the cutter is a distance from the predetermined splitting line L to the distance W, and the cutting depth of the cutter is about 120 μm to 130 μm.

In some implementations, the predetermined cutting depth D can be 120. Micron to 150 microns.

Referring to Figure 3B, each semiconductor wafer 11 has two predetermined cutting locations. Here, the tool cuts the opening of the trench 12 on the surface 15 of the semiconductor substrate 10 according to the predetermined cutting position, and repeats the cutting from the surface 15 of the semiconductor substrate 10 toward the bottom of the semiconductor substrate 10 according to the predetermined cutting depth D. The groove 12 is ground.

In some embodiments, the opening width of the trench 12 can be from 0.005 inches to 0.01 inches (5 mils to 10 mils).

Accordingly, the semiconductor substrate 10 is formed by cutting the surface 15 of the semiconductor substrate 10 by the cutter to form the plurality of trenches 12, thereby forming the plateau structure of the semiconductor substrate 10. Among them, the groove 12 has a circular arc shape, and the groove 12 can be polished to make the inner wall of the groove 12 evenly smooth.

Fig. 4A is a schematic view showing the plateau structure of the semiconductor substrate of the second embodiment of the present invention. Fig. 4B is a cross-sectional view taken along line AA' in Fig. 4A. Here, the first embodiment is different from the second embodiment in that the trench 12 of the semiconductor wafer 11 of the single-groove GPP is located on the predetermined split line L.

Referring to FIG. 4A, first, a predetermined split line L is determined on the surface of the semiconductor substrate 10, and a predetermined cutting position is determined on each semiconductor wafer 11. Here, the predetermined cutting depth D is about 120 micrometers to 130 micrometers (that is, the depth required for the trench of the GPP).

Therefore, the cutting position of the cutter can be set on the predetermined split line L, and the cutting depth of the cutter can be set to be about 120 to 130 μm.

In some implementations, the predetermined cutting depth D can be 120. Micron to 150 microns.

Referring to FIG. 4B, each semiconductor wafer 11 has two predetermined cutting positions, and each predetermined cutting position is located on a predetermined split line L.

Here, the tool is repeatedly cut from the predetermined split line L of the surface 15 of the semiconductor substrate 10 toward the bottom of the semiconductor substrate 10, and the width of the opening of the equal groove 12 is generated on both sides of the predetermined split line L. And the groove 12 is ground.

The trench 12 has a circular arc shape, and has a predetermined cutting depth D from the surface 15 of the semiconductor substrate 10 to the bottom of the trench 12, so that the bottom of the trench 12 is located on the predetermined split line L.

In some embodiments, the opening width of the trench 12 can be from 0.005 inches to 0.01 inches (5 mils to 10 mils). Wherein, the width of the bottom of the trench 12 is smaller than the width of the opening.

Accordingly, the semiconductor substrate 10 is formed by cutting the surface 15 of the semiconductor substrate 10 by the cutter to form the plurality of trenches 12, thereby forming the plateau structure of the semiconductor substrate 10. Among them, the groove 12 has a circular arc shape, and the groove 12 can be polished to make the inner wall of the groove 12 evenly smooth.

In some embodiments, the polishing step of the foregoing step S24 can be implemented via an etching step. Also, after polishing the trench 12, there may be a cleaning step. Here, the polishing trench 12 has a circular arc shape at the bottom of the trench 12, and the inner wall of the trench 12 is uniformly smoothed, thereby reducing the electric field tip effect (also referred to as a positive angle effect or an electric field effect), thereby improving The withstand voltage of the semiconductor wafer 11.

In some implementations, the polishing trench 12 can be wet etched By way of example, the semiconductor substrate 10 having the dicing trench 12 is placed in an acid solution, and the semiconductor substrate 10 is immersed by an acid solution for a short time (for example, about 2 minutes to 3 minutes) so that the acid solution etches the trenches 12 While polishing the groove 12.

In some implementations, the polishing trenches 12 can be implemented in a dry etch manner such that the semiconductor substrate 10 exhibits a Gaussian distribution from the trenches 12 to the surface 15 by ion collision. Among them, dry etching can be carried out by means of plasma or vapor releasing ions.

Here, since wet etching or/and dry etching is well known to those skilled in the art, no further details are provided herein.

In some embodiments, after the trench 12 is formed on the semiconductor substrate 10, the semiconductor substrate 10 is cleaned, the glass frit is filled in the trench 12, and the glass is sintered to form an insulating glass layer on the edge of each semiconductor wafer 11. . Finally, metal contacts are formed by surface plating, and the semiconductor substrate 10 is split into a plurality of semiconductor wafers 11. Then, the packaging process of the semiconductor wafer 11 can be performed.

Herein, since the formation of the insulating glass layer, the formation of metal contacts, the splitting, and the packaging process of the semiconductor wafer 11 are well known to those skilled in the art, no further details are provided herein.

In some embodiments, as shown in FIG. 5, since the trench 12 has a suitable opening and depth (the trench created by repeatedly etching the surface of the semiconductor substrate by the dicing blade has a more precise opening width and Depth), and the inner wall is even and smooth and the bottom is arc-shaped, thus reducing the electric field tip effect (also known as the positive angle effect or the electric field effect). In other words, compared to The positive angle θ1 of the groove which is conventionally manufactured (as shown in Fig. 1B) has a small positive angle θ2 of the groove 12 of the present invention. Therefore, the semiconductor wafer 11 can withstand a relatively high voltage, so that a semi-insulating polysilicon (SIPOS) process can be omitted.

In some embodiments, the semiconductor substrate 10 may be germanium, germanium or gallium arsenide or the like; or the semiconductor substrate 10 may be other suitable elementary semiconductor materials such as tantalum carbide, indium arsenide, indium phosphide. , or suitable alloy semiconductor materials, etc.

In some embodiments, the semiconductor substrate 10 may have sapphire, gallium phosphide (GaP), gallium arsenide (GaAsP), zinc selenide relative to one side of the trench 12 (ie, the bottom of the semiconductor substrate). (ZnSe), zinc sulfide (ZnS), zinc selenide sulfide (ZnSSe) or tantalum carbide (SiC), etc., but the invention is not limited thereto, and a suitable substrate can be selected according to the requirements of product specifications and process conditions.

The plateau structure of the semiconductor substrate of the present invention is applied to the first embodiment and the second embodiment for the purpose of description. However, the present invention is not limited thereto, and the method for forming the plateau structure of the semiconductor substrate of the present invention can also be implemented for manufacturing the insulated gate. Insulated Gate Bipolar Transistor (IGBT) and transient suppression diode (also known as clamp-type diode) (Transient-Voltage-Suppression (TVS)) and other semiconductor processes.

The semiconductor substrate of the present invention utilizes a predetermined split line of a predetermined splitting semiconductor wafer to lay out the groove, and then the surface of the semiconductor substrate is repeatedly cut by the cutter to form a groove, so that the groove can produce a more precise depth and opening width. Here, compared to the traditional method of manufacturing the groove Reduces a yellow light process and increases the accuracy of the opening and depth of the trench. Wherein, the bottom of the trench is arc-shaped to slow down the electric field tip effect (also known as the positive angle effect or the electric field effect), so that the wafer can withstand higher voltage, and the semi-insulation can be omitted due to the increase in withstand voltage. Process of polycrystalline germanium (SIPOS).

Moreover, after the trench is formed on the semiconductor substrate, the bottom of the trench is microetched, so that a large amount of or/or high-strength acid solution is not required, and the tip effect of the electric field can be avoided after polishing the bottom of the trench, thereby improving the semiconductor. Features, reduced costs, and reduced contamination from chemicals handling acid solutions while protecting the environment.

Although the technical content of the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and any modifications and refinements made by those skilled in the art without departing from the spirit of the present invention are encompassed by the present invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

S20‧‧‧ determines the layout of the plurality of predetermined split lines on the surface of the semiconductor substrate, the predetermined split line for splitting the semiconductor substrate into a plurality of semiconductor wafers

S21‧‧‧Determining the predetermined cut position according to the layout of the predetermined split line

S22‧‧‧determines a predetermined depth of cut such that the predetermined depth of cut is greater than the distance between the semiconductor junction of the semiconductor substrate and the surface of the semiconductor substrate

S23‧‧‧Cutting the surface of the semiconductor substrate with a cutter according to the predetermined cutting position and the predetermined cutting depth to form a plurality of grooves

S24‧‧‧ polishing the bottom of these grooves

Claims (10)

A method for forming a plateau structure of a semiconductor substrate, comprising: determining a layout of a plurality of predetermined split lines on a surface of a semiconductor substrate, the predetermined split lines for splitting the semiconductor substrate into a plurality of semiconductor wafers; The layout of the line determines a plurality of predetermined cutting positions; determining a predetermined cutting depth such that the predetermined cutting depth is greater than a distance between a semiconductor junction of the semiconductor substrate and the surface of the semiconductor substrate; and according to the predetermined cutting positions and the predetermined Cutting the depth, cutting the surface of the semiconductor substrate with a cutter to form a plurality of grooves; and polishing the bottoms of the grooves. The method for forming a plateau structure of a semiconductor substrate according to claim 1, wherein the tool forms the trenches by repeatedly cutting the surface of the semiconductor substrate corresponding to each of the predetermined cutting positions. The method for forming a plateau structure of a semiconductor substrate according to claim 1, wherein each of the plurality of trenches has an opening width of 0.005 inches to 0.01 inches. The method for forming a plateau structure of a semiconductor substrate according to claim 1, wherein the predetermined cutting depth is from 120 μm to 150 μm. The method for forming a plateau structure of a semiconductor substrate according to claim 1, wherein a width of a bottom portion of the trenches is smaller than a width of the opening. a method for forming a plateau structure of a semiconductor substrate according to claim 1, The polishing of the bottom of the trench comprises: an etching step. The method for forming a plateau structure of a semiconductor substrate according to claim 1 or 6, further comprising: a cleaning step. The method for forming a plateau structure of a semiconductor substrate according to claim 1, wherein the tool is one of a diamond knife and a round knife. A method of forming a plateau structure of a semiconductor substrate according to claim 1, wherein each of the plurality of semiconductor wafers has two of the predetermined cutting positions. A method of forming a plateau structure of a semiconductor substrate according to claim 1, wherein each of the predetermined cutting positions is located on one of the predetermined split lines.