TW201712472A - Solid-state memory device with plurality of memory devices - Google Patents

Abstract

A solid-state memory device has memory devices and memory sticks. Each memory stick is coupled to a subset of the memory devices. A controller provides parallel access to the memory devices through the memory sticks to provide a virtualized memory device and to present to a host a single non-volatile storage unit with a total capacity based on capacities of the memory devices. The controller operates according to a memory mapping that map memory requests from the host to the memory devices. The memory devices, memory sticks, and the controller can be disposed within a rack unit housing that is shaped and sized to fit a data-center rack or cabinet. One or more wireless interfaces can connect the controller to a memory stick and connect a memory device to a memory stick for wireless communications of instructions and data within the solid-state memory device.

Description

Solid state memory device with a plurality of memory devices

The present invention relates to electronic devices, and more particularly to electronic memory devices.

The demand for computer memory has steadily increased. Today's hard drives have many problems. Moving parts (for example, rotating disks) can make the hard drive unreliable. Heat generation and noise are also a problem. Solid state hard drives have been developed, but many of these solid state hard drives lack the low cost capability to effectively replace hard drives. In addition, some known techniques for organizing smaller storage devices are still inefficient or often have data loss events.

According to an aspect of the present invention, a solid state memory device includes: a rack unit housing, the rack unit housing is shaped and designed to be suitable for a data center rack or cabinet; a plurality of memory devices, a plurality of memories The device is disposed in the rack unit housing; and a plurality of memory sticks, and the plurality of memory sticks are disposed in the rack unit housing. Each memory stick of the plurality of memory sticks is coupled to a memory device of a subset of the plurality of memory devices. The solid state memory device further includes a controller configured to access the plurality of memory devices in parallel through the plurality of memory sticks to access the plurality of memory devices as the virtual memory device, and And presented to the host as a single non-volatile storage unit having a total capacity based on the capacity of the plurality of memory devices. The controller is further configured to operate in accordance with the memory map to map memory requests from the host to the plurality of memory devices. The memory map defines a memory area for accessing each of the memory sticks of the plurality of memory sticks. The memory area is mapped to a plurality of host areas defined by the host. Each host area of the plurality of host areas is mapped to a different memory device of each memory stick. Each memory region of a plurality of memory regions is mapped to a different memory stick for writing and reading a plurality of memory regions in parallel to increase the speed of memory access.

The controller can include a wireless interface, and the at least one memory stick of the plurality of memory sticks can include a wireless interface. The wireless interface of the controller and the wireless interface of the at least one memory stick are configurable to wirelessly communicate commands and data between the controller and the at least one memory stick.

The at least one memory stick of the plurality of memory sticks can include a wireless interface, and the at least one memory device of the plurality of memory devices can include a wireless interface. The wireless interface of the at least one memory stick and the wireless interface of the at least one memory device are configurable to wirelessly communicate commands and data between the at least one memory stick and the at least one memory device.

The solid state memory device can further include a power supply disposed within the rack unit housing for providing power to the solid state memory device.

Each memory device of the plurality of memory devices can include a solid state hard disk.

Each of the memory sticks of the plurality of memory sticks may be a memory card, and each memory device of the plurality of memory devices may include a memory card.

Each memory device of the subset of memory devices can be hot swapped from each memory stick.

The solid state memory device can further include a slidable tray that supports a plurality of memory devices and a plurality of memory sticks within the frame unit housing. The slidable tray is configured to slide into the rack unit housing and slide out of the rack unit housing to inspect and thermally insert at least one of the plurality of memory devices and the plurality of memory sticks.

A data center rack or cabinet can include the plurality of solid state memory devices described above.

In accordance with another aspect of the invention, a solid state memory device includes a plurality of memory devices and a plurality of memory sticks. Each memory stick of the plurality of memory sticks is coupled to a memory device of a subset of the plurality of memory devices. The solid state memory device further includes a controller configured to access a plurality of memory devices in parallel through the plurality of memory sticks to access the plurality of memory devices as virtual memory devices, and present to the host as having a basis A single non-volatile storage unit of the total capacity of the plurality of memory devices. The controller includes a wireless interface, and the at least one memory stick of the plurality of memory sticks includes a wireless interface. The wireless interface of the controller and the wireless interface of the at least one memory stick are configured to wirelessly communicate commands and data between the controller and the at least one memory stick. At least one memory device of the plurality of memory devices includes a wireless interface. The wireless interface of at least one memory stick is configured with the wireless interface of at least one memory device Wireless communication instructions and data between at least one memory stick and at least one memory device.

The controller can be further configured to operate in accordance with the memory map to map memory requests from the host to the plurality of memory devices. The memory map can define a memory area for accessing each of the memory sticks of the plurality of memory sticks. The memory area can be mapped to a plurality of host areas defined by the host. Each host area of the plurality of host areas can be mapped to a different memory device associated with each memory stick. Each memory region of a plurality of memory regions can be mapped to different memory sticks for writing and reading a plurality of memory regions in parallel to increase the speed of memory access.

Each of the memory sticks of the plurality of memory sticks may include a wireless interface such that all of the memory sticks are configured to wirelessly communicate commands and data to the controller.

Each memory device of the plurality of memory devices includes a wireless interface such that all of the memory devices are configured to wirelessly communicate commands and data to a plurality of memory sticks.

Each memory device of the plurality of memory devices can include a solid state hard disk.

Each of the memory sticks of the plurality of memory sticks may be a memory card, and each memory device of the plurality of memory devices may include a memory card.

Each memory device of the subset of memory devices can be hot swapped from each memory stick.

The solid state memory device can further include a rack unit housing that is shaped and sized to fit a data center rack or cabinet. A plurality of memory devices, a plurality of memory sticks, and a controller may be disposed in the frame unit housing.

The solid state memory device can further include a slidable tray that supports a plurality of memory devices and a plurality of memory sticks within the frame unit housing. The slidable tray is configured to slide into the rack unit housing and slide out of the rack unit housing to inspect and thermally insert at least one of the plurality of memory devices and the plurality of memory sticks.

10‧‧‧ memory device

12‧‧‧ housing

14‧‧‧Connector

16‧‧‧Opening

18‧‧‧ memory card

19‧‧‧ indicator

20‧‧‧ solid state memory device

22‧‧‧ housing

24‧‧‧USB cable

42‧‧‧ physical connector

44‧‧‧Physical interface

46‧‧‧Interface controller

48‧‧‧Sequence peripheral interface

50‧‧‧ memory card connector

52‧‧‧Controller core

54‧‧‧Instruction Memory

56‧‧‧ working memory controller

58‧‧‧ working memory

60‧‧‧USB host device

62‧‧‧ Field Programmable Gate Array (FPGA)

64‧‧‧Printed circuit board (PCB)

70‧‧‧USB listing information

72‧‧‧Command Mapping

74‧‧‧File Routing Table

80‧‧‧File System

82‧‧‧Files

84‧‧‧File handle

86‧‧‧File handle pair

90‧‧‧Substrate

92‧‧‧Connector Department

94‧‧‧Flexible cable

96‧‧‧Band cable

100‧‧‧ solid state memory device

102‧‧‧ housing

104‧‧‧Controller board

106‧‧‧ memory card stick

108‧‧‧ SATA埠

110‧‧‧USB埠

112‧‧‧ memory card

120‧‧‧SATA controller

122‧‧‧Power supply埠

124‧‧‧Power conditioner

126‧‧‧SPI

128‧‧‧SPI controller

130‧‧‧Memory Stick Connector

140‧‧‧PCB

142‧‧‧ physical connector

144‧‧‧buffer

150‧‧‧ memory area

152‧‧‧Width

154‧‧‧Host area

160‧‧‧Rack unit

162‧‧‧ solid state memory device

164‧‧‧ memory card stick

166‧‧‧ housing

168‧‧‧Power supply

169‧‧‧ cover

180‧‧‧Data Center Rack or Cabinet

190‧‧‧Data Center Rack or Cabinet

192‧‧‧ solid state memory device

200‧‧‧ controller

202‧‧‧ Memory Stick

204‧‧‧ memory device

206‧‧‧Control logic and memory

208‧‧‧Wireless interface

210‧‧‧Host wireless connection

212‧‧‧Wireless interface

214‧‧‧ Controller Wireless Link

216‧‧‧buffer

218‧‧‧Wireless interface

220‧‧‧Memory Wireless Link

222‧‧‧ memory

250‧‧‧Rack unit

252‧‧‧Tray

254‧‧‧rail

256‧‧‧Sliding guide rail in the middle

258‧‧‧Base rail

270‧‧‧ components

The drawings illustrate embodiments of the invention by way of example only.

Figure 1 is a perspective view of a solid state memory device, in accordance with some embodiments.

Figure 2 is a perspective view of a solid state memory device, in accordance with other embodiments.

Figure 3 is a block diagram of a solid state memory device.

Figure 4 is a block diagram of the components of the instruction memory.

Figure 5 is a block diagram of the file routing table and file system.

6a to 6b are schematic views of a solid state memory device, according to other embodiments.

Figure 7 is a perspective view of a solid state memory device, in accordance with additional embodiments.

Figure 8 is a block diagram of a solid state memory device such as shown in Figure 7.

Figure 9 is an illustration of a memory card with a plurality of memory cards.

Figure 10 is a graphical representation of memory mapping.

Figure 11 is a perspective view of a rack unit, in accordance with an embodiment.

Figure 12 is a perspective view of a data center rack, in accordance with an embodiment.

Figure 13 is a perspective view of another data center rack, according to another embodiment.

Figure 14 is a block diagram of a solid state memory device, according to another embodiment.

Figure 15 is a perspective view of a rack unit, according to another embodiment.

Figure 16 is a side elevational view of a sliding rail arrangement, in accordance with an embodiment.

Figure 17 is a perspective view of the components of the rack unit, in accordance with an embodiment.

The present invention relates to a solid state memory device that allows a plurality of removable memory cards to emulate a universal serial bus (USB) mass storage device, a serial ATA (SATA) hard disk drive, or the like. Set. This provides the ability to store large amounts of data in a memory card library while maintaining the convenience and functionality of known storage devices.

FIG. 1 illustrates a solid state memory device 10. The memory device 10 includes a housing 12 having a connector 14, such as a USB Type A plug, that protrudes directly from the housing 12 to give the memory device 10 a portable USB memory stick. structure. The housing 12 additionally includes an aperture 16 that is aligned with a plurality of memory card connectors located within the housing 12 to permit insertion and removal of the plurality of removable memory cards 18. An indicator 19 (eg, a red and green bi-color light emitting diode (LED)) can be provided to indicate read/write access and/or failure. Although two apertures 16 are shown, any number of apertures 16 can be provided to receive any number of removable memory cards 18. The solid state memory device 10 is portable and can be plugged directly into any suitable USB host device, such as a computer.

FIG. 2 illustrates the solid state memory device 20. The features and aspects of other embodiments described herein can be used with the presently described embodiments, and reference to the description of similarly identified elements. The memory device 20 includes a housing 22 and a connector 14, such as a USB Type A plug, which is attached to the circuit board housed within the housing by a USB cable 24. The housing 22 additionally includes an aperture 16 that is aligned with a plurality of memory card connectors located within the housing 12 to permit insertion and removal of the plurality of removable memory cards 18. A status indicator (not shown) is also available. Although ten apertures 16 are shown, any number of apertures 16 can be provided to receive any number of removable memory cards 18. Solid state memory device 20 can be used As a fixed or portable storage, the cable 24 allows the solid state memory device 20 to be plugged into any suitable USB host device, such as a computer.

The removable memory card 18 can be a Secure Digital (SD) card, a miniSD card, or a microSD card. The storage capacity of such a card can be any available size, such as 16 GB, 64 GB, 128 GB, 1 TB, etc., as long as the number of cards and the selected file system support such capacity.

Figure 3 is a block diagram of a solid state memory device, such as solid state memory devices 10, 20 of Figures 1 and 2, and devices partially depicted in Figures 6a through 6b. The components of the memory device shown in FIG. 3 are examples, and the functions discussed below may be implemented with other kinds of components, fewer generalized components, or a greater number of more specialized components.

The solid state memory device includes a physical connector 42, a physical interface 44 coupled to the physical connector 42, an interface controller 46 coupled to the physical interface 44, and a serial peripheral interface (SPI) 48. A plurality of memory card connectors 50 are connected to the SPI 48. Each memory card connector 50 is configured to receive a removable memory card 18. The memory device additionally includes a controller core 52 coupled between the interface controller 46 and the serial peripheral interface 48 to manage access to a mass storage type of the total capacity of the memory card 18. The memory device can additionally include a command memory 54 coupled to the controller core 52 and a working memory control coupled to the controller core 52. The device 56, and the working memory 58 connected to the working memory controller 56.

In some embodiments, the physical connector 42 is a universal serial bus (USB) connector, including a plug of USB Type A, connectable to a USB host device 60, such as a computer. Alternatively, the USB connector 14 can include another USB connector or a connector made according to another standard.

In some embodiments, the physical interface 44 is a USB physical interface 44 configured to translate the USB controller 46 (the USB controller 46 operates in 8-bit packets) and the two USB D+ and D-signals at the USB connector 42. A digital logic signal between lines. The USB physical interface 44 may include a high speed USB transceiver chip, such as those available under the designated USB 3319 of Microchip Technology, Chandler, Arizona.

In some embodiments, the interface controller 46 is a USB controller 46 configured to transfer data, read/write commands, and handshaking and flow control between the USB physical interface 44 and the controller core 52. communication. The USB controller 46 operates in an 8-bit packet.

The USB connector 14, the physical interface 44, and the controller 46 can be implemented in accordance with the USB 2.0 specification, the USB 3.0 specification, or the like.

The SPI 48 provides communication between the controller core 52 and a plurality of memory cards 18. In one example, the SPI 48 is configured to translate 32-bit read and write operations from controller core 52 into Recall the 1-bit or 4-bit command and data cycle of card 18. The SPI 48 can also be connected to the indicator 19 (Fig. 1), and the control indicator 19 illuminates according to read/write access and/or fault conditions.

The connector 50 provides a physical connection to the removable memory card 18. The connector 50 can be an off-the-shelf item that allows for physical removal and replacement of the removable memory card 18. However, in some embodiments, the removable memory card 18 can be snapped in place, such as by the shape of the housing or otherwise, to physically prevent removal of the memory card 18.

The controller core 52 is configured to present the removable memory card 18 to the host 60 as a single non-volatile storage unit having a total capacity substantially equal to the sum of the individual capacities of the removable memory card 18. In some embodiments, controller core 52 operates on an input 8-bit packet received from USB controller 46 and also provides an output 8-bit packet to USB controller 46 for transmission to host 60. Controller core 52 is configured to decode and respond to packets received from host 60 and to communicate data between host 60 and a plurality of removable memory cards 18. Thus, controller core 52 can be configured to operate a plurality of removable memory cards 18 in accordance with a USB mass storage class device protocol, and can thus be implemented in response to when host 60 is connected to a USB mass storage level device. Any USB status / command / request packet. In other embodiments, such as the implementation of SATA, controller core 52 operates on packets of different sizes or other data structures.

Controller core 52 may be further configured to use working memory 58 as a buffer for communicating data between host 60 and a plurality of removable memory cards 18. Controller core 52 can be implemented as a programmable state machine, a fixed logic structure, or a combination of these. Controller core 52 is configurable to operate on 32 bit logic.

The instruction memory 54 stores USB enumeration information (USB enumeration information is a command map for commands that can be issued by the host 60 and responded by the controller core 52) and one or more for the plurality of removable memory cards 18. File routing tables. The instruction memory 54 may additionally include a scratch pad memory for use by the controller core 52. The command map can be configured with standard storage access commands that can be requested by host 60.

Interface controller 46, controller core 52, instruction memory 54, and working memory controller 56 may be implemented with Field Programmable Gate Array (FPGA) 62 (eg, Spartan 6 from Xilinx Corporation), or implemented as micro-processable The code of the program executed on the device.

The working memory controller 56 allows the controller core 52 to access the working memory 58, which is used by the controller core 52 as a buffer for data communicated between the host 60 and the plurality of removable memory cards 18. . In this example, working memory 58 includes a 16-bit DDR2 RAM, and working memory controller 56 is configured to translate 32-bit read and write requests from controller core 52 into working memory 58. 16-bit data, address, refresh, and control cycles.

In addition to the selective exclusion of the physical connector 42, in some embodiments, all of the components of the solid state memory device can be disposed in a multilayer printed circuit board (PCB) 64 that is comprised of a housing (eg, The housings 12, 22) of Figures 1 to 2 are surrounded. When the solid state memory device 10 has a USB key shape, the physical connector 42 can also be disposed on the same PCB 64 as shown in FIG. In other embodiments (Figs. 2 and 6b), the physical connector 42 can be cabled to the PCB 64 to provide a desktop form factor.

As shown in FIG. 4, in some embodiments, the instruction memory 54 stores USB enumeration information 70. The USB enumeration information 70 includes device descriptors, configuration descriptors, interface descriptors, and any further information required by the host 60 to perform a USB enumeration sequence.

Instruction memory 54 may additionally store command map 72. The command map 72 maps commands (e.g., USB or ATA commands) that are expected to be issued by the host 60 to commands (e.g., ATA commands) that are compatible with the file system used on the memory card 18.

Instruction memory 54 may additionally store file routing table 74.

As shown in Figure 5, each memory card 18 operates under its own dedicated file system 80. In some embodiments, the file system is FAT32. In other embodiments, other file systems may be used, such as NTFS, exFAT, and the like. In some embodiments, each memory card 18 has its own separate file system and, if removed, can be accessed individually. File file of file 82 in a given memory card 18 The file handle is unique, but this is not necessarily the case when two or more memory cards 18 are considered.

The file routing table 74 stores information about the memory card 18 and allows the memory card 18 to be presented to the host 60 as a single, large storage capacity having a total capacity equal to the aggregate capacity of the memory card 18. This can be accomplished, for example, by the file routing table 74 storing a unique set of host-oriented file handles 84 (the file handles 84 are mapped to the unique capacity of the upper group) and the files of the group file handles in the file system 80. The handle is on 86. The set of unique file handles 84 are themselves configured to be followed by a file system (e.g., FAT32 or the like), and the host 60 views the file handles 84 as a single large capacity. Thus, when accessing a particular file, host 60 uses file handles 84 in the group, and such host-oriented file handles are translated into the set of file handle pairs 86 and capacity for accessing the correct memory card. 18 with the correct file on the memory card 18.

The file routing table 74 can be configured to display the host 60 as a table of contents. However, the file routing table 74 replaces the structural elements of the table of contents (e.g., starting cluster, file size, etc.) with a unique capacity and file handle pair 86 (a file in the unique identification memory card 18).

The file handle can be a file name, a file name and an extension, or other identifier local to the file system. The host-to-file handle 84 (which may occur when two or more files 82 of different memory cards 18 have the same file name) can be avoided by adding a digital suffix or similar to the host-oriented file. Handle 84.

Moreover, in some embodiments, the logic of the file routing table 74 is limited to completely storing a given file in a memory card 18. To accomplish this, the file routing table 74 or another table associated therewith can maintain a value representative of the remaining storage capacity of the memory card 18. Prior to writing the new file, controller core 52 may examine file routing table 74 to identify each memory card 18 that has sufficient remaining space to store the entire file. Controller core 52 then selects a memory card 18 that individually has sufficient space to store the file. The file does not allow for the splicing of multiple memory cards 18, which may help reduce the likelihood of data loss found in some types of conventional hard disk drive technology, and may further allow hot swapping of the memory card 18 and The removal of the individual use of the memory card 18 is allowed.

When the file routing table 74 is not properly formatted into a directory table that is compatible with the file system of the total capacity seen by the host 60, the controller core 52 can be configured to generate a representation of the file routing table 74 to request access at the host 60. Can be compatible. Such representations can be generated on the fly and can be quickly buffered for later use. Thus, additional information (eg, available space on the memory card) can be stored in the file routing table 74, and the controller core 52 can be configured to provide such information to the host 60 in response to an access command. Alternatively, two or more file routing tables 74 are used, one such table 74 being modeled as a table of contents for the benefit host 60, and the remaining one or more such tables are stored on the memory card 18 and on the memory card 18. Additional information about the file (such as available space).

When the memory card 18 is removed, added, or plugged in, the controller core 52 can be configured to re-enumerate and scan the solid state storage device for verification The relationship between the file handles 84, 86 of the groups in the file routing table is verified, generated, or deleted. The scan includes the controller core 52 obtaining a directory for each file system 80, and if no such file handle exists, a unique set of host-oriented file handles 84 for each file of such a directory is generated. The scanning further includes removing the file handle from the host to group 84 for the capacity associated with the memory card 18 that has been removed. When the file on the newly inserted memory card 18 has the same file handle as the file handle on the existing memory card 18, the controller core 52 can be configured to increase the suffix to the file name (eg, "my file" With "my file(1)"), the host that generates such a file is oriented to the file handle. The actual file name of such a file has not changed.

In other embodiments, controller core 52 is configured to operate a plurality of removable memory cards 18 as redundant array of independent disks (RAID). RAID mirroring can be implemented to allow data redundancy to help prevent data loss. Any useful RAID level can be used (for example, RAID 1, RAID 2, etc.). In some RAID implementations, the memory card 18 is not pluggable because it can corrupt the RAID data. In other embodiments, controller core 52 is configured to provide data encryption to provide a highly secure and fault tolerant mass storage device.

Figures 6a through 6b illustrate other embodiments in which the solid state memory device is configured to provide a plurality of memory cards within a standard 3.5 inch hard disk housing. The features and aspects of other embodiments described herein can be used with the presently described embodiments, and reference to the description of similarly identified elements. A plurality of memory card connectors 50 are disposed on the substrate 90, such as a PCB. The substrate 90 includes a connector portion 92 for receiving a connection of the flexible cable 94 to electrically connect the memory card connector 50 to the flexible cable 94. A plurality of memory cards 18 can be coupled to the memory card connector 50.

A plurality of components of the substrate 90, the memory card connector 50, and the installed memory card 18 can be stacked and connected to the PCB 64. The PCB 64 has a physical interface 44, an interface controller 46, and a sequence peripheral interface as discussed in relation to FIG. 48. Controller core 52, instruction memory 54, working memory controller 56, and working memory 58. Each substrate 90 is connected to the PCB 64 via one or more flexible cables 94. In some embodiments, a solid state memory device is configured to replace a hard disk drive having a rotating disk. Thus, the physical interface 44 is a SATA physical interface 44, a USB 2.0 or USB 3.0 interface, or the like. Similarly, the interface controller 46 is a SATA controller, a USB 2.0 or USB 3.0 controller, or the like, and the physical connector 42 is a SATA connector, a USB connector, or is coupled to the PCB via a ribbon cable 96. Similar.

The substrate 90 carrying the stack of memory card 18 and controller PCB 64 can be configured to fit within a standard volume of 3.5 inch hard disk. The housing (not shown) can also be provided with standard fastening points to the computer housing.

The plurality of memory cards 18 can be of a removable type (eg, microSD), but need not be user removable. That is, the configuration of substrate 90 and PCB 64 can be permanent or semi-permanent, requiring special tools to access and remove memory card 18 or to prevent any memory card from being completely removed.

Figure 7 is a perspective view of another embodiment of the present invention. The solid state memory device 100 includes a housing 102, a controller board 104, and a plurality of memory card bars 106. The solid state memory device 100 is a hard disk drive replacement, and as far as the host device is concerned, the solid state memory device 100 operates as a conventional hard disk drive having a rotating disk. Features and aspects of other solid state memory devices described herein can be used with solid state memory device 100.

The housing 102 is sized and shaped to meet the 3.5 inch hard drive housing standard. The housing 102 can include mounting points, and/or hardware for internal mounting to a computer housing, to a rack server, or the like. In other embodiments, the housing 102 can vary in size and shape.

The controller board 104 is a multi-layer PCB that includes interface hardware for connection to a host device (e.g., a computer) and allows the host device to read and write access to a plurality of memory card sticks 106. In this embodiment, the controller board 104 includes a SATA port 108 and a USB port 110 for connection to one or more individual ports at the host device. In other embodiments, one of SATA port 108 and USB port 110 is provided. In still other embodiments, different types of defects are provided.

Each of the plurality of memory card bars 106 includes a plurality of memory cards 112. In some embodiments, as depicted, a plurality of memory cards 112 (eg, four) are mounted on one side of the memory card 106, and a plurality of other memory cards 112 (eg, four) are mounted on the memory card The opposite side of 106. This can increase the density of memory cards in space-constrained implementations.

The number of memory sticks 106 provided and the number of memory cards 112 provided to each memory card 106 are not particularly limited.

The memory card 112 can be a removable SD card, a miniSD card, a microSD card, or the like. The memory card 112 can be mounted in the memory card 106 in a removable or non-removable manner. That is, the memory card 112 can be of a removable type (eg, microSD), but need not be user removable, as discussed above. The memory card 106 can be removable from the controller board 104 or removed from the controller board 104. Removing the memory card 106 and/or the memory card 112 advantageously allows the failed memory card 106 and/or memory card 112 to be plugged out.

Figure 8 is a block diagram of a solid state memory device, such as solid state memory device 100 of Figure 7. The components of the memory device shown in Figure 8 are examples, and the functions discussed below may be implemented with other kinds of components, fewer generalized components, or a greater number of more specialized components. Like reference numerals designate similar elements, and the redundant description is omitted for clarity.

The solid state memory device includes a controller core 52, a command memory 54, a working memory controller 56, and a working memory 58. The controller core 52 is coupled to the instruction memory 54 and the working memory controller 56, and the working memory controller 56 is coupled to the working memory 58. Controller core 52, instruction memory 54, and working memory controller 56 may be implemented by FPGA 62, which is suitably configured on controller board 104. Further details can be obtained by referring to the description of Fig. 3.

The solid state memory device additionally includes a SATA controller 120 that connects the SATA port 108 to the controller core 52. In this embodiment, the SATA controller 120 is configured to respond to read/write commands and handshaking between the controller core 52 and the SATA busbars located at the host device connected to the SATA port 108. Flow control provides 8-bit data transfer. The SATA controller 120 can follow industry standards. When implemented on an FPGA 62 (eg, Spartan 6), the SATA controller 120 can be connected to the data port 108 via a high speed gigabit transceiver pin that allows for glueless or direct mediation. Connect to the SATA bus of the host unit. The SATA controller 120 and SATA port 108 can be configured to allow a solid state memory device to be connected to a host device, just like a conventional hard disk drive.

The USB physical interface 44 and the USB controller 46 (both of which will be discussed in detail elsewhere herein) are provided with a USB port 110, which is a USB mass storage interface for solid state memory devices. The user can therefore choose whether to connect the solid state memory device to the host device (eg, a computer) via a SATA connection or a USB connection.

The solid state memory device additionally includes a power port 122 and a connected power conditioner 124. The power port 122 is configured to receive power from an external source, if desired, and the power conditioner 124 is configured to regulate the power supply and provide operational power to the solid state memory device at any desired voltage.

The solid state memory device additionally includes an SPI 126. The SPI 126 includes a plurality of SPI controllers 128. Each SPI controller 128 provides communication between the controller core 52 and a memory card 106. Each SPI controller 128 is configured to translate the read and write operations from the controller core 52 into a 4-bit command and data cycle of the standard SD card. In addition, each SPI controller 128 is configured to communicate in parallel with all of the memory cards 112 of the individual memory card 106. Each SPI controller 128 can also be coupled to an indicator (e.g., indicator 19 of FIG. 1), and the control indicators are illuminated according to read/write access and/or fault conditions of the individual memory card 106.

A plurality of memory stick connectors 130 are coupled to the SPI 126. Each memory stick connector 130 is configured to physically connect the memory card stick 106 to an individual SPI controller 128.

FIG. 9 is a diagram showing a memory card 106. The memory card 106 includes a PCB 140 on which the memory card 112 is mounted by a removable or non-removable connection. The memory card 106 additionally includes a physical connector 142 and a buffer 144 that connects the connector 142 to each of the memory cards 112.

The connector 142 can be the same component as the individual connector 130 (Fig. 8), or can be configured to be mated to the connector 130 in a removable or non-removable manner.

The buffer 144 can be configured to control the integrity of the signal and reduce the noise of data communication between the connector 142 and the memory card 112.

In the illustrated example, eight microSD memory cards 112 are disposed on each memory card 106. However, the number of the memory cards 112 is not particularly limited. In some examples, a 50 Mhz data clock is used to access memory card 112, and each memory card 112 is accessed via a 4-bit interface. This provides a read speed of 200 MB/s and a write speed of approximately 150 MB/s. The memory card 112 can be accessed in parallel such that two or four memory cards 112 can be in the same read or write queue. This can further increase the read/write speed to approximately 800 MB/s read and 600 MB/s write. This memory card is configured to allow data transfer rates for SATA 1, SATA 2, or SATA 3 speeds when accessed via SATA port 108 (Fig. 8).

Referring back to FIG. 8, controller core 52 is configured to provide parallel read/write access to memory card 112 for each memory card 106. Controller core 52 is configured to provide parallel access to memory card 106. Therefore, the total capacity of the solid state memory device is approximately equal to the sum of the capacities of the memory cards 112. In addition, because of the parallel access to the memory stick 106, the read/write access time for the total storage capacity is reduced relative to the read/write access time of the individual memory card 112.

In this embodiment, the solid state memory device handles all read, write, delete, and similar file access operations substantially as if it were a standard SATA hard drive and/or USB memory stick. The solid state memory device can emulate a SATA hard drive.

Figure 10 illustrates memory mapping, controller core 52 uses memory mapping to map memory requests from the host device to the memory card The individual memory card 112 of the stick 106. The memory map can be stored in the instruction memory 54 (Fig. 8) of the solid state memory device. Controller core 52 may be configured to access memory card 112 with reference to a memory map, as discussed elsewhere herein.

The memory map defines a memory region 150 having a width 152 of N bytes, where N is the number of memory cards 112 per memory card 106. In this example, eight memory cards 112 are used to generate an octet or 64-bit zone width 152. Further, in this example, the total zone size is selected to be 4 kilobytes (KB). The memory area 150 is mapped to the host area 154 used at the host device. In this example, host area 154 is a one-bit width and has a total size of 512 bytes, which is compatible with the standard area used by typical computer operating systems to access hard drives and similar storage devices. Thus, in this example, the memory map maps a standard 8-bit wide 512-bit host area 154 to a 64-bit wide 4 KB memory area 150.

In this embodiment, the memory card 122 of each memory card 106 is accessed in parallel, without the performance of individual memory card accesses, resulting in the memory card 106 operating as a virtual 64-bit wide memory card.

In this example, eight host regions 154 (each 512 bytes) are mapped to one memory region 150 (4 KB). Therefore, a linear group of 64 host areas 154 (32 KB) is mapped to eight memory areas 150, and a linear group of 128 host areas 154 (32 KB) is mapped to 16 memory areas 150.

The memory map can further map the memory region 150 to the memory card 106 in succession. That is, for the group of memory regions 150, the next memory region 150 is assigned to the next memory card 106. For example, when 25 memory cards 106 are used, the first memory region 150 is mapped to the first memory card 106, the second memory region 150 is mapped to the second memory card 106, and so on. The twenty-sixth memory region 150 is mapped to the second memory region of the first memory card 106.

Thus, memory mapping can allow parallel writing and reading of multiple memory regions 150 because each memory region 150 is successively mapped to a different memory card 106. Such parallel writing can result in an increase in the speed of memory access up to the number of memory sticks 106 used. In the example of 25 memory sticks 106, approximately 100 KB (25 4 KB memory areas) can be simultaneously written. The number of memory regions to be written higher than the number of memory card bars 106 can be listed.

The solid state device discussed above provides simultaneous access to multiple memory cards to simulate a high density, high speed hard disk drive. The order of the zones is configured such that a continuous configuration of the zones of the hard disk can be mapped to the memory card stick 106, allowing parallel/column access for sequential zone reads and writes. The zone mapping is performed in parallel on individual memory cards to increase access speed. The solid state device can read or write multiple zones at a time, keeping the USB or SATA interface full of data in response to the host device requesting 32, 64, 128, or more zones at a time.

In other embodiments, controller core 52 is configured to operate a plurality of memory card sticks 106 as RAID. Can implement RAID mirroring, To allow data redundancy, to help prevent data loss. Any useful RAID level can be used (for example, RAID 1, RAID 2, etc.). In other embodiments, controller core 52 is configured to provide data encryption to provide a highly secure and fault tolerant mass storage device.

Referring to FIG. 11, the present invention includes one or more solid state memory devices 162 configured as rack units 160. Solid state memory device 162 can be any of the solid state memory devices described herein. The solid state memory device 162 can include a plurality of memory card 164, and the memory card 164 can include a plurality of memory cards (eg, SD, miniSD, microSD, as discussed above), as described elsewhere herein. Additionally or alternatively, the solid state memory device 162 in the rack unit 160 can include a solid state drive (SSD) that does not use a removable memory card and a memory stick. In this embodiment, a plurality of similar or identical solid state memory devices 162 are configured as rack units 160.

The rack unit 160 includes a housing 166 that houses the solid state memory device 162, a power supply 168 that is coupled to the solid state memory device 162 to provide power to the solid state memory device 162, and a removable cover 169. The housing 166 includes a venting opening and an internal support for holding the solid state memory device 162. The power supply 168 is configured to adjust and regulate the primary power used by the solid state memory device 162 and may include an uninterruptable power source (UPS). A removable cover 169 is removably attached to the front of the rack unit 160 to allow access to the solid state memory device 162 to allow insertion and removal of the entire solid state memory device 162, device 162 The memory card on the top, or the individual memory card on the memory card. Each solid state memory device 162 can be individually removed and hot swapped from the rack unit 160 such that each solid state memory device 162 can be replaced with another solid state memory device 162. Each memory card and each memory card of each solid state memory device 162 can be individually removed and hot swapped, as discussed elsewhere herein. The power supply 168 is smaller than a conventional rack unit that uses a hard disk drive with similar overall storage capacity because the solid state memory devices described herein have reduced power requirements.

Rack unit 160 can be a 4U unit or any other size, such as 1 U, 2 U, etc., where the shape and size of housing 166 changes accordingly. Rack unit 160 can be mounted to a standard data center rack or cabinet 180, as shown in FIG. The data center rack 180 can be a standard 42U size and can hold any suitable number and size of rack units 160 for a total of 42U or less. Other components (eg, servers, uninterruptible power supplies, interfaces, and the like) may be mounted in the same rack 180 as one or more rack units 160.

As shown in FIG. 13, the customized data center rack or cabinet 190 can include any number of solid state memory devices (shown at 192) mounted directly into the rack 190. This eliminates the limitations of standards such as 1U, 2U, etc., and allows for a more efficient or cost effective configuration of solid state memory devices. Any of the solid state memory devices described herein can be used in a rack or cabinet 190.

Other high-capacity shapes are also conceivable, such as desktop boxes, tower servers, and the like.

A high storage density can be achieved using the embodiments illustrated in Figures 11 through 13 while maintaining other advantages of the solid state memory devices described herein.

Figure 14 illustrates another solid state memory device in accordance with the present invention. The components of the memory device shown in Fig. 14 are examples, and the functions discussed below may be implemented with other kinds of components, fewer generalized components, or a larger number of more specialized components. Like reference numerals designate similar elements, and the redundant description is omitted for clarity.

The solid state memory device includes a controller 200, a plurality of memory sticks 202, and a plurality of memory devices 204. Controller 200, memory stick 202, and memory device 204 are similar to those discussed elsewhere herein. For example, controller 200 includes one or more components depicted as being mounted at controller board 104 of FIG. 8, and specifically controller core 52, instruction memory 54, and working memory controller 56 and operation Memory 58. The memory stick 202 can include the elements and functions of the memory stick 106, and the memory device 204 can include a memory card (eg, SD, miniSD, microSD, etc.). The controller 200, the memory stick 202, and the memory device 204 are also mapped in accordance with the memory and operate in parallel, as discussed above in relation to FIG. 10, wherein the memory stick 202 and the memory device 204 are removable from the solid state memory device. Remove and hot swap. The fault tolerance, RAID, and encryption features discussed above can also be implemented using solid state memory devices. The controller 200, the memory stick 202, and the memory device 204 are connected to each other via wireless communication, and are connected to the host device 60 via wireless communication.

Controller 200 includes control logic and memory 206, such as controller core 52, instruction memory 54, and working memory controller 56 and working memory 58 as described in FIG. Control logic and memory 206 may further include other components described in relation to Figures 3 and 8. Control logic and memory 206 are configured to control memory access in accordance with the parallel memory map described in relation to FIG. In addition, control logic and memory 206 can be configured for fault tolerance, RAID, and encryption, as discussed elsewhere herein.

Controller 200 additionally includes a short or medium distance wireless interface 208, such as Bluetooth, Wi-Fi, WiMAX, or a similar interface. Wireless interface 208 includes a wireless transmitter, a wireless receiver, a wireless transceiver, or a combination of such devices having one or more suitable antennas. The wireless interface 208 is configured to provide a host wireless connection 210 for communicating commands and data between the controller 200 and the host device 60, such as a desktop/laptop, a smart phone, a server, or Other digital devices including compatible wireless interfaces. The wireless interface 208 is further configured to communicate instructions and data between the controller 200 and the memory stick 202. Alternatively, one or more additional wireless interfaces may be provided to controller 200 for communication with memory stick 202. Such additional wireless interfaces may be the same or different schemes (Bluetooth, Wi-Fi, WiMAX, etc.) as the wireless interface 208.

Each memory stick 202 includes a short or medium distance wireless interface 212, such as Bluetooth, Wi-Fi, WiMAX, or a similar interface. The wireless interface 212 includes a wireless transmitter, a wireless receiver, and a wireless transceiver. A combination of such devices, or one or more suitable antennas. The wireless interface 212 is configured to provide a wireless connection 214 to the controller of the controller 200 to communicate commands and data between the controller 200 and the memory stick 202. The wireless interface 212 is additionally configured to communicate commands and data to a subset of the memory device 204. Alternatively, one or more additional wireless interfaces may be provided to the memory stick 202 for communication with the memory device 204. Such additional wireless interfaces may be the same or different schemes (Bluetooth, Wi-Fi, WiMAX, etc.) as the wireless interface 212.

Each memory stick 202 can additionally include a buffer 216 for buffering data and instructions during transmission between the memory stick 202 and the associated memory device 204. Buffer 216 can be configured to control signal integrity and reduce noise in data communication between memory stick 202 and connected memory device 204.

Each memory device 204 includes a short or medium distance wireless interface 218, such as Bluetooth, Wi-Fi, WiMAX, or a similar interface. Wireless interface 218 includes a wireless transmitter, a wireless receiver, a wireless transceiver, or a combination of such devices having one or more suitable antennas. The wireless interface 218 is configured to provide a memory wireless connection 214 to a memory stick 202 for communicating commands and data between the memory device 204 and the memory stick 202. Each memory device 204 additionally includes a memory 222, such as a memory card (eg, SD, miniSD, microSD, etc.), an SSD, or the like. It is noted that the techniques discussed herein, how the memory card is connected, mapped, and controlled, are equally applicable to SSDs.

Each of controller 200, memory stick 202, and memory device 204 can store unique identifiers (eg, media access control, MAC, address) such that they can be identified for wireless communication purposes. That is, the controller 200 has an identifier that is recognized by the host device 60 and the memory stick 202 to identify the controller 200, and the identifier distinguishes the controller 200 from other devices within the range and using the same wireless communication scheme, such as a memory. Device 204. Similarly, each memory stick 202 has an identifier that is referenced by the controller 200 and the memory device 204 to identify the memory stick 202, and the identifier distinguishes the memory stick 202 from other devices that are within range and use the same wireless communication scheme. Similarly, each memory device 204 has an identifier that is referenced by the memory stick 202 to identify the memory device 204, and the identifier distinguishes the memory device 204 from other devices that are within range and use the same wireless communication scheme. Each of controller 200, memory stick 202, and memory device 204 can be configured to be associated with individual controller 200, memory stick 202, and memory device 204 that reference unique identifiers. Controller 200 is associated with a plurality of memory sticks 202, and each memory stick 202 is associated with a different subset of a plurality of memory devices 204. The association between devices can be established as part of a pairing or other processing of a wireless communication scheme. The association between the memory stick 202 and the memory stick 202 and the memory device 204 can be stored in the control logic and memory 206 of the controller 200. When the memory stick 202 is not accessible by the controller 200, the controller 200 marks the associated memory device 204 as being removed from the solid state memory device. If the wireless connection to the memory stick 202 is re-established, the controller 200 marks the associated memory device. 204 is available. When the wireless connection to the new memory stick 202 is established, the controller 200 enumerates the memory device 204 associated with the memory stick 202. The controller 200 can copy material from the existing memory device 204 to the memory device 204 of the new memory stick 202, for example, when RAID is implemented. The same concepts as above apply to individual memory devices 204 when wireless connections to individual memory sticks 202 are established, lost, and re-established.

In this embodiment, preferably, each memory device 204 is associated with only one memory stick 202 at a given time, and each memory stick 202 is associated with only one controller 200 at a given time. Controller 200 can be configured to manage wireless connections accordingly.

It is noted that memory stick 202 and memory device 204 are not computer or similar processing devices. That is, the functions of the memory stick 202 and the memory device 204 are limited to the storage and retrieval of data and related processing. This advantageously reduces complexity and may increase data access speed.

The memory mapping described above for other embodiments is equally applicable to the present embodiment. The memory map references the unique identifier of the memory stick 202 and the memory device 204 to distribute data between the memory devices 204 and to retrieve data from the memory device 204. The host device 60 only needs to know the identifier of the controller 200.

In some embodiments, the controller 200, the memory stick 202, and the memory device 204 are configured to form an ad hoc or private wireless network as a virtual storage pool, wherein each memory stick 202 and each memory device 204 have The private wireless MAC address associated with the zone/zone of the virtual storage pool. As described above, the controller 200 is the main one without the host 60. Line interface. In addition, controller 200 is configured to maintain a private wireless MAC address mapped to a sector/zone of a virtual storage pool to translate host requests to associated memory stick 202 and device 204. When the file system for the virtual storage pool is first generated, the controller 200 is configured to intercept the format commands from the host 60 and is further configured to construct the mapping with reference to the format commands. That is, the controller 200 can be configured to construct a table to record which memory sticks 202 and devices 204 form particular portions of the virtual storage pool, and if or when the memory stick 202 and device 204 are added, removed, or replaced. , update the table. In one example, such a table includes the private wireless MAC address of memory stick 202 and device 204, associated with the sector/area of the virtual storage pool visible to host 60. The controller 200 can be configured to maintain the indicator table and provide a user interface to the host 60 such that the indicator table can be accessed by the host 60 to output statistics, such as usage levels, and to allow replacement of a particular memory stick 202 and memory within the virtual storage pool. Body device 204. In these embodiments, the wireless memory stick 202 is associated with the memory of the wireless memory device 204 and can be automatically detected as a large disk having the ability to easily add/remove/replace the memory stick 202 and the memory device 204. ability.

In operation, host device 60 and controller 200 establish a wireless connection via host wireless connection 210, controller 200 establishes a wireless connection with memory stick 202 via controller wireless connection 214, and each memory stick 202 is wirelessly coupled via memory 220. A wireless connection is established with an individual subset of memory devices 204. From the host device 60, a command to store and retrieve data is sent to the controller 200, and the controller 200 interprets The commands also send corresponding instructions to the associated memory stick 202, and the associated memory stick 202 then commands the associated memory device 204. In response to the instructions, the data is stored in or retrieved from the memory device 204.

The embodiment of Figure 14 can be advantageously used with the rack and cabinet embodiments of Figures 11 through 13. For example, a 1U controller rack unit can manage a 1U memory stick rack unit, and a 1U memory stick rack unit manages eight 4U memory unit rack units with wireless communication transfer commands and data in between and control rack units and hosts. Between the devices, the host device can be installed in the same rack. In another example, the 8U rack unit includes the controller 200, the associated memory stick 202, and associated memory device 204 in a self-contained configuration, internally communicating via wireless communication, and communicating with the host device via wireless communication. External communication. Other examples are also envisaged.

Referring to Figure 15, the present invention includes one or more solid state memory devices 162 configured as a rack unit 250. Rack unit 250 is similar to rack unit 160 and only the differences between the two will be discussed in detail. Like reference numerals indicate like elements and reference to the above description of rack unit 160. Rack unit 250 houses a plurality of solid state memory devices 162, such as any of the solid state memory devices described herein. In the illustrated example, rack unit 250 is a 4U unit.

The rack unit 250 includes a plurality of trays 252 that are vertically supported within the rack unit 250. A plurality of solid state memory devices 162 are removably attached to the upper surface of each tray 252. Each tray 252 is thereby The attached plurality of solid state memory devices 162 are mechanically supported. The tray 252 may also include electrical connections, such as connector ports, for providing power and/or data connections to the supported solid state memory device 162. In this case, at least one of the flexible cable connection trays 252 is electrically connected to the main busbar or other system of the rack unit 250. Alternatively, tray 252 does not include electrical connections, and power and/or data connections to solid state memory device 162 are accomplished via flexible busses to the main busbars of rack unit 250 or other systems. In yet another example, the tray 252 includes electrical connections to provide power to the supported solid state memory device 162, while the data connection to the device 162 is accomplished via a flexible cable or wireless. In general, each power connection and data connection of device 162 can be provided via: (a) a rigid connector at support tray 252, and a main busbar or other system from support tray 252 to rack unit 250. Flexible cable, or (b) a flexible busbar from the device 162 to the main busbar of the rack unit 250 or other system. Additionally, the data connection of device 162 can be provided wirelessly without the need for a cable or rigid connector.

Each tray 252 is supported within the frame 250 by at least one slidable rail 254. Each slidable rail 254 is coupled to the housing 166 of the gantry unit 250 and is configured to view the solid state memory device 162 or individual memory card or memory stick when the cover 169 (not shown) is removed. Inspecting and inserting, the tray 252 to which the supported solid state memory device 162 is attached is slid out of the housing 166. As mentioned elsewhere herein, an indicator 19 (eg, an LED) can be provided to the solid state memory device 162 to visually indicate a fault or other event to facilitate inspection. Such an indicator 19 can be configured to indicate a failure of an individual memory card, memory card, and/or solid state memory device 162. Advantageously, the tray 252 and rail 254 system allows for easy access to the solid state memory device 162 for hot plugging of devices, rods, and cards, as well as for quick and convenient inspection.

Figure 16 is a side elevational view of the rail arrangement configured to slide the tray 252 into and out of the frame 250. The slidable rail 254 to which the tray 252 is fixed is telescopically engaged with the intermediate slidable rail 256, and the middle slidable rail 256 is telescopically engaged with the stationary base rail 258, and the base rail 258 is fixed to the frame. The interior of the housing 166 of 250. Any number of intermediate slidable rails 256 can be used. The intermediate slidable rail 256 can be omitted such that the slidable rail 254 is directly coupled to the stationary base rail 258. Telescopic sliding mechanical connections between the rails can include bearings, bushings, and the like.

Figure 17 illustrates a plurality of rack units 250 as components 270 of a cabinet or other vertically stacked configuration. Each tray 252 of each rack unit can be individually slid out to inspect and hot plug the solid state memory device 162, memory card, or individual memory card. Advantageously, each component of the oversized array storage element (down to a single individual memory card) can be individually inspected and hot swapped in the event of a fault or other need.

Although the above techniques are described in relation to SD cards, this is not intended to be limiting, and various aspects of the present invention are applicable to other memory technologies currently available, under development, or not yet developed. The various aspects of the invention are applicable to any type of memory, and the type of memory used can be purely theoretical and need not be known by the system. Examples of memory technologies that can be used with various aspects of the present invention include SD cards, flash memory, dynamic random access memory (DRAM), magnetic storage (eg, hard disk drives), memrist devices, Phase-change memory (PCM), and spin-transfer torque random access memory (STT-RAM). Each of these memory technologies can be applied as a memory device, a memory stick, or a memory card, as discussed elsewhere herein.

Advantages of the present invention can include no moving parts, reduced heat generation, reduced noise generation, and low cost capacity, which can effectively replace hard disk drives and/or USB mass storage devices. Additionally, the present invention can provide a relatively inexpensive and dense storage capacity compared to some types of solid state drives (SSDs). In addition, the capacity of a plurality of memory cards is combined in an efficient, user-friendly, and data-safe manner. Regarding high capacity, when using 25 memory card bars each including eight 128 GB microSD cards, the generated solid state disk has a capacity of about 25 TB. In addition, high-capacity form factor and wireless connectivity are available for high-density applications with fewer restrictions on physical placement.

While the foregoing provides certain non-limiting example embodiments, it should be understood that the foregoing combinations, sub-sets, and variations are conceivable. The exclusive right sought is defined by the scope of the patent application.

44‧‧‧Physical interface

46‧‧‧Interface controller

52‧‧‧Controller core

54‧‧‧Instruction Memory

56‧‧‧ working memory controller

58‧‧‧ working memory

62‧‧‧ Field Programmable Gate Array (FPGA)

104‧‧‧Controller board

106‧‧‧ memory card stick

108‧‧‧ SATA埠

110‧‧‧USB埠

120‧‧‧SATA controller

122‧‧‧Power supply埠

124‧‧‧Power conditioner

126‧‧‧SPI

128‧‧‧SPI controller

130‧‧‧Memory Stick Connector

Claims (18)

A solid state memory device comprising: a rack unit housing shaped and dimensioned to be adapted to a data center rack or cabinet; a plurality of memory devices, the plurality of memory device settings a plurality of memory sticks disposed in the rack unit housing, each memory stick of the plurality of memory sticks being coupled to a subset of the plurality of memory devices a memory device; the controller is configured to access the plurality of memory devices in parallel through the plurality of memory sticks to access the plurality of memory devices as a virtual memory device and present Giving a host a single non-volatile storage unit having a total capacity based on a capacity of the plurality of memory devices; the controller further configured to operate in accordance with a memory map to map memory requests from the host Up to the plurality of memory devices, the memory map defines a memory region for accessing each memory stick of the plurality of memory sticks, the memory Mapping to a plurality of host areas defined by the host, each host area of the plurality of host areas being mapped to a different memory device of each memory stick; and each memory area mapping of the plurality of memory areas Different The memory stick is used to write and read the plurality of memory areas in parallel to increase the speed of memory access. The device of claim 1, wherein the controller comprises a wireless interface, and the at least one memory stick of the plurality of memory sticks comprises a wireless interface, the wireless interface of the controller and the wireless of the at least one memory stick The interface is configured to wirelessly communicate instructions and data between the controller and the at least one memory stick. The device of claim 2, wherein the at least one memory stick of the plurality of memory sticks comprises a wireless interface, and the at least one memory device of the plurality of memory devices comprises a wireless interface, the at least one memory stick The wireless interface and the wireless interface of the at least one memory device are configured to wirelessly communicate commands and data between the at least one memory stick and the at least one memory device. The device of claim 1 further comprising a power supply disposed within the rack unit housing for providing power to the solid state memory device. The device of claim 1, wherein each of the plurality of memory devices comprises a solid state hard disk. The device of claim 1, wherein each memory stick of the plurality of memory sticks is a memory card, and each memory device of the plurality of memory devices includes a memory card. The device of claim 1, wherein the subset of memories Each memory device of the body device can be hot swapped from each memory stick. The device of claim 1, further comprising a slidable tray supporting the plurality of memory devices in the rack unit housing and the plurality of memory sticks, the slidable tray being configured to slide in The rack unit housing is slid out of the rack unit housing to inspect and hot plug the at least one of the plurality of memory devices and the plurality of memory sticks. A data center rack or cabinet comprising a plurality of solid state memory devices as claimed in claim 1. A solid state memory device comprising: a plurality of memory devices; a plurality of memory sticks, each memory stick of the plurality of memory sticks coupled to a memory device of a subset of the plurality of memory devices; a controller The controller is configured to access the plurality of memory devices in parallel through the plurality of memory sticks to access the plurality of memory devices as a virtual memory device and present to a host based on the complex number a single non-volatile storage unit having a total capacity of one of the memory devices; the controller includes a wireless interface, and the at least one memory stick of the plurality of memory sticks includes a wireless interface, the wireless interface of the controller The wireless interface with the at least one memory stick is configured to wirelessly communicate commands and resources between the controller and the at least one memory stick And the at least one memory device of the plurality of memory devices includes a wireless interface, the wireless interface of the at least one memory stick and the wireless interface of the at least one memory device being configured to be in the at least one memory stick Wireless communication instructions and data between the at least one memory device. The device of claim 10, wherein the controller is further configured to operate in accordance with a memory map to map a memory request from the host to the plurality of memory devices, the memory map defining a memory region The memory area is used to access each memory stick of the plurality of memory sticks, the memory area is mapped to a plurality of host areas defined by the host, and each host area of the plurality of host areas is mapped to each a different memory device associated with a memory stick, and each memory region of the plurality of memory regions is mapped to a different memory stick for writing and reading the plurality of memory regions in parallel Increase the speed of memory access. The device of claim 10, wherein each memory stick of the plurality of memory sticks comprises a wireless interface such that all of the memory sticks are configured to wirelessly communicate instructions and data to the controller. The device of claim 10, wherein each of the plurality of memory devices includes a wireless interface such that all of the memory devices are configured to wirelessly communicate instructions and data to the plurality of memory sticks. The device of claim 10, wherein each of the plurality of memory devices comprises a solid state drive. The device of claim 10, wherein each memory stick of the plurality of memory sticks is a memory card, and each memory device of the plurality of memory devices includes a memory card. The device of claim 10, wherein each memory device of the subset of memory devices is hot pluggable from each memory stick. The device of claim 10, further comprising a rack unit housing shaped and adapted to be adapted to a data center rack or cabinet, wherein the plurality of memory devices, the plurality A memory stick is disposed in the housing unit housing with the controller. The device of claim 17, further comprising a slidable tray supporting the plurality of memory devices in the rack unit housing and the plurality of memory sticks configured to slide in The rack unit housing is slid out of the rack unit housing to inspect and hot plug the at least one of the plurality of memory devices and the plurality of memory sticks.