TW202207424A - Semiconductor storage device - Google Patents

Abstract

Provided is a semiconductor storage device which is able to be produced with less cost. A semiconductor storage device according to one embodiment of the present invention is provided with a first substrate, a first element layer that is provided on the upper surface of the first substrate, a second substrate, and a second element layer that is provided on the upper surface of the second substrate. The first substrate comprises a first via. The first element layer comprises a first pad which is electrically connected to the first via, while being provided on the upper surface of the first element layer; and the second substrate comprises a second via. The second element layer comprises a second pad which is electrically connected to the second via, while being provided on the upper surface of the second element layer. The upper surface of the second element layer is arranged so as to face the upper surface of the first element layer. The first pad and the second pad are arranged symmetrically with respect to the facing surfaces of the first element layer and the second element layers, while being electrically connected to each other.

Description

Semiconductor memory device and manufacturing method of semiconductor memory device

Embodiments of the present invention relate to a semiconductor memory device.

A NAND (Not-And) type flash memory is known as a semiconductor memory device.

Embodiments of the present invention provide a semiconductor memory device capable of reducing manufacturing costs. A semiconductor memory device according to an embodiment of the present invention includes: a first substrate; a first element layer provided on the upper surface of the first substrate; a second substrate; and a second element layer provided on the second substrate on the upper surface. The said 1st board|substrate contains a 1st through hole. The first element layer includes a first pad electrically connected to the first through hole and provided on the upper surface of the first element layer, and the second substrate includes a second through hole. The second element layer includes a second pad electrically connected to the second through hole and disposed on the upper surface of the second element layer. The upper surface of the second element layer is oppositely disposed on the upper surface of the upper first element layer. The first pad and the second pad are symmetrically arranged with respect to the surfaces of the first element layer and the second element layer facing each other, and are electrically connected to each other.

Hereinafter, embodiments will be described with reference to the drawings. In addition, in the following description, the same reference signs are attached|subjected to the component which has the same function and structure. In addition, when distinguishing a plurality of constituent elements having the same reference symbol, the same reference symbol is marked with a subscript to distinguish it. Furthermore, when there is no need to distinguish a plurality of constituent elements in particular, only the same reference symbols are attached to the plural constituent elements, and no subscripts are attached. 1. First Embodiment The semiconductor memory device according to the first embodiment will be described. 1. 1. About the structure First, the structure of the semiconductor memory device according to the first embodiment will be described. 1. 1. 1 About the overall configuration of the memory system An example of the configuration of the memory system according to the first embodiment will be described with reference to FIG. 1 . FIG. 1 is a block diagram showing an example of the configuration of the memory system according to the first embodiment. The memory system 1 is provided, for example, on an external substrate system (not shown). The memory system 1 operates by the power supply voltage and the ground voltage GND supplied from the substrate system, and communicates with an external host device (not shown). The memory system 1 holds data from a host machine (not shown) and reads the data to the host machine. As shown in FIG. 1 , a memory system 1 includes a controller 2 and a semiconductor memory device (NAND-type flash memory) 3 . The controller 2 receives commands from the host machine, and controls the semiconductor memory device 3 based on the received commands. Specifically, the controller 2 writes the data instructed to be written from the host machine to the semiconductor memory device 3 , and reads the data instructed to read from the host machine from the semiconductor memory device 3 and sends it to the host machine. The controller 2 is connected to the semiconductor memory device 3 through a NAND bus. The semiconductor memory device 3 includes a plurality of memory cells and stores data in a non-volatile manner. The NAND bus carries out the sending and receiving according to the signals /CE, CLE, ALE, /WE, /RE, RE, /WP, /RB, DQS, /DQS, and I/O<7:0> of the NAND interface. The signal /CE is a signal for enabling the semiconductor memory device 3 . The signals CLE and ALE inform the semiconductor memory device 3 that the signals I/O<7:0> flowing through the semiconductor memory device 3 in parallel with the signals CLE and ALE are the command CMD and the address ADD, respectively. The signal /WE indicates that the signal I/O<7:0> flowing through the semiconductor memory device 3 in parallel with the signal /WE is to be captured to the semiconductor memory device 3 . The signals /RE and RE instruct to output the signal I/O<7:0> to the semiconductor memory device 3 . The signal /WP instructs the semiconductor memory device 3 to prohibit data writing and erasing. The signal /RB indicates whether the semiconductor memory device 3 is in a ready state (a state in which an external command is accepted) or a busy state (a state in which an external command is not accepted). Signal I/O<7:0> is, for example, an 8-bit signal. The signals DQS and /DQS are reference signals that serve as indicators of the timing of input and output of the signal I/O<7:0> of the semiconductor memory device 3 . The signal I/O<7:0> is the entity of the data sent and received between the semiconductor memory device 3 and the controller 2, including the command CMD, the address ADD, the data DAT, and the state STS. Data DAT includes writing data and reading data. 1. 1. 2. About the structure of the controller The controller of the memory system of the first embodiment will be described with reference to Fig. 1. The controller 2 includes a processor (CPU: Central Processing Unit, central processing unit) 5, a built-in memory (RAM: Random Access Memory, random access memory) 6, a NAND interface circuit 7, a buffer memory 8, and a host Interface circuit 9. The processor 5 controls the overall actions of the controller 2. For example, the processor 5 responds to the data write command received from the host machine, and issues the write command based on the NAND interface to the semiconductor memory device 3 . This operation is also the same in the case of readout and deletion. The built-in memory 6 is, for example, a semiconductor memory such as DRAM (Dynamic RAM, dynamic random access memory), and is used as an operation area of the processor 5 . The built-in memory 6 holds firmware for managing the semiconductor memory device 3, various management tables, and the like. The NAND interface circuit 7 is connected to the semiconductor memory device 3 via the NAND bus bar, and performs communication with the semiconductor memory device 3 . The NAND interface circuit 7 sends the command CMD, the address ADD, and the written data to the semiconductor memory device 3 according to the instruction of the processor 5 . Also, the NAND interface circuit 7 receives read data from the semiconductor memory device 3 . The buffer memory 8 temporarily holds the data and the like received by the controller 2 from the semiconductor memory device 3 and the host machine. The host interface circuit 9 is connected with the host machine to perform communication with the host machine. The host interface circuit 9, for example, transmits commands and data received from the host machine to the processor 5 and the buffer memory 8, respectively. 1. 1. 3 About the structure of the semiconductor memory device Next, an example of the structure of the semiconductor memory device of the first embodiment will be described with reference to FIG. 2 . FIG. 2 is a block diagram showing an example of the configuration of the semiconductor memory device of the first embodiment. The semiconductor memory device 3 includes, for example, an interface chip 10 and a core chip group 11 that are operated by a power supply voltage and a ground voltage GND supplied from a substrate system. The core wafer group 11 includes, for example, four core wafers CC (CC0, CC1, CC2, and CC3). The number of core chips CC is not limited to four, and any number can be used. Here, the "core chip CC" refers to a constituent unit of a semiconductor integrated circuit (chip) that can function as one NAND flash memory together with the interface chip 10 . The interface chip 10 has connection signals /CE, CLE, ALE, /WE, /RE, RE, /WP, /RB, DQS, /DQS, and I/O<7 between the controller 2 and the core chip group 11: 0> function. For example, the interface chip 10 transmits the signals DQS and /DQS, and the command CMD and the address ADD in the I/O<7:0> to the core chip group 11 . Also, for example, the interface chip 10 and the core chip group 11 transmit and receive DQS and /DQS, and write data and read data in the signal I/O<7:0>. Each core chip CC includes a memory cell array 12, a data transfer circuit 13, a logic control circuit 14, a sequencer 15, a voltage generation circuit 16, a driver set 17, a column decoder 18, and a sense amplifier 19. In the following description, it will be provided in the memory cell array 12 , the data transmission circuit 13 , the logic control circuit 14 , the sequencer 15 , the voltage generation circuit 16 , the driver set 17 , the column decoder 18 , and the sense amplifier 19 . The various circuits in each core chip are collectively referred to as "internal circuits". The memory cell array 12 includes, for example, four planes (plane 0, plane 1, plane 2, and plane 3). The plane includes a plurality of non-volatile memory cell transistors (not shown) associated with word lines and bit lines. In each plane, for example, in one write operation or one read operation, the write operation and the read operation can be performed simultaneously. Furthermore, the number of planes in the memory cell array 12 is not limited to 4, for example, 1, 2, 8, etc. can be used. The data transfer circuit 13 transfers the command CMD and the address ADD to the sequencer 15. In addition, the data transfer circuit 13 and the sense amplifier 19 send and receive write data and read data. The logic control circuit 14 receives signals corresponding to the signals /CE, CLE, ALE, /WE, /RE, RE, and /WP via the interface chip 10. In addition, the logic control circuit 14 transmits the signal /RB to the controller 2 via the interface chip 10 to notify the outside of the state of the core chip. The sequencer 15 receives the command CMD and controls the entirety of the core chip according to the sequence based on the received command CMD. The voltage generation circuit 16 generates voltages required for operations such as data writing, reading, and erasing based on instructions from the sequencer 15. The voltage generating circuit 16 supplies the generated voltage to the column decoder 18 and the sense amplifier 19 . Column decoder 18 receives the column address in address ADD from sequencer 15 and selects a portion of each plane based on the column address. Then, the voltage from the voltage generating circuit 16 is transmitted through the column decoder 18 to the selected portion of each plane. During data readout, the sense amplifier 19 senses the readout data read out from the memory cell transistor to the bit line, and transmits the sensed readout data to the data transmission circuit 13 . The sense amplifier 19 transmits the written data written through the bit line to the memory cell transistor when data is written. Also, the sense amplifier 19 receives the row address in the address ADD from the sequencer 15 and outputs row data based on the row address. Furthermore, in the example of FIG. 2 , the interface chip 10 and the core chip group 11 are shown as different chips, but it is not limited to this. For example, the core chip group 11 may also include circuits having the same functions as the interface chip 10 . In this case, the core chip group 11 can also communicate various signals with the controller 2 without going through the interface chip 10 . 1. 1. 4. Configuration of Core Chip Group Next, the configuration of the core chip group of the semiconductor memory device of the first embodiment will be described. 1. 1. 4. 1. Connection between core chips First, the connection between the core chips of the semiconductor memory device of the first embodiment will be described with reference to FIG. 3 . 3 is a circuit diagram for explaining an example of connection between core chips of the semiconductor memory device of the first embodiment. As shown in FIG. 3 , the core wafer group 11 is constituted by, for example, connecting the core wafers CC0 to CC3 in series. Specifically, each of the core chips CC0 to CC3 includes terminals T1a, T2a, T3a, and T4a, and terminals T1b, T2b, T3b, and T4b. In addition, each of the core chips CC0 to CC3 further includes logic circuits LGA and LGB. The terminals T1a-T4a of the core chip CC0 are connected to the external interface chip 10 or the controller 2, for example. The terminals T1b to T4b of the core chip CC0 are connected to the terminals T1a to T4a of the core chip CC1, respectively. The terminals T1b to T4b of the core chip CC1 are connected to the terminals T1a to T4a of the core chip CC2, respectively. The terminals T1b to T4b of the core chip CC2 are connected to the terminals T1a to T4a of the core chip CC3, respectively. In each core chip CC, the terminals T1a and T1b, the terminals T2a and T2b, and the terminals T3a and T3b are connected through wirings provided inside each core chip CC. In each core chip CC, the logic circuit LGA is arranged on the wiring between the terminals T2a and T2b, and the logic circuit LGB is arranged on the wiring between the terminals T3a and T3b. The logic circuit LGA includes an input terminal connected to the terminal T2a and an output terminal connected to the terminal T2b. The logic circuit LGB includes an input terminal connected to the terminal T3b and an output terminal connected to the terminal T3a. With the above configuration, from the terminal T1a of the core chip CC0 to the terminal T1b of the core chip CC3 functions as a signal path SL1 capable of transmitting and receiving signals between the core chips CC0-CC3. In addition, from the terminal T2a of the core chip CC0 to the terminal T2b of the core chip CC3 are sent to the core chip CC ( The signal path SL2 of n+1) functions. Furthermore, from the terminal T3a of the core chip CC0 to the terminal T3b of the core chip CC3, it functions as a signal path SL3 capable of transmitting a signal processed by the logic circuit LGB of the core chip CC(n+1) to the core chip CCn. . Furthermore, the terminal T4b of the core chip CCn to the terminal T4a of the core chip CC(n+1) functions as a signal path SL4 that can transmit and receive signals between the core chips CCn and CC(n+1). Furthermore, the terminals T1a to T4a of the core chip CC0 can send and receive various signals with the interface chip 10 or the controller 2 . In addition, the signals communicated between the terminals T in each core chip CC are connected to the internal circuits in the core chip CC. As a result, the internal circuits of each core chip CC can receive signals flowing through the signal paths SL1 to SL4, or send signals to the signal paths SL1 to SL4. In addition, in the example of FIG. 3, although the terminal T1a-T4a, the terminal T1b-T4b, and the logic circuit LG1, LG2 are shown separately from an internal circuit, it is not limited to this. For example, the terminals T1a to T4a, the terminals T1b to T4b, and the logic circuits LG1 and LG2 may be included in the internal circuit. Furthermore, if the logic circuits LGA and LGB are circuit elements whose input and output cannot be interchanged, any logic circuit can be applied. Specifically, the operation processing of the logic circuits LGA and LGB can be, for example, a NOT (NOT) operation, an OR (OR) operation, an AND (AND) operation, an inverse-AND (NAND) operation, an inverse-OR (NOR) operation, a mutually exclusive OR (XOR) operation and other logical operations. Furthermore, FIG. 3 shows an example in which the terminals T1b to T4b are provided on the core chip CC3, but it is not limited to this. For example, when the core chip CC3 is not connected to the core chip CC other than the core chip CC2, the terminals T1b to T4b are not required. In the following description, for the sake of convenience, terminals that are not connected to other core chips CC may be indicated similarly to the core chip CC3 shown in FIG. 3 . However, as described above, the terminal may not be provided. 1. 1. 4. 2 About the structure of the core chip Next, the structure of the core chip of the semiconductor memory device of the first embodiment will be described. The circuit configuration of the core chip shown in FIG. 3 includes, for example, a semiconductor integrated circuit provided on a semiconductor substrate and an element layer on the semiconductor substrate. The semiconductor integrated circuit is specifically designed by, for example, the arrangement of internal circuits (also referred to as a "layout pattern") and the arrangement of wirings connecting the internal circuits (also referred to as a "wiring pattern"). More specifically, for example, the layout pattern determines the memory cell array 12, the data transfer circuit 13, the logic control circuit 14, the sequencer 15, the voltage generation circuit 16, the driver set 17, the column decoder 18, the sensing The arrangement on the semiconductor substrate of the amplifier 19, the terminals T1a to T4a, the terminals T1b to T4b, and the logic circuits LGA and LGB. Also, for example, the wiring pattern determines the input-output relationship of the internal circuits arranged by the layout pattern. The overall information of the design of the core chip CC including the layout pattern and the wiring pattern is also referred to as "chip design". In addition, in the following description, the layout pattern and the wiring pattern are described, for example, as a unit corresponding to one pattern on one semiconductor substrate among the chips cut out from the wafer in the dicing step. . 4 and 6 are plan views for explaining the layout pattern of the core chip of the semiconductor memory device of the first embodiment. 5 and 7 are cross-sectional views for explaining the layout pattern and the wiring pattern of the core chip of the semiconductor memory device of the first embodiment. 5 and 7 respectively show a cross section taken along the line V-V shown in FIG. 4 and the line VII-VII shown in FIG. 6 . 4 and 5 show a configuration common to core chips CC0 and CC2, and FIGS. 6 and 7 show a configuration common to core chips CC1 and CC3. Furthermore, in the following description, the surface on which the internal circuit is provided in the semiconductor substrate is defined as the "upper surface", and the surface on the opposite side of the upper surface is defined as the "lower surface". On the other hand, the surface on the semiconductor substrate side of each layer constituting the internal circuit on the semiconductor substrate is defined as the "lower surface", and the surface on the opposite side of the lower surface is defined as the "upper surface". In addition, the surface on the side of the semiconductor substrate in the core chip is defined as the "lower surface", and the surface on the side of the internal circuit is defined as the "upper surface". Moreover, let the surface parallel to the upper surface and the lower surface of the semiconductor substrate be the xy plane, and let the direction perpendicular to the xy plane be the z direction. In addition, the x direction and the y direction are set to be orthogonal to each other in the xy plane. First, the configuration of the core chips CC0 and CC2 will be described. As shown in FIG. 4 , the layout patterns of the core chips CC0 and CC2 are arranged on the xy plane in a rectangular area having two sides along the x-direction and two sides along the y-direction. Plane 0 to Plane 3 are respectively disposed at the four corners of the rectangular region (the upper left corner, the lower left corner, the upper right corner, and the lower right corner in FIG. 4 ). The column decoder 18 and the sense amplifier 19 are divided into parts corresponding to planes 0 to 3 and arranged. In the following description, the part of the column decoder 18 and the part of the sense amplifier 19 corresponding to the planes 0 to 3 are referred to as the column decoders 18-0 to 18-3 and the sense amplifiers 19-0 to 19, respectively. 19-3. One of the sides of the column decoders 18 - 0 to 18 - 3 along the y direction is connected to, for example, the sides of the planes 0 to 3 along the y direction, respectively. The other of the y-direction sides of column decoders 18-0 and 18-1 is contiguous with the other of the y-direction sides, eg, column decoders 18-2 and 18-3, respectively. The sense amplifiers 19 - 0 to 19 - 3 are respectively connected to, for example, the sides of the planes 0 to 3 along the x-direction. In the area sandwiched by the sense amplifiers 19-0 to 19-3 in the y direction, the data transmission circuit 13, the logic control circuit 14, the sequencer 15, the voltage generation circuit 16, and the driver set 17 are configured. Furthermore, in the following description, the data transmission circuit 13, the logic control circuit 14, the sequencer 15, the voltage generation circuit 16, and the driver set 17 are referred to as the memory cell array 12, the column decoder 18, and the sensor. The "peripheral circuit" of the test amplifier 19. The data transfer circuit 13 is provided in the center of the rectangular area, and the driver set 17 is divided into a portion corresponding to the plane 0 and the plane 2 and a portion corresponding to the plane 1 and the plane 3 and arranged. In the following description, the part of driver set 17 corresponding to plane 0 and plane 2 and the part of driver set 17 corresponding to plane 1 and plane 3 are referred to as driver sets 17U and 17D, respectively. The driver sets 17U and 17D are connected to, for example, the side of the data transfer circuit 13 along the x-direction. The voltage generation circuit 16 is disposed on the plane 0 and plane 1 sides with respect to the data transmission circuit 13 and the driver set 17, for example. The logic control circuit 14 and the sequencer 15 are disposed on the plane 2 and plane 3 sides, for example, with respect to the data transfer circuit 13 and the driver set 17 . The layout patterns of the core chips CC0 and CC2 configured as above correspond, for example, to the symbol P1 shown in FIG. 4 . Also, as shown in FIG. 5 , the element layer 21 is provided on the upper surface of the semiconductor substrate 20 according to the layout pattern corresponding to the symbol P1 and the wiring pattern corresponding to the layout pattern. In addition, in FIG. 5, the description about the internal circuits other than the terminals T1a-T4a, T1b-T4b and the logic circuits LGA and LGB is abbreviate|omitted for simplification. The semiconductor substrate 20 is provided with a plurality of through holes 22 ( 22-1, 22-2, 22-3, and 22-4) that function as TSVs (Through Silicon Vias). A plurality of bumps 23 (23-1, 23-2, 23-3, 23-1, 23-2, 23-3, 23-1, 23-3, 23-3, and 23-4). On the upper surface of the element layer 21, a plurality of pads 24 (24-1, 24-2, 24-3, and 24-4) functioning as the terminals T1b to T4b are provided. The upper surface of the pad 24 is exposed on the upper surface of the element layer 21 . In the element layer 21, the logic element layers 25 and 26 and wiring layers 27-33 which function as logic circuits LGA and LGB are provided. The wiring layer 27 includes a first end disposed on the upper end of the through hole 22-1, and a second end disposed on the lower end of the bonding pad 24-1. The wiring layer 27 is connected to, for example, an internal circuit. The wiring layer 28 includes a first end disposed on the upper end of the through hole 22-2, and a second end disposed on the lower end of the logic element layer 25. The wiring layer 28 is connected to, for example, an internal circuit. The wiring layer 29 includes a first end provided on the upper end of the logic element layer 25, and a second end provided on the lower end of the pad 24-2. The logic element layer 25 includes a lower end having a function as an input end, and an upper end having a function as an output end. That is, the logic element layer 25 functions as the logic circuit LGA that outputs the signal input from the bump 23-2 toward the pad 24-2. The wiring layer 30 includes a first end disposed on the upper end of the through hole 22-3, and a second end disposed on the lower end of the logic element layer 26. The wiring layer 31 includes a first end provided on the upper end of the logic element layer 26, and a second end provided on the lower end of the pad 24-3. The wiring layer 31 is connected to, for example, an internal circuit. The logic element layer 26 includes a lower end having a function as an output end, and an upper end having a function as an input end. That is, the logic element layer 26 functions as a logic circuit LGB that outputs a signal input from the pad 24-3 toward the bump 23-3. The wiring layer 32 includes a first end disposed on the upper end of the through hole 22-4, for example, connected to an internal circuit. The wiring layer 33 includes a first end disposed on the lower end of the bonding pad 24-4, for example, connected to an internal circuit. In the example of FIG. 5 , the bumps 23-1 and the pads 24-1 are respectively disposed at positions with distances d1 and d5 from the end (right end) of the semiconductor substrate 20 in the +x direction. The bumps 23 - 2 and the pads 24 - 2 are respectively disposed at distances d2 and d6 from the right end of the semiconductor substrate 20 . The bumps 23 - 3 and the bonding pads 24 - 3 are respectively disposed at distances d3 and d7 from the right end of the semiconductor substrate 20 . The bumps 23 - 4 and the bonding pads 24 - 4 are respectively disposed at distances d4 and d8 from the right end of the semiconductor substrate 20 . Furthermore, the distances d1 and d5, the distances d2 and d6, the distances d3 and d7, or the distances d4 and d8 may be the same distance from each other, or may be different distances. Next, the configuration of the core chips CC1 and CC3 will be described. As shown in FIG. 6, the layout patterns of the core chips CC1 and CC3 are arranged in the same rectangular area as the core chips CC0 and CC2. Furthermore, the layout patterns of the core chips CC1 and CC3 and the layout patterns of the core chips CC0 and CC2 are designed to be mirror-symmetrical with respect to the opposing surfaces when the respective upper surfaces face each other. Specifically, for example, the layout patterns of the core chips CC1 and CC3 are mirror-symmetrical with respect to the layout patterns of the core chips CC0 and CC2 with respect to the yz plane. More specifically, the planes 0 to 3 are respectively provided at the four corners of the rectangular region (the upper right corner, the lower right corner, the upper left corner, and the lower left corner in FIG. 6 ). The other various circuits are arranged in the same manner as described in the core chips CC0 and CC2. The layout patterns of the core chips CC1 and CC3 configured as above, for example, as shown in FIG. 6 correspond to the symbol P2 obtained by mirror-symmetrically converting the symbol P1 shown in FIG. 4 with respect to the yz plane. That is, the layout patterns of the core chips CC1 and CC3 are consistent with the layout patterns of the core chips CC0 and CC2 by performing the same conversion as the conversion from the symbol P2 to the symbol P1. Also, as shown in FIG. 7 , an element layer 41 is provided on the upper surface of the semiconductor substrate 40 according to a layout pattern corresponding to the symbol P2 and a wiring pattern corresponding to the layout pattern. In addition, in FIG. 7, the description about the internal circuits other than the terminals T1a-T4a, the terminals T1b-T4b, and the logic circuits LGA and LGB is abbreviate|omitted for simplification. The semiconductor substrate 40 is provided with a plurality of through holes 42 (42-1, 42-2, 42-3, and 42-4) that function as TSVs. The exposed portions of the through holes 42-1 to 42-4 on the lower surface of the semiconductor substrate 40 are respectively provided with a plurality of bumps 43 (43-1, 43-2, 43-3, and 43-4). On the upper surface of the element layer 41, a plurality of pads 44 (44-1, 44-2, 44-3, and 44-4) that function as the terminals T1a to T4a are provided. The upper surface of the pad 44 is exposed on the upper surface of the element layer 41 . In the element layer 41, the logic element layers 45 and 46 and wiring layers 47-53 which function as logic circuits LGA and LGB are provided. The wiring layer 47 includes a first end disposed on the upper end of the through hole 42-1, and a second end disposed on the lower end of the bonding pad 44-1. The wiring layer 47 is connected to, for example, an internal circuit. The wiring layers 48 and 49 are connected between the through holes 42-2, the logic element layer 45, and the pads 44-2 using a wiring pattern different from that of the wiring layers 28 and 29 in FIG. 5 . Specifically, the wiring layer 48 includes a first end provided on the upper end of the through hole 42 - 2 and a second end provided on the upper end of the logic element layer 45 . The wiring layer 48 is connected to, for example, an internal circuit. The wiring layer 49 includes a first end provided on the lower end of the logic element layer 45 and a second end provided on the lower end of the bonding pad 44-2. The logic element layer 45 includes a lower end having a function as an input end, and an upper end having a function as an output end. That is, the logic element layer 45 functions as a logic circuit LGA that outputs a signal input from the pad 44-2 to the bump 43-2. The wiring layers 50 and 51 are connected between the through holes 42-3, the logic element layer 46, and the pads 44-3 by using a wiring pattern different from that of the wiring layers 30 and 31 in FIG. 5 . Specifically, the wiring layer 50 includes a first end provided on the upper end of the through hole 42 - 3 and a second end provided on the upper end of the logic element layer 46 . The wiring layer 50 is connected to, for example, an internal circuit. The wiring layer 51 includes a first end provided on the lower end of the logic element layer 46 and a second end provided on the lower end of the bonding pad 44-3. The logic element layer 46 includes a lower end having a function as an output end, and an upper end having a function as an input end. That is, the logic element layer 46 functions as a logic circuit LGB that outputs a signal input from the bump 43-3 toward the pad 44-3. The wiring layer 52 includes a first end disposed on the upper end of the through hole 42-4, for example, connected to an internal circuit. The wiring layer 53 includes a first end disposed on the lower end of the pad 44-4, for example, connected to an internal circuit. As described above, the layout patterns of the core chips CC1 and CC3 are in a mirror-symmetrical relationship with the layout patterns of the core chips CC0 and CC2 with respect to the yz plane. Therefore, in the example of FIG. 7 , the bumps 43 - 1 and the pads 44 - 1 are respectively disposed at positions with distances d1 and d5 from the end (left end) of the semiconductor substrate 40 in the −x direction. The bump 43 - 2 and the bonding pad 44 - 2 are respectively disposed at distances d2 and d6 from the left end of the semiconductor substrate 40 . The bumps 43 - 3 and the pads 44 - 3 are respectively disposed at distances d3 and d7 from the left end of the semiconductor substrate 40 . The bumps 43 - 4 and the pads 44 - 4 are respectively disposed at distances d4 and d8 from the left end of the semiconductor substrate 40 . By being constructed as above, the chip designs of the core chips CC1 and CC3 include the layout patterns that are mirror-symmetrical to the layout patterns of the core chips CC0 and CC2, and the wiring patterns that are different from the wiring patterns of the core chips CC0 and CC2. 1. 1. 4. 3. About the laminated structure of the core chip group Next, the laminated structure of the core chip group of the semiconductor memory device according to the first embodiment will be described with reference to FIG. 8 . 8 is a cross-sectional view for explaining the laminated structure of the core chip group of the semiconductor memory device of the first embodiment. FIG. 8 shows a structure in which the core wafers CC0 to CC3 shown in FIGS. 5 and 7 are stacked in this order. As shown in FIG. 8 , the upper surface of the core chip CC0 is bonded to the upper surface of the core chip CC1. As described above, the layout pattern of the core chip CC0 and the layout pattern of the core chip CC1 are designed to be mirror-symmetrical with respect to the opposing surfaces of the upper surfaces of each other. Therefore, the positions of the bonding pads 24-1 to 24-4 of the core chip CC0 are aligned with the positions of the bonding pads 44-1 to 44-4 of the core chip CC1, respectively. In addition, the lower surface of the core chip CC1 is bonded to the lower surface of the core chip CC2. As described above, the layout pattern of the core chip CC1 and the layout pattern of the core chip CC2 are designed to be mirror-symmetrical with respect to the opposing surfaces of the upper surfaces of each other. Therefore, the positions of the bumps 43-1 to 43-4 of the core chip CC1 are aligned with the positions of the bumps 23-1 to 23-4 of the core chip CC2, respectively. In addition, the upper surface of the core chip CC2 is bonded to the upper surface of the core chip CC3. As described above, the layout pattern of the core chip CC2 and the layout pattern of the core chip CC3 are designed to be mirror-symmetrical with respect to the opposing surfaces of the upper surfaces of each other. Therefore, the positions of the bonding pads 24-1 to 24-4 of the core chip CC2 are aligned with the positions of the bonding pads 44-1 to 44-4 of the core chip CC3, respectively. With the above configuration, the core chips CC0-CC3 can form the signal paths SL1-SL4 which can communicate with each internal circuit. As described above, the wiring patterns of the core chips CC0 and CC2 and the wiring patterns of the core chips CC1 and CC3 are different from each other. Therefore, in the signal path SL2, the input-output relationship between the logic element layer 25 and the logic element layer 45 is matched. In addition, in the signal path SL3, the input-output relationship between the logic element layer 26 and the logic element layer 46 is matched. In addition, in the following description, the group of core chips CC0 and CC1 and the group of core chips CC2 and CC3 include two semiconductor substrates and the upper surfaces of the element layers are bonded to each other as a "chip". Set CS". In the first embodiment, the wafer set CS of the group including the core chips CC0 and CC1 has the same configuration as the wafer set CS of the group including the core chips CC2 and CC3. 1. 2. About the manufacturing method Next, the manufacturing method of the semiconductor memory device of the first embodiment will be described. 1. 2. 1. Outline of the manufacturing method First, the outline of the manufacturing method of the semiconductor memory device of the first embodiment will be described. FIG. 9 is a schematic diagram for explaining the outline of the manufacturing method of the semiconductor memory device of the first embodiment. FIG. 10 is a flowchart for explaining the method of manufacturing the semiconductor memory device of the first embodiment. As shown in FIG. 9 , a plurality of wafer sets CS are cut out from two wafers W1 and W2 that are attached to each other. The outline thereof will be described with reference to FIG. 10 . As shown in FIG. 10 , in step ST10 , the device layers 21 and 41 are transferred on the upper surfaces of each of the wafers W1 and W2 by using a pre-designed mask set by photolithography. That is, the one mask set can define the chip designs (layout patterns and wiring patterns) of the core chips CC0 to CC3. In addition, in the following description, a part corresponding to one wafer set CS in the two wafers W1 and W2 is also referred to as a wafer set CS in a state before being diced from the wafers W1 and W2. In step ST20, the two wafers W1 and W2 on which the element layers are formed are bonded together. Specifically, the wafers W1 and W2 are attached in such a manner that the element layers disposed on the respective upper surfaces face each other. In step ST30, the lower surfaces of the bonded wafers W1 and W2 are ground. Specifically, one of the bonded wafers W1 and W2 (for example, wafer W2 ) is made to function as a support substrate, and the other (for example, wafer W1 ) is polished. In addition, during polishing of the wafer W2, it may be fixed on the side of the wafer W1 by a dummy semiconductor substrate that functions as a support substrate. The dummy semiconductor substrate is removed, for example, after grinding or after the wafer screening step described below. As a result of the polishing, the lower ends of the through holes 22 and the lower ends of the through holes 42 are exposed on the polished surfaces of each of the wafers W1 and W2. On the exposed portions of the through holes 22 and 42, bumps 23 and 43 are provided. In step ST40, the defective core wafer area is detected by the wafer screening step. Specifically, the pin contact terminals of the die sorter are brought into contact (probe) with the bumps 23 or 43 provided in step ST20, and it is checked whether the required communication can be performed. As a result of the detection, the wafer set CS capable of performing the required communication at all the pin contact positions is determined as no defect (good product) detected. On the other hand, the wafer set CS including the portion in which the required communication cannot be performed is determined to be defective (defective product). In step ST50, wafers W1 and W2 are divided into wafer sets CS units by a dicing step. Thereafter, the wafer sets CS judged to be good products in step ST40 are screened and stacked. Thereby, the core wafer group 11 is provided. Furthermore, in combination with the interface chip 10 manufactured separately, the manufacture of the semiconductor memory device 3 is finally completed. 1. 2. 2. Formation of wafers Next, a method of forming an element layer on a wafer and a method of bonding two wafers in the manufacturing method of the semiconductor memory device of the first embodiment will be described. 11 is a schematic diagram for explaining a method of forming an element layer on a wafer in the semiconductor memory device of the first embodiment. FIG. 12 is a schematic view for explaining the bonding method of two wafers in the semiconductor memory device of the first embodiment. That is, FIGS. 11 and 12 correspond to steps ST10 and ST20 in FIG. 10 , respectively. In FIGS. 11 and 12 , the layout patterns transferred onto the wafers W1 and W2 using the mask set MS1 are schematically shown. Specifically, in FIGS. 11 and 12 , the layout pattern explained in FIGS. 4 and 5 is represented by the symbol P1 , and the layout pattern explained in FIGS. 6 and 7 is represented by the symbol P2 . In the following description, the layout pattern illustrated in FIGS. 4 and 5 is referred to as a layout pattern P1, and the layout pattern illustrated in FIGS. 6 and 7 is referred to as a layout pattern P2. As shown in FIG. 11 , the mask set MS1 is alternately arranged in layout patterns P1 and P2 along the x-direction. Furthermore, the mask set MS1 is arranged so that both ends along the x-direction have different layout patterns. Also, as shown in FIG. 12 , the wafers W1 and W2 are, for example, folded in half with respect to the yz plane from the state of being aligned in the x direction on the xy plane. Thereby, for example, in FIG. 12 , the area AreaA in the upper left corner of the wafer W1 on which the layout pattern P1 is transferred and the area AreaB in the upper right corner of the wafer W2 on which the layout pattern P2 is transferred are bonded. The same is true for other areas, the area on the wafer W1 to which the layout pattern P1 is transferred is bonded to the area on the wafer W2 to which the layout pattern P2 is transferred, and the area on which the layout pattern P2 is transferred on the wafer W1 The area on which the layout pattern P1 is transferred on the bonding wafer W2. Also, in the mask set MS1, the layout patterns P1 and P2 correspond to the wiring pattern shown in FIG. 5 and the wiring pattern shown in FIG. 7, respectively. By bonding the wafers W1 and W2 on which the mask set MS1 as described above is transferred, a plurality of structures capable of functioning as the wafer set CS described in FIG. 8 can be obtained. Furthermore, in FIGS. 11 and 12 , the case where one mask set MS1 is used has been described, but the present invention is not limited to this. For example, wafers W1 and W2 may also use different mask sets. Specifically, for example, it is assumed that only the layout pattern P1 is transferred to the wafer W1, and that only the layout pattern P2 is transferred to the wafer W2. 1. 2. 3. About wafer screening Next, the method of wafer screening in the manufacturing method of the semiconductor memory device of the first embodiment will be described. FIG. 13 is a schematic diagram for explaining the detection of the wafer screening of the semiconductor memory device of the first embodiment. That is, FIG. 13 corresponds to step ST40 in FIG. 10 . As shown in FIG. 13 , the wafer screening of the wafer W2 can be implemented, for example, by bringing the probe terminals of a wafer screening machine (not shown) into contact with the bumps 43 provided on the lower surface of the wafer W2. As described above, the mask sets MS1 are alternately arranged in the layout patterns P1 and P2 along the x-direction. Therefore, on the lower surface of the wafer W2, according to the mask set MS1, the bumps 43 arranged with the arrangement patterns B1 and B2 different from each other are alternately arranged in the x direction. More specifically, the arrangement patterns B1 and B2 are mirror-symmetrical with respect to the yz plane. Therefore, the needle contact position applicable to the arrangement pattern B1 cannot be applied to the arrangement pattern B2. In the first embodiment, regarding the repeating unit of the needle contact position DS1 of the wafer screening machine (represented as DSU in FIG. 13 ), a group of two different layout patterns adjacent to each other in the x direction can be defined as one. unit. That is, the repeating unit DSU of the needle contact position DS1 of the wafer screening machine corresponds to the group of the arrangement patterns B1 and B2. By defining the pin contact position DS1 of the wafer screening machine as defined above, it is possible to use one repeating unit DSU of the pin contact position of the wafer screening machine for the wafer W2 having different layout patterns P1 and P2 arranged in the x-direction. Perform wafer screening. Furthermore, when only the layout pattern P1 is transferred to the wafer W1, and only the layout pattern P2 is transferred to the wafer W2, the arrangement pattern of the bumps 63 arranged on the same wafer is in the chip set CS unit. All the same. Therefore, the size of the repeating unit DSU applied to the pin contact position of the wafer screener on the same wafer can be set as half of that in the case of FIG. 13 . 1. 3 Effects of the present embodiment According to the first embodiment, the manufacturing cost of the core chip group can be reduced. This effect will be described below. As a configuration capable of improving the characteristics of a memory product, a configuration including a core chip group formed by laminating core chips having TSVs is known. In general, the core chip group can be formed by stacking core chips obtained by dicing one wafer so that the upper surfaces and the lower surfaces of each other are in contact with each other. In the first embodiment, the upper surfaces of the two wafers W1 and W2 are bonded to each other before dicing. Then, the wafer set CS is obtained by simultaneously dicing the bonded two wafers W1 and W2. The core wafer group 11 is provided by stacking the wafer set CS. Both the part corresponding to the wafer W1 and the part corresponding to the wafer W2 of the chip set CS function as one core chip CC. Thereby, four core wafers CC are laminated every time two wafer sets CS are laminated. Therefore, compared with the case where the core wafers CC are layered one by one after the wafers W1 and W2 are diced one by one, the steps required for layering can be greatly reduced. Therefore, the manufacturing cost can be reduced. Also, the bumps of the two wafer sets CS are connected to each other. Therefore, in the manufacturing step, two bumps can be regarded as one bump. Thereby, the size of the bump required for the connection between the chip sets CS can be controlled substantially to the size of about one bump. Therefore, the height in the stacking direction of the wafer cluster can be reduced, thereby reducing the manufacturing cost. In addition, wafers W1 and W2 form device layers by the same mask set MS1. The mask set MS1 includes two layout patterns P1 and P2 that are different from each other. The layout patterns P1 and P2 are alternately arranged. Therefore, when the wafers W1 and W2 are bonded together, the element layer on which the layout pattern P1 is transferred and the element layer on which the layout pattern P2 is transferred can be bonded together. Furthermore, the cost required for the design of the mask set MS1 is equivalent to the cost of designing the layout patterns P1 and P2. However, the layout patterns P1 and P2 have a mirror-symmetrical relationship with each other. Therefore, the layout pattern P2 is substantially included in the design cost of the layout pattern P1. Therefore, the design cost of the mask set MS1 can be controlled to be equal to the design cost of one core chip CC. Also, as described above, the layout patterns P1 and P2 have a mirror-symmetrical relationship with each other. Therefore, when the wafers W1 and W2 are bonded together, the positions and uses of the terminals T1b to T4b provided on the wafer W1 and the terminals T1a to T4a provided on the wafer W2 are the same. Thereby, the connection between the wafers W1 and W2 can be matched. In addition, when the wafers W1 and W2 are bonded together, the functions of the internal circuits of the core chip CC provided on the wafer W1 and the functions of the internal circuits of the core chip CC provided on the wafer W2 are arranged in the same lamination direction. the location. Therefore, a signal required for the core chip CC provided on the wafer W1 and a signal required for the core chip CC provided on the wafer W2 can be communicated with one signal path. Thereby, the number of signal paths to be provided can be reduced. Furthermore, the arrangement of the terminals of the portion on the wafer where the layout pattern P1 is transferred and the portion where the layout pattern P2 is transferred are different from each other. In the first embodiment, the probe terminals used at the time of wafer screening are arranged differently for two different layout patterns P1 and P2 adjacent to each other. Furthermore, the arrangement of terminals including the two different arrangements is defined as a repeating unit DSU. Therefore, even when different layout patterns P1 and P2 are transferred onto the same wafer, the wafer screening step can be performed without problems. Furthermore, as described above, since the layout patterns P1 and P2 have a mirror-symmetrical relationship with each other, if the wafers W1 and W2 are bonded together, the orientations of the input and output terminals of the logic circuit are opposite to each other. In the first embodiment, the layout patterns P1 and P2 correspond to mutually different wiring patterns. Specifically, in one wiring pattern, if the input end and output end of the logic circuit are connected to the pad and the bump, respectively, in another wiring pattern, the input end and the output end of the logic circuit are respectively connected to the bump blocks and pads. Therefore, when the wafers W1 and W2 are bonded together, the input-output relationship between the logic circuit provided in the wafer W1 and the logic circuit provided in the wafer W2 can be matched. 1. 4. Variation of the first embodiment Furthermore, the semiconductor memory device of the first embodiment is not limited to the above-described example, and various modifications can be applied. For example, in the first embodiment, the case where the two layout patterns are mirror-symmetrical with respect to the yz plane has been described, but the present invention is not limited to this, and may be mirror-symmetrical with respect to the xz plane. FIG. 14 is a plan view illustrating a layout pattern of a core chip of a semiconductor memory device according to a modification of the first embodiment. In FIG. 14, the structure common to the core chips CC1 and CC3 is shown. In addition, about the core chips CC0 and CC2, it is set as the structure similar to 1st Embodiment, and the description is abbreviate|omitted. As shown in FIG. 14, the layout patterns of the core chips CC1 and CC3 are arranged in the same rectangular area as the core chips CC0 and CC2. Also, the layout patterns of the core chips CC1 and CC3 are mirror-symmetrical with respect to the layout patterns of the core chips CC0 and CC2 with respect to the xz plane. More specifically, plane 0 to plane 3 are respectively arranged at four corners (lower left corner, upper left corner, lower right corner, and upper right corner in FIG. 14 ) of the rectangular region. The other various circuits are configured in the same manner as described in the core chips CC0 and CC2. The layout pattern of the core chips CC1 and CC3 configured as above, for example, as shown in FIG. 14 corresponds to the symbol P3 obtained by mirror-symmetrically converting the symbol P1 shown in FIG. 4 with respect to the xz plane. That is, the layout patterns of the core chips CC1 and CC3 are consistent with the layout patterns of the core chips CC0 and CC2 by performing the same conversion as the conversion from the symbol P3 to the symbol P1. Next, a method of forming an element layer on a wafer and a method of bonding two wafers in the method of manufacturing a semiconductor memory device according to a modification of the first embodiment will be described. FIG. 15 is a schematic view for explaining a method of forming an element layer on a wafer in the semiconductor memory device according to a modification of the first embodiment. FIG. 16 is a schematic diagram for explaining a method of bonding two wafers in the semiconductor memory device according to a modification of the first embodiment. That is, FIGS. 15 and 16 correspond to steps ST10 and ST20 in FIG. 10 , respectively. In FIGS. 15 and 16, the layout patterns transferred onto wafers W1 and W2 using mask set MS2 are schematically shown. Specifically, in FIGS. 15 and 16 , the layout pattern illustrated in FIG. 4 is represented by the symbol P1 , and the layout pattern illustrated in FIG. 14 is represented by the symbol P3 . In the following description, the layout pattern illustrated in FIGS. 14 and 7 is referred to as a layout pattern P3. As shown in FIG. 15 , the mask set MS2 is alternately arranged in the layout patterns P1 and P3 along the y-direction. Furthermore, the mask set MS2 is arranged so that both ends along the y-direction have different layout patterns. Also, as shown in FIG. 16 , the wafers W1 and W2 are, for example, folded in half with respect to the xz plane from the state of being aligned in the y direction on the xy plane. Thereby, for example, in FIG. 16 , the area AreaA in the upper left corner of the wafer W1 on which the layout pattern P1 is transferred and the area AreaC in the lower left corner of the wafer W2 on which the layout pattern P3 is transferred are bonded. The same is true for other regions, the region on the wafer W1 where the layout pattern P1 is transferred is bonded to the region on the wafer W2 where the layout pattern P3 is transferred, and the region on the wafer W1 where the layout pattern P3 is transferred The area on which the layout pattern P1 is transferred on the bonding wafer W2. Also, in the mask set MS1, the layout patterns P1 and P3 correspond to the wiring pattern shown in FIG. 5 and the wiring pattern shown in FIG. 7, respectively. By bonding the wafers W1 and W2 on which the mask set MS2 as described above is transferred, a plurality of structures capable of functioning as the wafer set CS described in FIG. 8 can be obtained. Next, a method of wafer screening in the method of manufacturing a semiconductor memory device according to a modification of the first embodiment will be described. FIG. 17 is a schematic diagram for explaining the detection of the wafer screening of the semiconductor memory device of the modification of the first embodiment. That is, FIG. 17 corresponds to step ST40 in FIG. 10 . As described above, the mask set MS2 is alternately arranged in the layout patterns P1 and P3 along the y-direction. Therefore, as shown in FIG. 17, on the lower surface of the wafer W2, bumps 43 arranged with different arrangement patterns B1 and B3 are alternately arranged in the y direction according to the mask set MS2. Since the arrangement patterns B1 and B3 are mutually mirror-symmetrical with respect to the xz plane, the needle contact positions applicable to the arrangement pattern B1 cannot be applied to the arrangement pattern B3. Therefore, in the modification of the first embodiment, regarding the repeating unit DSU of the needle contact position DS2 of the wafer screening machine, a group of two different layout patterns adjacent to each other in the y direction can be defined as one unit. That is, the repeating unit DSU of the needle contact position DS2 of the wafer screening machine corresponds to the group of the arrangement patterns B1 and B3. By defining the pin contact position DS2 of the wafer screening machine as defined above, it is possible to use one repeating unit DSU of the pin contact position of the wafer screening machine for the wafer W2 arranged in the y-direction with different layout patterns P1 and P3 Perform wafer screening. 2. Second Embodiment Next, a semiconductor memory device according to a second embodiment will be described. The semiconductor memory device of the first embodiment is designed such that the layout patterns of the two core chips constituting the chip set are mirror-symmetrical with respect to the facing surfaces when the upper surfaces of the two face each other. The semiconductor memory device of the second embodiment is designed so that the layout patterns of the two core chips constituting the chip set are the same. Hereinafter, the same reference numerals are given to the same components as those of the first embodiment, and the description thereof will be omitted, and the parts different from those of the first embodiment will be described. 2. 1 About the structure The structure of the semiconductor memory device according to the second embodiment will be described. 2. 1. 1. Connection between core chips The connection between the core chips of the semiconductor memory device of the second embodiment will be described with reference to FIG. 18 . 18 is a circuit diagram for explaining an example of connection between core chips of the semiconductor memory device of the second embodiment. As shown in FIG. 18, each of the core chips CC0-CC3 includes terminals T1a, T4a, T5a, T6a, T7a, and T8a, and terminals T1b, T4b, T5b, T6b, T7b, and T8b. Moreover, each of the core chips CC0 to CC3 includes logic circuits LGA1, LGA2, LGB1, and LGB2. Since the connection of the terminals T1a and T1b and the terminals T4a and T4b is the same as that of the first embodiment, the description thereof will be omitted. The terminals T5a-T8a of the core chip CC0 are connected to the external interface chip 10 or the controller 2, for example. The terminals T5b-T8b of the core chip CC0 are respectively connected to the terminals T5a-T8a of the core chip CC1. The terminals T5b to T8b of the core chip CC1 are respectively connected to the terminals T5a to T5a of the core chip CC2. The terminals T5b-T8b of the core chip CC2 are respectively connected to the terminals T5a-T8a of the core chip CC3. In each core chip CC, the terminals T5a and T5b, the terminals T6a and T6b, the terminals T7a and T7b, and the terminals 8a and T8b are connected through wirings provided inside each core chip CC. In the core chips CC0 and CC2, the logic circuit LGA1 is arranged on the wiring between the terminals T7a and T7b, and the logic circuit LGB1 is arranged on the wiring between the terminals T8a and T8b. The logic circuit LGA1 includes an input terminal connected to the terminal T7a and an output terminal connected to the terminal T7b. The logic circuit LGB1 includes an input terminal connected to the terminal T8b and an output terminal connected to the terminal T8a. In addition, in the core chips CC1 and CC3, the logic circuit LGA2 is provided on the wiring between the terminals T7a and T7b, and the logic circuit LGB2 is provided on the wiring between the terminals T8a and T8b. The logic circuit LGA2 includes an input terminal connected to the terminal T7a and an output terminal connected to the terminal T7b. The logic circuit LGB2 includes an input terminal connected to the terminal T8b and an output terminal connected to the terminal T8a. With the above configuration, signals can be sent and received from the terminal T5a of the core chip CC0 to the terminal T5b of the core chip CC3, and from the terminal T6a of the core chip CC0 to the terminal T6b of the core chip CC3, respectively. Signal paths SL5 and SL6 of each of CC3 function. The signal path SL5 is connected to the internal circuits in the core chips CC0 and CC2, but the internal circuits in the core chips CC1 and CC3 are cut off (skip the internal circuits). The signal path SL6 is connected to the internal circuits in the core chips CC1 and CC3, but bypasses the internal circuits in the core chips CC0 and CC2. Thereby, the internal circuits of each core chip CC can communicate signals with the controller 2 and the interface chip 10 via the signal paths SL5 or SL6. In addition, the signal path SL1 in 2nd Embodiment assumes the power supply etc. which are commonly supplied in each core chip CC, for example. In addition, from the terminal T7a of the core chip CC0 to the terminal T7b of the core chip CC3, the signals that can be processed by the logic circuit LGA1 or LGA2 of the core chip CCn (n is 0≦n≦2) can be sent to the core chip. The signal path SL7 of CC(n+1) functions. In addition, from the terminal T8a of the core chip CC0 to the terminal T8b of the core chip CC3 is a signal path SL8 that can transmit the signal processed by the logic circuit LGB1 or LGB2 of the core chip CC(n+1) to the core chip CCn. function. Furthermore, the terminals T5a to T8a of the core chip CC0 can send and receive various signals with the interface chip 10 or the controller 2 . Furthermore, the logic circuits LGA1 and LGA2 may be different from each other, or even though they are the same circuit, any one of them does not perform a logic operation substantially. Similarly, the logic circuits LGB1 and LGB2 may be different from each other, or may be the same circuit, but any one of them does not perform a logic operation substantially. That is, signal path SL7 includes signal path SL2, and signal path SL8 includes signal path SL3. In addition, the logic circuits LGA1 , LGA2 , LGB1 , and LGB2 may or may not be connected to the internal circuit. 2. 1. 2 About the structure of the core chip Next, the structure of the core chip of the semiconductor memory device of the second embodiment will be described. The top views of the core chips CC0 to CC3 in the second embodiment are the same as the top views of the core chips CC0 and CC2 shown in FIG. 4 of the first embodiment. However, the layout pattern of the core chip CC in the second embodiment differs from the layout pattern of the core chip CC in the first embodiment in the arrangement of terminals and logic circuits not shown in FIG. 4 . 19 and 20 are cross-sectional views for explaining the layout pattern and the wiring pattern of the core chip of the semiconductor memory device of the second embodiment. 19 and 20 correspond to the cross-sections along the line V-V shown in FIG. 4 . 19 shows a configuration common to core chips CC0 and CC2, and FIG. 20 shows a configuration common to core chips CC1 and CC3. First, the configuration of the core chips CC0 and CC2 will be described. The layout pattern shown in FIG. 19 corresponds to the symbol P4 which is different from the symbol P1 shown in FIG. 4 . As shown in FIG. 19 , the element layer 61 is provided on the upper surface of the semiconductor substrate 60 according to the layout pattern corresponding to the symbol P4 and the wiring pattern corresponding to the layout pattern. In addition, in FIG. 19, the description about the internal circuits other than terminals T5a-T8a, T5b-T8b and logic circuits LGA1 and LGB1 is abbreviate|omitted for simplification. The semiconductor substrate 60 is provided with a plurality of through holes 62L (62L-1, 62L-2, 62L-3, and 62L-4) and 62R (62R-1, 62R-2, 62R-3) that function as TSVs , and 62R-4). In the core chips CC0 and CC2, the exposed portions of the through holes 62L-1 to 62L-4 on the lower surface of the semiconductor substrate 60 are provided with bumps 63L-1 that function as terminals T5a, T7a, T8a, and T4a, respectively , 63L-2, 63L-3, and 63L-4. The exposed portions of the through holes 62R-1 to 62R-4 on the lower surface of the semiconductor substrate 60 are provided with bumps 63R-1, 63R-2, 63R-3 that function as the terminals T6a, T8a, T7a, and T4a, respectively , and 63R-4. On the upper surface of the element layer 61, a plurality of pads 64L (64L-1, 64L-2, 64L-3, and 64L-4) that function as terminals T5b, T7b, T8b, and T4b are provided. Further, on the upper surface of the element layer 61, a plurality of pads 64R (64R-1, 64R-2, 64R-3, and 64R-4) functioning as terminals T6b, T8b, T7b, and T4b are provided. The upper surface of the bonding pad 64 is exposed on the upper surface of the element layer 61 . Logic element layers 65 to 67 and wiring layers 68 to 80 that function as logic circuits LGA1 , LGB1 , and LGB1 are provided in the element layer 61 , respectively. The wiring layer 68 includes a first end disposed on the upper end of the through hole 62L-1, and a second end disposed on the lower end of the pad 64L-1. The wiring layer 68 is connected to, for example, an internal circuit. The wiring layer 69 includes a first end disposed on the upper end of the through hole 62R-1, and a second end disposed on the lower end of the pad 64R-1. For example, the wiring layer 69 is not connected to the internal circuit, and the element layer 61 is skipped. The wiring layer 70 includes a first end disposed on the upper end of the through hole 62L- 2 , and a second end disposed on the lower end of the logic element layer 65 . The wiring layer 70 is connected to, for example, an internal circuit. The wiring layer 71 includes a first end provided on the upper end of the logic element layer 65 and a second end provided on the lower end of the pad 64L-2. The logic element layer 65 includes a lower end having a function as an input end, and an upper end having a function as an output end. That is, the logic element layer 65 functions as the logic circuit LGA1 that outputs the signal input from the bump 63L-2 toward the pad 64L-2. The wiring layer 72 includes a first end disposed on the upper end of the through hole 62R- 2 , and a second end disposed on the lower end of the logic element layer 66 . The wiring layer 73 includes a first end provided on the upper end of the logic element layer 66 and a second end provided on the lower end of the pad 64R- 2 . The wiring layers 72 and 73 are not connected to the internal circuit, for example, and the element layer 61 is skipped. The logic element layer 66 includes a lower end having a function as an output end, and an upper end having a function as an input end. That is, the logic element layer 66 functions as the logic circuit LGB1 that outputs the signal input from the pad 64R- 2 to the bump 63R- 2 . The wiring layer 74 includes a first end disposed on the upper end of the through hole 62L-3, and a second end disposed on the lower end of the logic element layer 67. The wiring layer 75 includes a first end provided on the upper end of the logic element layer 67 and a second end provided on the lower end of the pad 64L-3. The wiring layers 74 and 75 are not connected to the internal circuit, for example, and the element layer 61 is skipped. The logic element layer 67 includes a lower end having a function as an output end, and an upper end having a function as an input end. That is, the logic element layer 67 functions as the logic circuit LGB1 that outputs the signal input from the pad 64L-3 toward the bump 63L-3. The wiring layer 76 includes a first end disposed on the upper end of the through hole 62R-3, and a second end disposed on the lower end of the bonding pad 64R-3. The wiring layer 76 is connected to, for example, an internal circuit. The wiring layer 77 includes a first end disposed on the upper end of the through hole 62L-4, for example, connected to an internal circuit. The wiring layer 78 includes a first end disposed on the lower end of the pad 64L-4, for example, connected to an internal circuit. The wiring layer 79 includes a first end disposed on the upper end of the through hole 62R-4, for example, connected to an internal circuit. The wiring layer 80 includes a first end disposed on the lower end of the pad 64R- 4 , for example, connected to an internal circuit. In the example of FIG. 19 , the bumps 63L and 63R are disposed at symmetrical positions with respect to the center of the width of the semiconductor substrate 60 along the x direction (hereinafter referred to as “the center of the semiconductor substrate 60”). Specifically, the bumps 63L- 1 and 63R- 1 are provided at positions distanced d9 from the center of the semiconductor substrate 60 . The bumps 63L- 2 and 63R- 2 are provided at positions at a distance d10 from the center of the semiconductor substrate 60 . The bumps 63L- 3 and 63R- 3 are provided at positions at a distance d11 from the center of the semiconductor substrate 60 . The bumps 63L- 4 and 63R- 4 are provided at positions at a distance d12 from the center of the semiconductor substrate 60 . Also, the pads 64L and 64R are disposed at positions symmetrical with respect to the center of the semiconductor substrate 60 . Specifically, the bonding pads 64L- 1 and 64R- 1 are provided at positions at a distance d13 from the center of the semiconductor substrate 60 . The bonding pads 64L- 2 and 64R- 2 are disposed at a distance d14 from the center of the semiconductor substrate 60 . The bonding pads 64L- 3 and 64R- 3 are provided at positions at a distance d15 from the center of the semiconductor substrate 60 . The bonding pads 64L- 4 and 64R- 4 are disposed at a distance d16 from the center of the semiconductor substrate 60 . Furthermore, the distances d9 and d13, the distances d10 and d14, the distances d11 and d15, or the distances d12 and d16 may be the same distance from each other, or may be different distances. Next, the configuration of the core chips CC1 and CC3 will be described. As shown in FIG. 20, the layout patterns of the core chips CC1 and CC3 are consistent with the layout patterns of the core chips CC0 and CC2. That is, the layout patterns of the core chips CC1 and CC3 correspond to the symbol P4. Therefore, in the core chips CC1 and CC3, the bumps 63L and 63R are symmetrical with respect to the center of the semiconductor substrate 60, and are disposed at the same positions as the bumps 63L and 63R in the core chips CC0 and CC2. Also, in the core chips CC1 and CC3, the pads 64L and 64R are symmetrical with respect to the center of the semiconductor substrate 60, and are disposed at the same positions as the pads 64L and 64R in the core chips CC0 and CC2. Furthermore, in the core chips CC1 and CC3, the functions of the bumps 63, the bonding pads 64, and the logic element layers 65-67 are different from those of the core chips CC0 and CC2. Specifically, in the core chips CC1 and CC3, the bumps 63L-1 to 63L-4 function as terminals T6b, T8b, T7b, and T4b, respectively. The bumps 63R-1 to 63R-4 function as terminals T5b, T7b, T8b, and T4b, respectively. The pads 64L-1 to 64L-4 function as terminals T6a, T8a, T7a, and T4a, respectively. The pads 64R-1 to 64R-4 function as terminals T5a, T7a, T8a, and T4a, respectively. The logic element layers 65 to 67 function as logic circuits LGB2, LGA2, and LGA2, respectively. By being constructed as above, the chip designs of the core chips CC1 and CC3 include the same layout patterns and the same wiring patterns as those of the core chips CC0 and CC2. That is, the core chips CC0-CC3 contain the same chip design. 2. 1. 3. About the laminated structure of the core chip group Next, the laminated structure of the core chip group of the semiconductor memory device according to the second embodiment will be described with reference to FIG. 21 . FIG. 21 is a cross-sectional view for explaining the laminated structure of the core chip group of the semiconductor memory device of the second embodiment. FIG. 21 shows a structure in which the core wafers CC0 to CC3 shown in FIGS. 19 and 20 are laminated in this order. As shown in FIG. 21 , the top surface of the core chip CC0 and the top surface of the core chip CC2 are respectively attached to the top surface of the core chip CC1 and the top surface of the core chip CC3. In addition, the lower surface of the core chip CC1 is bonded to the lower surface of the core chip CC2. As described above, in the core chips CC0 to CC4, the bumps 63L and 63R are disposed at positions symmetrical to each other with respect to the center of the semiconductor substrate 60 . Also, the pads 64L and 64R are provided at positions symmetrical to each other with respect to the center of the semiconductor substrate 60 . Therefore, the positions of the bonding pads 64L-1 to 64L-4 and 64R-1 to 64R-4 of the core chips CC0 and CC2 are respectively the same as those of the bonding pads 64L-1 to 64L-4 and 64R-1 of the core chips CC1 and CC2, respectively. The position of ~64R-4 is aligned. In addition, the positions of the bumps 63L-1 to 63L-4 and 63R-1 to 63R-4 of the core chip CC1 are respectively the same as those of the bumps 63L-1 to 63L-4 and 63R-1 to 63R-4 of the core chip CC2. position alignment. With the above configuration, the core chips CC0 to CC3 form the signal paths SL4 to SL8 that can communicate with each other. 2. 2. About the manufacturing method Next, the manufacturing method of the semiconductor memory device of the second embodiment will be described. 2. 2. 1. About wafer formation The method of forming the element layer on the wafer and the method of laminating two wafers in the method of manufacturing the semiconductor memory device of the second embodiment will be described. Fig. 22 is a schematic diagram for explaining a method of forming an element layer on a wafer in the semiconductor memory device of the second embodiment. FIG. 22 corresponds to step ST10 in FIG. 10 . In FIG. 22, the layout pattern transferred onto wafers W1 and W2 using mask set MS3 is schematically shown. In the second embodiment, as described above, the core chips CC0 to CC3 are formed by the same chip design. Therefore, as shown in FIG. 22, the mask set MS3 is arranged in the same layout pattern P4. For example, the wafers W1 and W2 can be attached by folding them in half with respect to the yz plane from the state of being aligned in the x direction on the xy plane, as in FIG. 12 in the first embodiment, or as in the modification of the first embodiment. In FIG. 16, it is likewise folded in half with respect to the xz plane from the state of being aligned in the y direction on the xy plane. By bonding the wafers W1 and W2 on which the mask set MS3 is transferred as described above, a plurality of structures capable of functioning as the wafer set CS described in FIG. 21 can be obtained. 2. 2. 2. About wafer screening Next, a method of wafer screening in the manufacturing method of the semiconductor memory device of the second embodiment will be described. FIG. 23 is a schematic view for explaining the detection of the wafer screening of the semiconductor memory device of the second embodiment. That is, FIG. 23 corresponds to step ST40 in FIG. 10 . As shown in FIG. 23 , the wafer screening of the wafer W2 can be implemented, for example, by bringing the probe terminals of a wafer screening machine (not shown) into contact with the bumps 63 provided on the lower surface of the wafer W2. As described above, the mask set MS3 is similarly arranged in the same layout pattern P4. Therefore, on the lower surface of the wafer W2, the bumps 63 arranged by the arrangement pattern B4 corresponding to the layout pattern P4 are similarly provided in accordance with the mask set MS3. Therefore, in the second embodiment, about the repeating unit DSU of the needle contact position DS3 of the wafer screening machine, one layout pattern can be defined as one unit. That is, the repeating unit DSU of the needle contact position DS3 of the wafer screening machine corresponds to the arrangement pattern B4. By defining the pin contact position DS3 of the wafer screening machine as defined above, wafer screening can be performed using one repeating unit DSU of the pin contact position of the wafer screening machine for wafers W2 arranged with the same wafer design. 2. 3. Effects of the present embodiment In the second embodiment, the wafers W1 and W2 are formed by the same mask set MS3 to form element layers. The mask set MS3 is likewise aligned with the same chip design. Thereby, the mask set MS3 can be designed only by designing the layout pattern and the wiring pattern of one core chip CC. Therefore, the manufacturing cost can be reduced. Furthermore, in the layout pattern of the second embodiment, bumps 63 and pads 64 are provided at positions symmetrical with respect to the center of the semiconductor substrate. Therefore, when the wafers W1 and W2 are bonded together, the positions of the terminals of each other are aligned. Thereby, the connection between the wafers W1 and W2 can be aligned. Furthermore, in the second embodiment, when the wafers W1 and W2 are bonded together, the internal circuit of the core chip CC0 provided on the wafer W1 and the internal circuit of the core chip CC provided on the wafer W2 are separated. The functions are arranged in different positions in the stacking direction. Therefore, there is a possibility that the signal required in the core chip CC disposed on the wafer W1 and the signal required in the core chip CC disposed on the wafer W2 cannot be communicated using the same signal path. Therefore, in the second embodiment, a signal path SL5 for connecting to the internal circuits of the core chips CC0 and CC2 and a signal path SL6 for connecting to the internal circuits of the core chips CC1 and CC3 are provided. That is, in the signal path SL5, the signal is transmitted and received to the core chips CC0 and CC2, and the core chips CC1 and CC3 skip the signal. In the signal path SL6, the signal is sent and received to the core chips CC1 and CC3, and the core chips CC0 and CC2 skip the signal. Thereby, although the number of signal paths provided on the wafers W1 and W2 increases, the required signals can be sent and received to each core chip CC using the same chip design. 2. 4. First modification of the second embodiment In addition, the semiconductor memory device of the second embodiment is not limited to the above-mentioned example, and various modifications can be applied. In the second embodiment, the case where the same chip design is applied to the core chips CC0 and CC1 has been described, but it is not limited to this. For example, it is also possible to apply the same layout pattern to the core chips CC0 and CC1 while applying different wiring patterns. This situation may occur when, for example, logic circuits disposed in left-right symmetrical positions in the core chip CC input and output signals in the same direction. 24 and 25 are cross-sectional views for explaining the layout pattern and the wiring pattern of the core chip of the semiconductor memory device according to the first modification of the second embodiment. In FIG. 24, the configuration common to the core chips CC0 and CC2 is shown, and in FIG. 25, the configuration common to the core chips CC1 and CC3 is shown. The layout pattern shown in FIG. 24 corresponds to the symbol P5 which is different from the symbol P4 shown in FIG. 19 . As shown in FIG. 24 , in the first modification of the second embodiment, the core chips CC0 and CC2 include a logic element layer 66A instead of the logic element layer 66 . That is, the wiring layer 72 includes a first end provided on the upper end of the through hole 62R- 2 and a second end provided on the lower end of the logic element layer 66A. The wiring layer 73 includes a first end provided on the upper end of the logic element layer 66A, and a second end provided on the lower end of the pad 64R- 2 . The logic element layer 66A includes a lower end having a function as an input end, and an upper end having a function as an output end. That is, the logic element layer 66A functions as the logic circuit LGA1 that outputs the signal input from the bump 63R- 2 toward the pad 64R- 2 . Also, as shown in FIG. 25, the layout patterns of the core chips CC1 and CC3 correspond to the symbol P5 similarly to the core chips CC0 and CC2. However, the core chips CC1 and CC3 include different wiring patterns from the core chips CC0 and CC2. Specifically, the core chips CC1 and CC3 include wiring layers 70A to 73A in place of the wiring layers 70 to 73 . The wiring layer 70A includes a first end disposed on the upper end of the through hole 62L- 2 , and a second end disposed on the upper end of the logic element layer 65 . The wiring layer 71A includes a first end provided on the lower end of the logic element layer 65 and a second end provided on the lower end of the pad 64L-2. That is, the logic element layer 65 functions as the logic circuit LGA2 that outputs the signal input from the pad 64L-2 toward the bump 63L-2. The wiring layer 72A includes a first end provided on the upper end of the through hole 62R- 2 , and a second end provided on the upper end of the logic element layer 66A. The wiring layer 73A includes a first end provided on the lower end of the logic element layer 66A, and a second end provided on the lower end of the pad 64R- 2 . That is, the logic element layer 66A functions as the logic circuit LGA2 that outputs the signal input from the pad 64R- 2 toward the bump 63R- 2 . FIG. 26 is a cross-sectional view for explaining the build-up structure of the core chip group of the semiconductor memory device according to the first modification of the second embodiment. As shown in FIG. 26, in the signal paths SL7a and SL7b, in the core chips CC0 and CC2 and the core chips CC1 and CC3, the positions of the input and output terminals of the logic element layer are reversed. In order to match the input-output relationship of the logic element layers, the core chips CC1 and CC3 have different wiring patterns in the signal paths SL7a and SL7b from those of the core chips CC0 and CC2. Specifically, the input end and the output end of the logic element layer 65 in the core chips CC0 and CC2 are respectively connected to the bump 63L-2 and the pad 64L-2, and the logic element layer 66A in the core chips CC1 and CC3 is connected to the The input terminal and the output terminal are connected to the pad 64R-2 and the bump 63R-2, respectively. In addition, the input terminal and the output terminal of the logic element layer 66A in the core chips CC0 and CC2 are respectively connected to the bump 63R-2 and the pad 64R-2, and the input terminal of the logic element layer 65 in the core chips CC1 and CC3 is connected and the output terminals are respectively connected to the pad 64L-2 and the bump 63L-2. By configuring in this way, even when the same logic circuits are provided in the left-right symmetrical positions in the core chip CC, the input-output relationship of each signal path can be matched. Next, the method of forming the element layer on the wafer in the method of manufacturing the semiconductor memory device according to the first modification of the second embodiment will be described. 27 is a schematic view for explaining a method of forming an element layer on a wafer in the semiconductor memory device according to the first modification of the second embodiment. In the following description, the layout patterns of the core chips CC0 to CC3 described in FIGS. 24 and 25 are referred to as layout patterns P5. As shown in FIG. 27, the mask set MS3a is arranged in the same layout pattern P5. Furthermore, in the example of FIG. 27, the mask set MS3a is alternately arranged in the x-direction, for example, the layout pattern P5 corresponding to the wiring pattern for the core chips CC0 and CC2 and the wiring pattern for the core chips CC1 and CC3 are arranged alternately The corresponding layout pattern P5. Moreover, the mask set MS3a is arrange|positioned so that both ends along the x direction may become different wiring patterns, respectively. Wafers W1 and W2 are folded in half with respect to the yz plane from the state of being aligned in the x direction on the xy plane, for example, similarly to FIG. 12 in the first embodiment. By bonding the wafers W1 and W2 onto which the mask set MS3 is transferred as described above, a plurality of structures capable of functioning as the wafer set CS described in FIG. 26 can be obtained. Furthermore, the manufacturing method of the first modification of the second embodiment is not limited to the example of using one mask set including mutually different wiring patterns, and two mask sets including different wiring patterns may be used. FIG. 28 is a schematic diagram for explaining a method of forming an element layer on a wafer in the semiconductor memory device according to the first modification of the second embodiment. As shown in FIG. 28, different mask sets MS3b and MS3c can also be applied to wafers W1 and W2, respectively. Specifically, as shown in FIG. 28(A), the mask set MS3b is similarly arranged in a layout pattern P5 corresponding to the wiring patterns for the core chips CC0 and CC2. Also, as shown in FIG. 28(B), the mask set MS3c is similarly arranged in a layout pattern P5 corresponding to the wiring patterns for the core chips CC1 and CC3. By laminating the wafer W1 on which the mask set MS3b has been transferred and the wafer W2 on which the mask set MS3c has been transferred as described above, a plurality of wafer sets CS that can function as described in FIG. 26 can be obtained. The composition of functions. 3. Third Embodiment Next, a semiconductor memory device according to a third embodiment will be described. In the semiconductor memory device of the second embodiment, the case where the bumps are provided in the left-right symmetrical positions in the core chip CC has been described. The semiconductor memory device of the third embodiment is different from the second embodiment in that the bumps in the core chip CC are arranged in left-right asymmetrical positions. Furthermore, the semiconductor memory device of the second embodiment is designed to have the same layout pattern between the wafer sets, but the semiconductor memory device of the third embodiment uses different layout patterns between the two chip sets. More specifically, two layout patterns different from each other are designed to be mirror-symmetrical. Hereinafter, the same reference numerals are given to the same components as those of the second embodiment, and the description thereof will be omitted, and the parts different from those of the second embodiment will be described. 3. 1 About the structure The structure of the semiconductor memory device according to the third embodiment will be described. 3. 1. 1 About the structure of the core chip The structure of the core chip of the semiconductor memory device of the third embodiment will be described. 29 to 32 are cross-sectional views for explaining the layout pattern and the wiring pattern of the core chip of the semiconductor memory device of the third embodiment. The configurations of the core chips CC0 to CC3 are shown in FIGS. 29 to 32 , respectively. As described above, in the third embodiment, the layout patterns of the core chips CC0 and CC1 and the layout patterns of the core chips CC2 and CC3 are different from each other. First, the core chip CC0 will be explained. The layout pattern shown in FIG. 29 corresponds to the symbol P6 which is different from the symbol P4 shown in FIG. 19 and the symbol P5 shown in FIG. 24 . As shown in FIG. 29, the core chip CC0 has the same structure as that of FIG. 19 except for a part. Specifically, the core chip CC0 includes through holes 62R-3B, bumps 63R-3B, wiring layers 76B, and pads 64R-3B in place of the through holes 62R-3, bumps 63R-3, and wiring layers in FIG. 19 . 76, and pad 64R-3. The connection relationship between the bumps 63R-3B, the through holes 62R-3B, the wiring layer 76B, and the pads 64R-3B is the connection between the bumps 63R-3, the through holes 62R-3, the wiring layer 76, and the pads 64R-3 The relationship is the same. However, the bumps 63L- 3 and 63R- 3B are disposed at asymmetrical positions with respect to the center of the semiconductor substrate 60 . Specifically, the bumps 63R- 3B are disposed at a distance d11B from the center of the semiconductor substrate 60 while the bumps 63L-3 are disposed at a distance d11 from the center of the semiconductor substrate 60 . Furthermore, the bonding pads 64L-3 and 64R-3 are disposed at symmetrical positions with respect to the center of the semiconductor substrate 60 . Specifically, the bonding pads 64L- 3 and 64R- 3 are provided at positions at a distance d15 from the center of the semiconductor substrate 60 . Next, the core chip CC1 will be described. As shown in FIG. 30, the layout pattern of the core chip CC1 is consistent with the layout pattern of the core chip CC0. Therefore, in the example of FIG. 30, the pads 64L-3 and 64R-3 are symmetrical with respect to the center of the semiconductor substrate 60, and are disposed at the same positions as the pads 64L-3 and 64R-3 in FIG. 29 . In addition, the bumps 63L-3 and 63R-3 are asymmetrical with respect to the center of the semiconductor substrate 60, and are disposed at the same positions as the bumps 63L-3 and 63R-3 in FIG. 29 . Next, the core chip CC2 will be explained. The layout pattern shown in FIG. 31 corresponds to the symbol P7 which is different from the symbol P6 shown in FIGS. 29 and 30 . As shown in FIG. 31 , the layout pattern of the core chip CC2, for example, has a mirror-symmetrical relationship with respect to the yz plane with respect to the layout patterns of the core chips CC0 and CC1. Specifically, the element layer 91 is provided on the semiconductor substrate 90. A plurality of through holes 92L (92L-1, 92L-2, 92L-3, and 92L-4) and 92R (92R-1, 92R-2, 92R-3, 92R-1, 92R-2, 92R-3, and 92R-4). The exposed portions of the through holes 92L-1 to 92L-4 on the lower surface of the semiconductor substrate 90 are provided with bumps 93L-1, 93L-2, 93L-3 that function as the terminals T5a, T7a, T8a, and T4a, respectively , and 93L-4. The exposed portions of the through holes 92R-1 to 92R-4 on the lower surface of the semiconductor substrate 90 are provided with bumps 93R-1, 93R-2, 93R-3 that function as the terminals T6a, T8a, T7a, and T4a, respectively , and 93R-4. A plurality of pads 94L (94L-1, 94L-2, 94L-3, and 94L-4) that function as terminals T5b, T7b, T8b, and T4b are provided on the upper surface of the element layer 91 . Further, on the upper surface of the element layer 91, a plurality of pads 94R (94R-1, 94R-2, 94R-3, and 94R-4) functioning as the terminals T6b, T8b, T7b, and T4b are provided. The upper surface of the bonding pad 94 is exposed on the upper surface of the element layer 91 . Logic element layers 95 to 97 and wiring layers 98 to 110 that function as logic circuits LGA1 , LGB1 , and LGA1 are provided in the element layer 91 , respectively. The wiring layer 98 includes a first end disposed on the upper end of the through hole 92L-1, and a second end disposed on the lower end of the bonding pad 94L-1. For example, the wiring layer 98 is not connected to the internal circuit, and the element layer 91 is skipped. The wiring layer 99 includes a first end disposed on the upper end of the through hole 92R-1, and a second end disposed on the lower end of the bonding pad 94R-1. The wiring layer 99 is connected to, for example, an internal circuit. The wiring layer 100 includes a first end disposed on the upper end of the through hole 92L- 2 , and a second end disposed on the upper end of the logic element layer 95 . The wiring layer 100 is connected to, for example, an internal circuit. The wiring layer 101 includes a first end provided on the lower end of the logic element layer 95 and a second end provided on the lower end of the bonding pad 94L-2. The logic element layer 95 includes a lower end having a function as an output end, and an upper end having a function as an input end. That is, the logic element layer 95 functions as the logic circuit LGA1 that outputs the signal input from the bump 93L-2 toward the pad 94L-2. The wiring layer 102 includes a first end disposed on the upper end of the through hole 92R- 2 , and a second end disposed on the upper end of the logic element layer 96 . The wiring layer 103 includes a first end provided on the lower end of the logic element layer 96 and a second end provided on the lower end of the bonding pad 94R- 2 . For example, the wiring layers 102 and 103 are not connected to the internal circuit, and the element layer 91 is skipped. The logic element layer 96 includes a lower end having a function as an input end, and an upper end having a function as an output end. That is, the logic element layer 96 functions as the logic circuit LGB1 that outputs the signal input from the pad 94R- 2 to the bump 93R- 2 . The wiring layer 104 includes a first end disposed on the upper end of the through hole 92L-3, and a second end disposed on the lower end of the bonding pad 94L-3. The wiring layer 104 is connected to, for example, an internal circuit. The wiring layer 105 includes a first end disposed on the upper end of the through hole 92R- 3 , and a second end disposed on the upper end of the logic element layer 97 . The wiring layer 106 includes a first end provided on the lower end of the logic element layer 97 and a second end provided on the lower end of the bonding pad 94R-3. The wiring layers 105 and 106 are not connected to the internal circuit, for example, and the element layer 91 is skipped. The logic element layer 97 includes an upper end having a function as an input end, and a lower end having a function as an output end. That is, the logic element layer 97 functions as the logic circuit LGA1 that outputs the signal input from the bump 93R-3 toward the pad 94R-3. The wiring layer 107 includes a first end disposed on the upper end of the through hole 92L-4, for example, connected to an internal circuit. The wiring layer 108 includes a first end disposed on the lower end of the pad 94L-4, for example, connected to an internal circuit. The wiring layer 109 includes a first end disposed on the upper end of the through hole 92R-4, for example, connected to an internal circuit. The wiring layer 110 includes a first end disposed on the lower end of the pad 94R- 4 , for example, connected to an internal circuit. In the example of FIG. 31 , the bonding pads 94L and 94R are disposed at positions symmetrical with respect to the center of the semiconductor substrate 90 . Specifically, the bonding pads 94L- 1 and 94R- 1 are provided at positions at a distance d13 from the center of the semiconductor substrate 90 . The bonding pads 94L- 2 and 94R- 2 are disposed at a distance d14 from the center of the semiconductor substrate 90 . The bonding pads 94L- 3 and 94R- 3 are disposed at a distance d15 from the center of the semiconductor substrate 90 . The bonding pads 94L- 4 and 94R- 4 are disposed at a distance d16 from the center of the semiconductor substrate 90 . In addition, the bumps 93L and 93R are disposed at asymmetrical positions with respect to the center of the semiconductor substrate 90 except for the bumps 93L-3 and 93R-3. Specifically, the bumps 93L- 1 and 93R- 1 are provided at positions at a distance d9 from the center of the semiconductor substrate 90 . The bumps 93L- 2 and 93R- 2 are provided at positions at a distance d10 from the center of the semiconductor substrate 90 . The bumps 93L- 4 and 93R- 4 are provided at positions at a distance d12 from the center of the semiconductor substrate 90 . Furthermore, the bumps 93L-3 and 94R-3 are disposed at asymmetrical positions with respect to the center of the semiconductor substrate 90 . Specifically, the bump 93L- 3 is provided at a distance d11B from the center of the semiconductor substrate 90 , while the bump 93R- 3 is provided at a distance d11 from the center of the semiconductor substrate 90 . Next, the core chip CC3 will be explained. As shown in FIG. 32, the layout pattern of the core chip CC3 is consistent with the layout pattern of the core chip CC2. Therefore, in the example of FIG. 32, the pads 94L-3 and 94R-3 are symmetrical with respect to the center of the semiconductor substrate 90, and are disposed at the same positions as the pads 94L-3 and 94R-3 in FIG. 31 . Also, the bumps 93L-3 and 93R-3 are asymmetrical with respect to the center of the semiconductor substrate 90, and are disposed at the same positions as the bumps 93L-3 and 93R-3 in FIG. 31 . 3. 1. 2 About the laminated structure of the core chip group Next, the laminated structure of the core chip group of the semiconductor memory device according to the third embodiment will be described with reference to FIG. 33 . 33 is a cross-sectional view for explaining the laminated structure of the core chip group of the semiconductor memory device of the third embodiment. As shown in FIG. 33, in the third embodiment, the wafer set CSa including the core chips CC0 and CC1 and the wafer set CSb including the core chips CC2 and CC3 are different from each other. Specifically, the core chips CC2 and CC3 have layout patterns that are mirror-symmetrical to the core chips CC0 and CC1. Therefore, in the signal paths SL7 and SL8, in the core chips CC0 and CC1 and the core chips CC2 and CC3, the positions of the input and output terminals of the logic element layer are reversed. In order to match the input-output relationship of the logic element layer, the core chips CC2 and CC3 have different wiring patterns in the signal paths SL7 and SL8 from those of the core chips CC0 and CC1. Specifically, for example, in the signal path SL7, the wiring layers 70 and 71 are respectively connected to the lower end and the upper end of the logic element layer 65 in the core chip CC0, and the lower end and the upper end of the logic element layer 95 in the core chip CC2 are connected to the wiring layers 70 and 71 respectively. Wiring layers 101 and 100 are connected to the upper ends, respectively. In addition, in the core chip CC1, the wiring layers 73 and 72 are connected to the upper end and the lower end of the logic element layer 66, respectively, and the wiring layers 102 and 103 are respectively connected to the upper end and the lower end of the logic element layer 96 in the core chip CC3. By configuring in this way, even when bumps are provided in the core chip CC at left-right asymmetrical positions, the input-output relationship of each signal path can be matched. 3. 2. About the manufacturing method Next, the manufacturing method of the semiconductor memory device of the third embodiment will be described. 3. 2. 1 About Wafer Formation The method of forming the element layer on the wafer in the method of manufacturing the semiconductor memory device of the third embodiment will be described. 34 is a schematic view for explaining a method of forming an element layer on a wafer in the semiconductor memory device of the third embodiment. In the following description, the layout patterns of the core chips CC0 and CC1 described in FIGS. 30 and 31 are referred to as layout patterns P6. In addition, the layout pattern of the core chips CC2 and CC3 demonstrated in FIG. 32 and FIG. 33 is called a layout pattern P7. As shown in FIG. 34, the mask set MS3d is arranged in the same layout pattern P6 in the x direction, for example. In addition, the mask set MS3d is arranged in the same manner as the layout pattern P7 in the x direction, for example, in a row different from the layout pattern P6. Wafers W1 and W2 are folded in half with respect to the yz plane from the state of being aligned in the x direction on the xy plane, for example, similarly to FIG. 12 in the first embodiment. By laminating the wafers W1 and W2 on which the mask set MS3d has been transferred as described above, a plurality of configurations capable of functioning as the wafer set CSa described in FIG. 34 and the wafer set CSb can be obtained at the same time. And the composition of the function. Furthermore, in the third embodiment, it is not limited to the above method, and two mask sets may be used. Specifically, for example, as the first mask set, only a mask set in which the layout pattern P6 is arranged in the same manner may be used. In addition, the chip set CSa may be provided by bonding two wafers whose device layers are formed by the first mask set. In addition, as the second mask set, only a mask set in which the layout pattern P7 is arranged in the same manner may be used. Then, the chip set CSb can also be provided by bonding the two wafers on which the element layer was formed by the second mask set. 3. 2. 2. About wafer screening The wafer screening step in the manufacturing method of the semiconductor memory device of the third embodiment can be applied, for example, to the same method as the first modification of the first embodiment. That is, the mask portion of the layout pattern P6 and the mask portion for the layout pattern P7 can be defined as the repeating unit DSU of the pin contact position of the wafer screening machine. This makes it possible to perform wafer screening using the repeating unit DSU of the needle contact position of one wafer screening machine for wafers in which the same wafer design is arranged. Furthermore, when the device layer is formed from two mask sets, the wafer screening of the wafer with the layout pattern P6 transferred and the wafer screening of the wafer transferred with the layout pattern P7 are carried out respectively. Also, in each wafer screening, a repeating unit DSU of different pin contact positions is defined. 3. 3 Effects of the present embodiment According to the third embodiment, the layout pattern P7 of the core chip CC2 and the layout pattern P6 of the core chip CC1 have a mirror-symmetrical relationship. Therefore, the bumps of the core chip CC2 are arranged at positions symmetrical to the bumps of the core chip CC1 with respect to the surface on which the core chips CC1 and CC2 are abutted. Thereby, the positions of the bumps of the core chip CC1 and the core chip CC2 are aligned with each other. In addition, the layout pattern P7 of the core chip CC3 and the layout patterns P6 of the core chips CC0 and CC1 have a mirror-symmetrical relationship. Therefore, the bumps of the core chip CC3 are arranged at positions symmetrical to the bumps of the core chip CC0 with respect to the surface on which the core chips CC1 and CC2 are abutted. Thereby, the positions of the bumps of the core chip CC3 and the core chip CC0 are aligned with each other. Therefore, the core wafer CC0 can be further laminated on the core wafer CC3. Furthermore, as mentioned above, since the layout patterns P6 and P7 have a mirror-symmetrical relationship with each other, if the chip sets CSa and CSb are attached to each other, the directions of the input and output terminals of the logic circuit are opposite to each other. In the third embodiment, wiring patterns different from each other are applied to the layout patterns P6 and P7. Specifically, in the wiring pattern of the core chip CC in one chip set CS, if the input end and the output end of the logic circuit are connected to the pads and bumps, respectively, the core chip in the other chip set CS In the wiring pattern of CC, the input terminal and the output terminal of the logic circuit are respectively connected to the bump and the pad. Therefore, when the core chips CC1 and CC2 are bonded together, the input-output relationship between the logic circuit disposed in the core chip CC1 and the logic circuit disposed in the core chip CC2 can be matched. In addition, when the core chips CC3 and CC0 are bonded together, the input-output relationship between the logic circuit provided in the core chip CC3 and the logic circuit provided in the core chip CC0 can be matched. 4. Fourth Embodiment Next, a semiconductor memory device according to the fourth embodiment will be described. In the first to third embodiments, the core wafer is provided on one semiconductor substrate. On the other hand, the core chip of the semiconductor memory device of the fourth embodiment is provided separately on at least two or more semiconductor substrates. Hereinafter, the same components as those of the first to third embodiments are given the same reference numerals, and the description thereof will be omitted, and the parts different from those of the first to third embodiments will be described. 4. 1 About the structure The structure of the semiconductor memory device according to the fourth embodiment will be described. 4. 1. 1 About the configuration of the core chip group An example of the configuration of the core chip group of the semiconductor memory device according to the fourth embodiment will be described with reference to FIG. 35 . FIG. 35 is a block diagram showing an example of the configuration of the core chip group of the semiconductor memory device of the fourth embodiment. As shown in FIG. 35 , each of the core chips CC (CC0, CC1, . . . ) of the core chip group 11 includes a plurality of sub-chips SC. Specifically, for example, core wafer CC0 includes sub wafers SC0 and SC1, and core wafer CC1 includes sub wafers SC2 and SC3. Furthermore, any natural number can be applied to the number of core chips CC. Here, the "sub-chip SC" refers to a semiconductor integrated circuit provided on one semiconductor substrate, and refers to a semiconductor integrated circuit that constitutes a part of the function of the core chip CC. 4. 1. 2. Connection between core chips Next, the connection between the core chips of the semiconductor memory device of the fourth embodiment will be described with reference to FIG. 36 . 36 is a circuit diagram for explaining an example of connection between core chips of the semiconductor memory device of the fourth embodiment. In FIG. 36, two core chips CC0 and CC1 are shown. Fig. 36 corresponds to Fig. 18 shown in the second embodiment. As shown in FIG. 36, the connections between the sub-chips SC0, SC1, SC2, and SC3 are the same as the connections between the core chips CC0, CC1, CC2, and CC3 in FIG. 18, respectively. That is, the core chips CC0 and CC1 are connected by the connection between the sub-chips SC1 and SC2. By configuring as above, from the terminal T1a of the subchip SC0 to the terminal T1b of the subchip SC3, from the terminal T5a of the subchip SC0 to the terminal T5b of the subchip SC3, and from the terminal T6a of the subchip SC0 to the subchip The terminal T6b of SC3 functions as signal paths SL1, SL5, and SL6 that can transmit and receive signals to each of the core chips CC0 to CC1, respectively. Further, from the terminal T7a of the sub-chip SC0 to the terminal T7b of the sub-chip SC3 are sent to the sub-chip as signals that can be processed by the logic circuit LGA1 or LGA2 of the sub-chip SCn (n is 0≦n≦2). The signal path SL7 of SC(n+1) functions. Further, from the terminal T8a of the sub-chip SC0 to the terminal T8b of the sub-chip SC3 is a signal path SL8 that can transmit the signal processed by the logic circuit LGB1 or LGB2 of the sub-chip SC(n+1) to the sub-chip SCn. function. Further, from the terminal T4b of the subchip SCn to the terminal T4a of the subchip SC(n+1) functions as a signal path SL4 capable of transmitting and receiving signals between the subchips SCn and SC(n+1). Furthermore, the terminals T1a and T4a to T8a of the sub-chip SC0 can send and receive various signals with the interface chip 10 or the controller 2 . 4. 1. 3. Configuration of sub-chip Next, the configuration of the sub-chip of the semiconductor memory device of the fourth embodiment will be described. 37 and 39 are plan views for explaining the layout pattern of the sub-chip of the semiconductor memory device of the fourth embodiment. 38 and 40 are cross-sectional views for explaining the layout pattern and the wiring pattern of the sub-chip of the semiconductor memory device of the fourth embodiment. 38 and 40 respectively show cross sections taken along the line XXXVIII-XXXVIII shown in FIG. 37 and the line XXXX-XXXX shown in FIG. 39 . 37 and FIG. 38 show the configuration common to the sub-chips SC0 and SC2, and FIG. 39 and FIG. 40 show the configuration common to the sub-chips SC1 and SC3. First, the configurations of the sub-chips SC0 and SC2 will be described. As shown in FIG. 37 , the layout patterns of the sub-chips SC0 and SC2 are part of the layout patterns of the core chips CC0 and CC1, respectively, and are arranged on the xy plane in a rectangle with two sides along the x-direction and two sides along the y-direction shape area. Specifically, subchips SC0 and SC2 include plane 0 and plane 1, data transfer circuit 13L, voltage generation circuit 16, driver sets 17UL and 17DL, column decoders 18-0 and 37-1, and sense amplifier 19-0 and 19-1. The layout patterns of the sub-chips SC0 and SC2 shown in FIG. 37 are, for example, relative to the left half of FIG. 4 and correspond to the symbol P8. Also, as shown in FIG. 38, an element layer 121 is provided on the upper surface of the semiconductor substrate 120 according to the layout pattern corresponding to the symbol P8 and the wiring pattern corresponding to the layout pattern. 38, for simplicity, descriptions of internal circuits other than terminals T4a, T5a, T7a, T8a, T4b, T5b, T7b, and T8b, and logic circuits LGA1 and LGB1 are omitted. On the semiconductor substrate 120 and the device layer 121, for example, a plurality of through holes 122 (122-1, 122-2, 122-3, and 122-4) and a plurality of bumps 123 (123-1, 123-2, 123) are provided. -3, and 123-4), a plurality of pads 124 (124-1, 124-2, 124-3, and 124-4), logic element layers 125 and 126, and wiring layers 127-133. The through holes 122, the bumps 123, the pads 124, the logic element layers 125 and 126, and the wiring layers 127 to 133 are respectively connected with, for example, the through holes 62L, bumps 63L, pads 64L, and logic element layers 65 shown in FIG. 19 . and 67, and the wiring layers 68, 70, 71, 74, 75, 77, and 78 are arranged in the same manner. In the example of FIG. 38 , the bumps 123-1 and the pads 124-1 are respectively disposed at positions d9 and d13 from the right end of the semiconductor substrate 120. The bump 123 - 2 and the bonding pad 124 - 2 are respectively disposed at distances d10 and d14 from the right end of the semiconductor substrate 120 . The bumps 123 - 3 and the bonding pads 124 - 3 are respectively disposed at distances d11 and d15 from the right end of the semiconductor substrate 120 . The bumps 123 - 4 and the bonding pads 124 - 4 are respectively disposed at distances d12 and d16 from the right end of the semiconductor substrate 120 . Next, the configurations of the sub-chips SC1 and SC3 will be described. As shown in FIG. 39, the layout patterns of the sub-chips SC1 and SC3 are part of the layout patterns of the sub-chips SC0 and SC1, respectively, and are arranged in the same rectangular area as the sub-chips SC0 and SC2 on the xy plane. Specifically, sub-chips SC1 and SC3 include planes 2 and 3, data transfer circuit 13R, logic control circuit 14, sequencer 15, driver sets 17UR and 17DR, column decoders 18-2 and 18-3, and a sensor Test amplifiers 19-2 and 19-3. The layout patterns of the sub-chips SC0 and SC2 correspond to, for example, the right half of FIG. 4 and correspond to the symbol P9. Also, as shown in FIG. 40, an element layer 141 is provided on the upper surface of the semiconductor substrate 140 according to the layout pattern corresponding to the symbol P9 and the wiring pattern corresponding to the layout pattern. 40, for simplicity, descriptions of internal circuits other than the terminals T4a, T6a, T7a, T8a, T4b, T6b, T7b and T8b, and the logic circuit LGA2 are omitted. On the semiconductor substrate 140 and the device layer 141, for example, a plurality of through holes 142 (142-1, 142-2, 142-3, and 142-4) and a plurality of bumps 143 (143-1, 143-2, 143) are provided. -3, and 143-4), a plurality of pads 144 (144-1, 144-2, 144-3, and 144-4), a logic element layer 145, and wiring layers 146-151. The through hole 142, the bump 143, the pad 144, the logic element layer 145, and the wiring layers 146-151 are respectively connected with, for example, the through hole 62R, the bump 63R, the pad 64R, the logic element layer 66, and The wiring layers 69, 72, 73, 76, 79, and 80 are arranged in the same manner. In the example of FIG. 40 , the bumps 143-1 and the pads 144-1 are respectively disposed at positions d9 and d13 from the right end of the semiconductor substrate 140. The bumps 143 - 2 and the bonding pads 144 - 2 are respectively disposed at distances d10 and d14 from the right end of the semiconductor substrate 140 . The bumps 143 - 3 and the bonding pads 144 - 3 are respectively disposed at distances d11 and d15 from the right end of the semiconductor substrate 140 . The bumps 143 - 4 and the pads 144 - 4 are respectively disposed at distances d12 and d16 from the right end of the semiconductor substrate 140 . By configuring as above, the layout patterns of the sub-chips SC1 and SC3 are different from the layout patterns of the sub-chips SC0 and SC2. Specifically, the terminals of the sub-chips SC1 and SC3 are arranged in mirror-symmetrical positions with the terminals of the sub-chips SC0 and SC2, but the configurations of the internal circuits including the directions of the input and output of the logic circuits are different from each other. 4. 1. 4. About the laminated structure of the core chip group Next, the laminated structure of the core chip group of the semiconductor memory device according to the fourth embodiment will be described with reference to FIG. 41 . FIG. 41 is a cross-sectional view for explaining the laminated structure of the core chip group of the semiconductor memory device of the fourth embodiment. FIG. 41 shows a structure in which the sub-wafers SC0 to SC3 shown in FIGS. 38 and 40 are laminated in this order. As shown in FIG. 41 , the upper surface of the sub-chip SC0 and the upper surface of SC2 are bonded to the upper surface of the sub-chip SC1 and the upper surface of the sub-chip SC3, respectively. As described above, the positions of the bonding pads 124 of the sub-chips SC0 and SC2 and the positions of the bonding pads 144 of the sub-chips SC1 and SC3 are designed to be mirror-symmetrical with respect to the facing surfaces of each other's upper surfaces. Therefore, the positions of the bonding pads 124-1 to 124-4 of the subchip SC0 are aligned with the positions of the bonding pads 144-1 to 144-4 of the subchip SC1, respectively. In addition, the lower surface of the sub-chip SC1 is bonded to the lower surface of the sub-chip SC2. As described above, the positions of the bumps 143 of the sub-wafer SC1 and the positions of the bumps 123 of the sub-wafer SC2 are designed to be mirror-symmetrical with respect to the opposing surfaces of the upper surfaces of each other. Therefore, the positions of the bumps 143-1 to 143-4 of the subchip SC1 are aligned with the positions of the bumps 123-1 to 123-4 of the subchip SC2, respectively. With the above configuration, the sub-chips SC0 to SC3 can form signal paths SL4, SL5, SL7, and SL8 that can communicate with each internal circuit. As described above, the sub-chips SC0 and SC2 and the sub-chips SC1 and SC3 are provided with logic circuits by different layout patterns. Therefore, for example, in the signal path SL7, the logic element layer 145 having the input/output direction from the element layer 141 toward the semiconductor substrate 140 can be made to correspond to the logic element layer 125 having the input/output direction from the semiconductor substrate 120 toward the element layer 121 . Therefore, the logic device layer 125 including the lower end connected to the through hole 122-2 and the upper end connected to the pad 124-2, and the logic device layer 125 including the lower end connected to the through hole 142-2 and the upper end connected to the bonding pad 144-2 The input-output relationship of the logic element layer 145 is matched. 4. 2. About the manufacturing method Next, the manufacturing method of the semiconductor memory device of the fourth embodiment will be described. 4. 2. 1 About Wafer Formation The method of forming the element layer on the wafer in the manufacturing method of the semiconductor memory device of the fourth embodiment will be described. FIG. 42 is a schematic view for explaining a method of forming an element layer on a wafer in the semiconductor memory device of the fourth embodiment. That is, FIG. 42 corresponds to step ST10 in FIG. 10 . In FIG. 42, the layout pattern transferred onto wafers W1 and W2 using mask set MS4 is schematically shown. Specifically, in FIG. 42 , the layout pattern explained in FIGS. 37 and 38 is represented by the symbol P8, and the layout pattern explained in FIGS. 39 and 40 is represented by the symbol P9. In the following description, the layout pattern illustrated in FIGS. 37 and 38 is referred to as a layout pattern P8, and the layout pattern illustrated in FIGS. 39 and 40 is referred to as a layout pattern P9. As shown in FIG. 42 , the mask set MS4 is alternately arranged in layout patterns P8 and P9 along the x-direction. Moreover, the mask set MS4 is arrange|positioned so that both ends along the x direction may become different layout patterns, respectively. Wafers W1 and W2 are folded in half with respect to the yz plane from the state of being aligned in the x direction on the xy plane, for example, similarly to FIG. 12 in the first embodiment. By laminating the wafers W1 and W2 on which the mask set MS4 is transferred as described above, a plurality of structures capable of functioning as the chip set CS in FIG. 41 can be obtained. 4. 2. 2. About wafer screening The wafer screening step in the manufacturing method of the semiconductor memory device of the fourth embodiment can be applied, for example, by the same method as that of the first embodiment. That is, the mask portion of the layout pattern P8 and the mask portion for the layout pattern P9 can be defined as the repeating unit DSU of the pin contact position of the wafer screening machine. Thereby, it is possible to perform wafer screening using the repeating unit DSU of the needle contact position of one wafer screening machine for wafers in which the same wafer design is arranged. 4. 3 Effects of the present embodiment According to the fourth embodiment, the core wafer CC0 includes sub wafers SC0 and SC1 whose upper surfaces are bonded to each other. That is, one core wafer CC is included in one wafer set CS. Therefore, compared with the first to third embodiments in which two core wafers CC are included in one wafer set CS, the yield rate per wafer set CS obtained by dicing is controlled to be halved in size the yield. Therefore, the manufacturing efficiency of good products can be improved. In addition, wafers W1 and W2 form device layers by the same mask set MS4. The mask set MS4 includes two layout patterns P8 and P9 that are different from each other. The layout patterns P8 and P9 are arranged alternately. Therefore, when the wafers W1 and W2 are bonded together, the element layer to which the layout pattern P8 is transferred and the element layer to which the layout pattern P9 is transferred can be bonded to each other. Furthermore, the cost required for the design of the mask set MS4 is equivalent to the cost of designing the layout patterns P8 and P9. However, the layout patterns P8 and P9 in total correspond to one core wafer CC. Therefore, the design cost of the mask set MS4 can be controlled to be equal to the design cost of one core chip CC. In addition, as described above, since one core chip CC is constituted by one chip set CS, the length of wiring required for communication within the core chip CC can be shortened. 43 and 44 are schematic diagrams for explaining the effect of the semiconductor memory device of the fourth embodiment. FIG. 43(A) and FIG. 44(A) show an example of circuit arrangement of one core chip CC0 formed on one semiconductor substrate. FIGS. 43(B) and 44(B) correspond to the fourth embodiment, and show the structure of one core wafer CC0 constituted by two sub-chips SC0 and SC1 respectively provided on two bonded semiconductor substrates. Example of circuit configuration. FIG. 43 shows a case where one core chip CC0 includes 4 planes, and FIG. 44 shows a case where one core chip CC0 includes 8 planes. As shown in FIG. 43(A), when the core chip CC0 is disposed on one semiconductor substrate, when it is necessary to communicate between the point Q1 and the point Q2 of the peripheral circuit, it is necessary to start from the left end to the right end of the core chip CC0 Wiring up to the length. The length from the left end to the right end of the core chip CC0 is, for example, in the order of millimeters (mm). On the other hand, as shown in FIG. 43(B) , when the core wafer CC0 is provided separately on the two semiconductor substrates to be bonded, the point Q2 is disposed right above the point Q1 in the build-up direction. Therefore, the length of the wiring from the point Q1 to the point Q2 becomes at most the length of the signal path between the subchips SC0 and SC1. The length of the signal path between the sub-chips SC0 and SC1 is, for example, in the order of micrometers (μm). That is, the structure of FIG. 43(B) can shorten the length of the wiring from the point Q1 to the point Q2 compared with the structure of FIG. 43(A). Therefore, according to the fourth embodiment, the wiring pattern in the peripheral circuit can be simplified, and the manufacturing cost can be reduced. Furthermore, as shown in FIG. 44(A), in the case where the core chip CC0 of 8 planes is formed on one semiconductor substrate, when the communication between the point Q3 and the point Q4 in the peripheral circuit is performed, the 4 planes are formed In this case, the wiring length is twice as long. Therefore, as the wiring length increases, the electrical characteristics deteriorate, and there is a possibility that the design that satisfies the constraints associated with communication delays and the like becomes difficult. On the other hand, as shown in FIG. 44(B), when the 8-plane structure is provided separately on two semiconductor substrates to be bonded, the length of the wiring from the point Q3 to the point Q4 becomes the second at most The length of the signal path between chips SC0 and SC1. Furthermore, the maximum length of the wiring in the internal circuit can be controlled to be equivalent to the case of the four-plane configuration shown in FIG. 43(A). Therefore, it becomes easy to solve the problem of the length of the wiring which becomes obvious in the case of FIG. 44(A), and it becomes easy to carry out the design of an 8-plane structure. In addition, since the area of the semiconductor substrate can also be controlled to the same scale as in the case of FIG. 44(A), the limitation of the area in the package can also be improved. 4. 4. First modification of the fourth embodiment In addition, the semiconductor memory device of the fourth embodiment is not limited to the above-mentioned example, and various modifications can be applied. For example, the positions of the bumps between the sub-chips SC in the same core chip CC may not be arranged in mutually mirror-symmetrical positions. 45 to 48 are cross-sectional views for explaining the layout pattern and the wiring pattern of the sub-chip of the semiconductor memory device according to the first modification of the fourth embodiment. The configurations of the sub wafers SC1 to SC3 are shown in FIGS. 45 to 48 , respectively. In addition, the configuration of the sub wafer SC0 is the same as that shown in FIG. 38 in the fourth embodiment. First, the sub-chip SC1 will be described. The layout pattern of the sub-chip SC1 of the first modification of the fourth embodiment is different from the layout pattern of the sub-chip SC1 of the fourth embodiment. Therefore, the layout pattern shown in FIG. 45 corresponds to the symbol P10 which is different from the symbol P9 shown in FIG. 40 . As shown in FIG. 45, the sub-chip SC1 has the same structure as that of FIG. 40 except for a part. Specifically, the sub-chip SC1 includes vias 142-3B, bumps 143-3B, wiring layers 149B, and pads 144-3B in place of the vias 142-3, bumps 143-3, and wiring layers in FIG. 40 . 149, and the pad 144-3. The connection relationship between the bump 143-3B, the through hole 142-3B, the wiring layer 149B, and the pad 144-3B is the connection between the bump 143-3, the through hole 142-3, the wiring layer 149, and the pad 144-3 The connection relationship is the same. However, the bump 143-3B is provided at a different position from the bump 143-3. That is, the bump 143-3B is provided at a position that is not mirror-symmetrical with the bump 123-3 shown in FIG. 38 . Specifically, while the bump 143 - 3 is disposed at a distance d11 from the left end of the semiconductor substrate 140 , the bump 143 - 3B is disposed at a distance d11B from the left end of the semiconductor substrate 140 . Furthermore, the bonding pad 144-3B is disposed at the same position as the bonding pad 144-3. That is, the bonding pad 144-3B is disposed in a mirror-symmetrical position with the bonding pad 124-3 shown in FIG. 38 . Specifically, the bonding pad 144 - 3B is disposed at a distance d15 from the left end of the semiconductor substrate 140 . Next, the sub-chip SC2 will be described. As shown in FIG. 46 , the layout pattern of the sub-chip SC2, for example, has a mirror-symmetric relationship with respect to the yz plane with respect to the layout pattern of the sub-chip SC1. The layout pattern shown in FIG. 46 corresponds to the symbol P11 which is different from the symbol P10 shown in FIG. 45 . Specifically, the element layer 161 is provided on the semiconductor substrate 160. A plurality of through holes 162 ( 162 - 1 , 162 - 2 , 162 - 3 , and 162 - 4 ) that function as TSVs are provided in the semiconductor substrate 160 . The exposed portions of the through holes 162-1 to 162-4 on the lower surface of the semiconductor substrate 160 are provided with bumps 163-1, 163-2, 163-3 that function as the terminals T5a, T7a, T8a, and T4a, respectively , and 163-4. On the upper surface of the element layer 161, a plurality of pads 164 (164-1, 164-2, 164-3, and 164-4) functioning as the terminals T5b, T7b, T8b, and T4b are provided. The upper surface of the pad 164 is exposed on the upper surface of the element layer 161 . In the element layer 161, a logic element layer 165 functioning as the logic circuit LGA1, and wiring layers 166 to 171 are provided. The wiring layer 166 includes a first end disposed on the upper end of the through hole 162-1, and a second end disposed on the lower end of the bonding pad 164-1. For example, the wiring layer 166 is not connected to the internal circuit, and the element layer 161 is skipped. The wiring layer 167 includes a first end disposed on the upper end of the through hole 162-2, and a second end disposed on the upper end of the logic element layer 165. The wiring layer 168 includes a first end disposed on the lower end of the logic element layer 165, and a second end disposed on the lower end of the bonding pad 164-2. For example, the wiring layers 167 and 168 are not connected to the internal circuit, and the element layer 161 is skipped. The logic element layer 165 includes a lower end having a function as an output end, and an upper end having a function as an input end. That is, the logic element layer 165 functions as the logic circuit LGA1 that outputs the signal input from the bump 163-2 toward the pad 164-2. The wiring layer 170 includes a first end disposed on the upper end of the through hole 162-4, for example, connected to an internal circuit. The wiring layer 171 includes a first end disposed on the lower end of the bonding pad 164-4, for example, connected to an internal circuit. In the example of FIG. 46, the bonding pad 164-3 is disposed in a mirror-symmetrical position with the bonding pad 144-3B of FIG. 45. Specifically, relative to the bonding pad 144 - 3B which is positioned at a distance d15 from the left end of the semiconductor substrate 140 , the bonding pad 164 - 3 is positioned at a distance d15 from the right end of the semiconductor substrate 160 . The other pads 164-1, 164-2, and 164-4 are similarly disposed in mirror-symmetrical positions with the pads 144-1, 144-2, and 144-4 in FIG. 45 . In addition, the bump 163-3 is disposed in a mirror-symmetrical position with the bump 143-3B of FIG. 45 . Specifically, relative to the bump 143 - 3B disposed at a distance d11B from the left end of the semiconductor substrate 140 , the bump 163 - 3 is disposed at a distance d11B from the right end of the semiconductor substrate 160 . The other bumps 163-1, 163-2, and 163-4 are similarly disposed in mirror-symmetrical positions with the bumps 143-1, 143-2, and 143-4 in FIG. 45 . Next, the sub-chip SC3 will be described. As shown in FIG. 47 , the layout pattern of the sub-chip SC2, for example, has a mirror-symmetrical relationship with respect to the yz plane relative to the layout pattern of the sub-chip SC0. The layout pattern of the sub-chip SC3 corresponds to the symbol P12 which is different from the symbol P8 shown in FIG. 38 . Specifically, the element layer 181 is provided on the semiconductor substrate 180. A plurality of through holes 182 ( 182 - 1 , 182 - 2 , 182 - 3 , and 182 - 4 ) that function as TSVs are provided in the semiconductor substrate 180 . The exposed portions of the through holes 182-1 to 182-4 on the lower surface of the semiconductor substrate 180 are provided with bumps 183-1, 183-2, and 183-3 that function as the terminals T5b, T7b, T8b, and T4b, respectively. , and 183-4. On the upper surface of the element layer 181, a plurality of pads 184 (184-1, 184-2, 184-3, and 184-4) functioning as terminals T5a, T7a, T8a, and T4a are provided. The upper surface of the bonding pad 184 is exposed on the upper surface of the element layer 181 . Logic element layers 185 and 186 and wiring layers 187 to 193 that function as logic circuits LGA2 and LGB2 are provided in the element layer 181, respectively. The wiring layer 187 includes a first end disposed on the upper end of the through hole 182-1, and a second end disposed on the lower end of the bonding pad 184-1. The wiring layer 187 is connected to, for example, an internal circuit. The wiring layer 188 includes a first end disposed on the upper end of the through hole 182-2, and a second end disposed on the upper end of the logic element layer 185. The wiring layer 188 is connected to, for example, an internal circuit. The wiring layer 189 includes a first end disposed on the lower end of the logic element layer 185 and a second end disposed on the lower end of the bonding pad 184-2. The logic element layer 185 includes a lower end having a function as an input end, and an upper end having a function as an output end. That is, the logic element layer 185 functions as the logic circuit LGA2 that outputs the signal input from the pad 164-2 toward the bump 163-2. The wiring layer 190 includes a first end disposed on the upper end of the through hole 182-3, and a second end disposed on the upper end of the logic element layer 186. The wiring layer 191 includes a first end disposed on the lower end of the logic element layer 186, and a second end disposed on the lower end of the bonding pad 184-3. For example, the wiring layers 190 and 191 are not connected to the internal circuit, and the element layer 181 is skipped. The logic element layer 186 includes a lower end having a function as an output end, and an upper end having a function as an input end. That is, the logic element layer 186 functions as the logic circuit LGB2 that outputs the signal input from the bump 163-3 toward the pad 164-3. The wiring layer 192 includes a first end disposed on the upper end of the through hole 182-4, for example, connected to an internal circuit. The wiring layer 193 includes a first end disposed on the lower end of the pad 184-4, for example, connected to an internal circuit. In the example of FIG. 47, the pad 184-3 is disposed in a mirror-symmetrical position with the pad 124-3 of FIG. 38. Specifically, relative to the bonding pad 124 - 3 that is positioned at a distance d15 from the right end of the semiconductor substrate 120 , the bonding pad 184 - 3 is positioned at a distance d15 from the left end of the semiconductor substrate 180 . The other pads 184-1, 184-2, and 184-4 are similarly disposed in mirror-symmetrical positions with the pads 124-1, 124-2, and 124-4 in FIG. 38 . In addition, the bump 183-3 is arranged in a mirror-symmetrical position with the bump 123-3 in FIG. 38 . Specifically, while the bump 123 - 3 is disposed at a distance d11 from the right end of the semiconductor substrate 120 , the bump 183 - 3 is disposed at a distance d11 from the right end of the semiconductor substrate 180 . The other bumps 183-1, 183-2, and 183-4 are similarly disposed in mirror-symmetrical positions with the bumps 123-1, 123-2, and 123-4 in FIG. 38 . Fig. 48 is a cross-sectional view for explaining the build-up structure of the core chip group of the semiconductor memory device according to the first modification of the fourth embodiment. As shown in FIG. 48, in the first modification of the fourth embodiment, the wafer set CSa including the sub wafers SC0 and SC1 and the wafer set CSb including the sub wafers SC2 and SC3 are different from each other. Specifically, the sub-chips SC0 and SC1 have bumps in the signal path SL8 that are arranged at positions that are not mirror-symmetrical to each other. Therefore, in the signal path SL8, the positions of the bumps on the lower surface of the subchip SC1 and the lower surface of the subchip SC0 are not aligned. Subchip SC2 has a layout pattern that is mirror-symmetrical to subchip SC1. Therefore, the positions of the bumps on the lower surface of sub-wafer SC1 and the lower surface of sub-wafer SC2 are aligned. However, in the case where the same wiring pattern is applied to the sub-chips SC1 and SC2, the input-output relationship of the logic element layer does not match. Therefore, the input-output relationship of the logic element layer and the wiring pattern of the inversion of the sub-chip SC1 are applied to the sub-chip SC2. Thereby, the input-output relationship of the logic element layers between the sub-chips SC1 and SC2 is matched. Subchip SC3 has a layout pattern that is mirror-symmetrical to subchip SC0. Therefore, the positions of the pads on the upper surface of subchip SC2 and the upper surface of subchip SC3 are aligned. However, in the case where the same wiring pattern as that of the sub-chip SC0 is applied to the sub-chip SC3, the input-output relationship of the logic element layer does not match that of the sub-chip SC2. Therefore, in the sub-chip SC3, the input-output relationship of the logic element layer and the wiring pattern of the inversion of the sub-chip SC0 are applied. Thereby, the input-output relationship of the logic element layers between the sub-chips SC2 and SC3 is matched. Also, as described above, sub-wafer SC3 has a layout pattern that is mirror-symmetrical to sub-wafer SC0. Therefore, the lower surface of sub-wafer SC3 is aligned with the positions of the bumps on the lower surface of sub-wafer SC0. Thereby, the wafer set CSa can be further laminated on the wafer set CSb. Furthermore, in the first modification of the fourth embodiment, a layout pattern (P8 and P9) of one core chip and a mirror-symmetrical layout pattern (P10 and P11) of the layout pattern must be designed. In addition, the layout patterns P10 and P11 include wiring patterns different from the layout patterns P8 and P9. However, since the mirror-symmetrical layout pattern does not need to redesign the configuration of peripheral circuits and the like from scratch, the design cost is low. Therefore, the entire chip design can be designed by only adding the cost of the wiring pattern to the design cost of one chip design. Therefore, even when the positions of the bumps between the sub-chips SC within the same core chip CC are not set to be mirror-symmetrical, a plurality of core chips CC can be stacked with less manufacturing cost. 4. 5. Second modification of the fourth embodiment The semiconductor memory device of the fourth embodiment described above has been described as an example in which two sub-chips SC are included in one core chip CC, but the present invention is not limited to this. For example, the core wafer CC is not limited to two, and an even number (4, 6, . . . ) of sub wafers SC may be stacked and configured. Fig. 49 is a cross-sectional view for explaining the laminated structure of the core wafer group according to the second modification of the fourth embodiment. As shown in FIG. 49 , the core wafer CC0 may also include four sub wafers SC0 to SC3. With the above configuration, the area efficiency can be further improved as compared with the case where one core wafer CC is composed of two sub wafers SC. In addition, the wiring length of signals that must be communicated in the core chip CC can be further shortened. 4. 6. Third modification of the fourth embodiment In the semiconductor memory device of the fourth embodiment described above, the case where there is a circuit that exists only in the peripheral circuits of either of the subchips SC0 and SC1 has been described. Specifically, for example, the peripheral circuit of the sub-chip SC0 includes the voltage generating circuit 16 , but does not include the logic control circuit 14 and the sequencer 15 . On the other hand, the peripheral circuit of the sub-chip SC1 does not include the voltage generating circuit 16 , but includes the logic control circuit 14 and the sequencer 15 . However, it is not limited to this, and the sub-chips SC0 and SC1 may also be constituted by a partial circuit in which the same circuit is provided in any peripheral circuit. In this case, the layout patterns of the sub-chips SC0 and SC1 may also be designed in such a way that the partial circuits provided on the sub-chip SC0 and the partial circuits provided on the sub-chip SC1 overlap with the circuit regions in the stacking direction. 50 and 51 are plan views for explaining the layout pattern of the sub-chip of the semiconductor memory device according to the third modification of the fourth embodiment. The configurations of sub-chips SC0 and SC2 and sub-chips SC1 and SC3 are shown in FIGS. 50 and 51 , respectively. As shown in FIG. 51, in the layout pattern of the sub-chips SC0 and SC2, the peripheral circuits include a data transfer circuit 13L, a logic control circuit 14L, a sequencer 15L, a voltage generation circuit 16L, and driver sets 17UL and 17DL. Also, as shown in FIG. 52, in the layout pattern of the sub-chips SC1 and SC3, the peripheral circuits include a data transfer circuit 13R, a logic control circuit 14R, a sequencer 15R, a voltage generation circuit 16R, and driver sets 17UR and 17DR. For example, the data transmission circuit 13L, the logic control circuit 14L, the sequencer 15L, the voltage generation circuit 16L, and the driver sets 17UL and 17DL are respectively provided in the data transmission circuit 13R, the logic control circuit 14R, the sequencer 15R, and the voltage generation circuit. 16R, and the mirrored positions of the drive sets 17UR and 17DR. Furthermore, each circuit is not limited to being arranged in a mirror-symmetrical position, as long as there is a portion where a portion of the circuit having the same function when the upper surfaces of the sub-chips SC are attached to each other overlaps in the stacking direction. Can. With the above configuration, when the subchips SC are bonded to each other, circuits having the same function are arranged in the overlapping regions in the z direction. Thus, for example, when a signal is communicated between the voltage generation circuit 16L of the subchip SC0 and the voltage generation circuit 16R of the subchip SC1, the wiring connecting the voltage generation circuits 16L and 16R can be extended only in the lamination direction. Can. Therefore, it becomes unnecessary to provide extra wiring in the same primary wafer SC, and the design of the wiring pattern can be simplified. Furthermore, in the case where circuits having the same function are arranged at different positions along the z direction when the subchips SC are attached to each other, it is necessary to set different signal paths in the subchips SC0 and SC2 and the subchips SC1 and SC3. In this case, the signal paths for the sub-chips SC0 and SC2 are not available in the sub-chips SC1 and SC3, so the number of terminals or the wiring length increases. In the third modification of the fourth embodiment, as described above, when the subchips SC are bonded to each other, circuits having the same functions are arranged at the same positions along the z direction. Therefore, it is possible to reduce the need to separate the signal paths necessary for a certain circuit from the sub-chips SC0 and SC2 from the sub-chips SC1 and SC3. Therefore, a chip design with fewer restrictions can be designed, and the design cost can be reduced. 5. Fifth Embodiment Next, a semiconductor memory device according to a fifth embodiment will be described. In the semiconductor memory device of the fourth embodiment, one subchip SC is provided on one semiconductor substrate. On the other hand, in the fifth embodiment, two sub wafers SC are provided on one semiconductor substrate. Each of the 2 sub-chips SC becomes part of a core chip CC that is different from each other. That is, two core wafers CC (four sub wafers SC) are formed in one wafer set CS. Hereinafter, the same reference numerals are given to the same components as those of the fourth embodiment, and the description thereof will be omitted, and the parts different from those of the fourth embodiment will be described. 5. 1 About the structure The structure of the semiconductor memory device according to the fifth embodiment will be described. 5. 1. 1 About the configuration of the core chip group An example of the configuration of the core chip group of the semiconductor memory device according to the fifth embodiment will be described with reference to FIG. 52 . FIG. 52 is a block diagram showing an example of the configuration of the core chip group of the semiconductor memory device of the fifth embodiment. As shown in FIG. 52, the core chip group 11 includes, for example, a core chip CC twice as large as the core chip CC in the core chip group 11 in the fourth embodiment. Specifically, the core wafer group 11 includes a plurality of core wafers CC (CC0A, CC1A, . . . , and CC0B, CC1B, . . . ). Each core wafer CC includes two sub wafers SC. Specifically, the core chip CC0A includes sub-chips SC0A and SC1A, and the core chip CC1A includes sub-chips SC2A and SC3A. In addition, core chip CC0B includes sub-chips SC0B and SC1B, and core chip CC1B includes sub-chips SC2B and SC3B. Furthermore, an arbitrary natural number can be applied to the number of core chips CC. The sub-chips SC0A and SC0B are disposed on the semiconductor substrate SSO. The sub wafers SC1A and SC1B are provided on the semiconductor substrate SS1. The sub-chips SC2A and SC2B are provided on the same semiconductor substrate SS2. The sub-chips SC3A and SC3B are provided on the same semiconductor substrate SS3. 5. 1. 2. Configuration of sub-chip Next, the configuration of the sub-chip of the semiconductor memory device of the fifth embodiment will be described. 53 is a plan view for explaining the layout pattern of the sub-chip of the semiconductor memory device of the fifth embodiment. In FIG. 53, a group of two sub-chips SC provided on the same semiconductor substrate SS is shown. That is, FIG. 53 shows a configuration common to the group of sub-chips SC0A and SC0B, the group of sub-chips SC1B and SC1A, the group of sub-chips SC2A and SC2B, or the group of sub-chips SC3B and SC3A. The plan view shown in FIG. 53 corresponds to, for example, a combination of the right end of the plan view shown in FIG. 37 and the left end of the plan view shown in FIG. 39, and corresponds to the symbol P13. As shown in FIG. 53, the sub-wafers SC0A, SC1B, SC2A, and SC3B correspond to the layout pattern P8. The sub-chips SC0B, SC1A, SC2B, and SC3A are consistent with the layout pattern P9. Furthermore, the cross-sectional view showing the layout pattern and the wiring pattern of the fifth embodiment corresponds, for example, to the one obtained by combining the right end of the cross-sectional view shown in FIG. 38 and the left end of the cross-sectional view shown in FIG. 40 . 5. 1. 3. About the laminated structure of the core chip group Next, the laminated structure of the core chip group of the semiconductor memory device according to the fifth embodiment will be described with reference to FIG. 54 . FIG. 54 is a cross-sectional view for explaining the laminated structure of the core chip group of the semiconductor memory device according to the fifth embodiment. As shown in FIG. 54, the wafer set CS of the core wafer group in the fifth embodiment includes the wafer set CS shown in FIG. 41 of the fourth embodiment, and the wafer set CS shown in FIG. 41 is reversed upside down. By. Thereby, the core chip CC0A including the sub-chips SC0A and SC1A, and the core chip CC0B including the sub-chips SC0B and SC1B are arranged in one chip set CS. In addition, core chip CC1A including subchips SC2A and SC3A, and core chip CC1B including subchips SC2B and SC3B are provided in one chip set CS. In the example of FIG. 54 , the core chips CC0A and CC1A share independent signal path groups with the core chips CC0B and CC1B, respectively. 5. 2. About the manufacturing method Next, the manufacturing method of the semiconductor memory device of the fifth embodiment will be described. 5. 2. 1 About Wafer Formation The method of forming the element layer on the wafer in the manufacturing method of the semiconductor memory device of the fifth embodiment will be described. 55 is a schematic diagram for explaining a method of forming an element layer on a wafer in the semiconductor memory device of the fifth embodiment. That is, FIG. 55 corresponds to step ST10 in FIG. 10 . In FIG. 55, the layout pattern transferred onto wafers W1 and W2 using mask set MS6 is schematically shown. Specifically, in FIG. 55, the layout pattern described in FIG. 53 is represented by the symbol P13. As described above, the set of sub-chips SC0A and SC0B, the set of sub-chips SC1B and SC1A, the set of sub-chips SC2A and SC2B, and the set of sub-chips SC3B and SC3A comprise the same chip design. Therefore, as shown in FIG. 55, the mask set MS6 is arranged in the same wafer design. Wafers W1 and W2, for example, like FIG. 22 in the second embodiment, may be folded in half with respect to the yz plane by being aligned in the x direction on the xy plane, or they may be aligned in the y direction on the xy plane. The state is fit in the way of folding in half on the xz plane. By bonding the wafers W1 and W2 on which the mask set MS6 is transferred as described above, a plurality of structures capable of functioning as the wafer set CS described in FIG. 54 can be obtained. 5. 2. 2. About wafer screening The wafer screening step in the manufacturing method of the semiconductor memory device of the fifth embodiment can be applied, for example, by the same method as that of the second embodiment. That is, the mask portion of the layout pattern P13 can be defined as the repeating unit DSU of the pin contact position of the wafer screening machine. Thereby, it is possible to perform wafer screening using the repeating unit DSU of the needle contact position of one wafer screening machine for wafers in which the same wafer design is arranged. 5. 3. Effects of the present embodiment According to the fifth embodiment, the element layer provided on the semiconductor substrate SS0 includes the internal circuit of the sub-chip SC0A and the internal circuit of the sub-chip SC0B. The element layer provided on the semiconductor substrate SS1 includes the internal circuit of the subchip SC1A and the internal circuit of the subchip SC1B. The core chip CC0A includes sub-chips SC0A and SC1B, and the core chip CC0B includes sub-chips SC0B and SC1A. The sub-chips SC0A and SC1B correspond to the left half of the layout pattern of one core chip CC, and the sub-chips SC0B and SC1A correspond to the right half of the layout pattern of one core chip CC. Therefore, two core wafers CC can be provided in one wafer set CS. This makes it possible to double the number of core wafers CC provided in one wafer set CS compared to the fourth embodiment. Also, in the fifth embodiment, as in the second embodiment, the wafers W1 and W2 are formed with the same mask set MS6 to form element layers. The mask set MS6 is likewise aligned with the same chip design. Thereby, the mask set MS6 can be designed only by designing the layout pattern and wiring pattern of one core chip CC. Therefore, the manufacturing cost can be reduced. In addition, the layout pattern of the fifth embodiment is the same as that obtained by combining the right end of the layout pattern P8 of the fourth embodiment with the left end of the layout pattern P9. That is, in the layout pattern of the fifth embodiment, bumps and pads are provided at positions symmetrical with respect to the center of the semiconductor substrate. Therefore, when the wafers W1 and W2 are bonded together, the positions of the terminals of each other are matched. Thereby, the connection between the wafers W1 and W2 can be aligned. Furthermore, in the fifth embodiment, as in the fourth embodiment, the sub-chips SC0A and SC0B provided on the same semiconductor substrate SSO are provided with logic circuits by different layout patterns. Therefore, for example, in the signal path SL7, the logic element layer having the input/output direction from the element layer toward the semiconductor substrate can be made to correspond to the logic element layer having the input/output direction from the semiconductor substrate toward the element layer. Therefore, the logic element layer in sub-chip SC0A matches the input-output relationship of the logic element layer in sub-chip SC1B. In addition, the logic element layer in the sub-chip SC0B matches the input-output relationship with the logic element layer in the sub-chip SC1A. Also, as in the fourth embodiment, two sub-wafers SC provided on two semiconductor substrates are laminated to form one core wafer. Therefore, the length of wiring required for communication within the core chip CC can be shortened. 5. 4. First modification of the fifth embodiment In addition, the semiconductor memory device of the fifth embodiment is not limited to the above-mentioned example, and various modifications can be applied. In the fifth embodiment, as a case similar to the fourth embodiment, the case where the bumps in the two sub-wafers SC provided on the same semiconductor substrate SS are provided in a left-right symmetry has been described, but it is not limited to this. here. For example, similarly to the first modification of the fourth embodiment, the bumps in the two sub-chips SC provided on the same semiconductor substrate SS may be provided in a left-right asymmetric manner. Fig. 56 is a cross-sectional view for explaining the structure of the core chip group of the semiconductor memory device according to the first modification of the fifth embodiment. As shown in FIG. 56, in the first modification of the fifth embodiment, a wafer set CSa including sub wafers SC0A, SC0B, SC1A, and SC1B, and a wafer set CSb including sub wafers SC2A, SC2B, SC3A, and SC3B different from each other. Specifically, the layout patterns of the sub-chips SC2A and SC2B are in a mirror-symmetrical relationship with the layout pattern P13. Therefore, the bumps of the subchips SC2A and SC2B are arranged at positions symmetrical to the bumps of the subchips SC1A and SC1B with respect to the surfaces of the subchips SC1A and SC1B and the surfaces of the subchips SC2A and SC2B that are bonded. Thereby, the positions of the bumps of the subchips SC1A and SC1B and the subchips SC2A and SC2B are aligned with each other. In addition, the layout patterns of the sub-chips SC3A and SC3B are in a mirror-symmetrical relationship with the layout pattern P13. Therefore, the bumps of the subchips SC3A and SC3B are arranged at positions symmetrical to the bumps of the subchips SC0A and SC0B with respect to the surfaces of the subchips SC1A and SC1B and the surfaces of the subchips SC2A and SC2B that are bonded. Thereby, the sub-chips SC3A and SC3B, and the bumps of the sub-chips SC0A and SC0B are aligned. Therefore, the hierarchical wafers SC0A and SC0B can be further stacked on the sub wafers SC3A and SC3B. Furthermore, as mentioned above, since the chip sets CSa and CSb have a mutually mirror-symmetrical relationship, if the chip sets CSa and CSb are attached to each other, the orientations of the input and output terminals of the logic circuit become opposite to each other. In the fifth embodiment, wiring patterns different from each other can be applied to the layout patterns P4 and P6. Specifically, when the input terminal and the output terminal of the logic circuit in the wiring pattern of the subchip SC in one chip set CS are connected to the pads and the bumps, respectively, the subchip SC in the other chip set CS The input end and the output end of the logic circuit in the wiring pattern are respectively connected to the bump and the pad. Therefore, when the subchips SC1A and SC2A are bonded together, the input-output relationship between the logic circuit provided in the subchip SC1A and the logic circuit provided in the subchip SC2A can be matched. Similarly, when the subchips SC1B and SC2B are bonded together, the input-output relationship between the logic circuit provided in the subchip SC1B and the logic circuit provided in the subchip SC2B can be matched. Furthermore, when the subchips SC3A and SC0A are bonded together, the input-output relationship between the logic circuit provided in the subchip SC3A and the logic circuit provided in the subchip SC0A can be matched. Similarly, when the subchips SC3B and SC0B are bonded together, the input-output relationship between the logic circuit provided in the subchip SC3B and the logic circuit provided in the subchip SC0B can be matched. 5. 5. Second modification of the fifth embodiment The semiconductor memory device of the fifth embodiment described above has been described as an example in which two sub-chips SC are included in one core chip CC, but the present invention is not limited to this. For example, the core wafer CC is not limited to two, and an even number (4, 6, . . . ) of sub wafers SC may be stacked and configured. Fig. 57 is a cross-sectional view for explaining the laminated structure of the core wafer group according to the second modification of the fifth embodiment. As shown in FIG. 57 , the core chips CC0A and CC0B may also include four sub-chips SC0A to SC3A and SC0B to SC3B, respectively. With the above configuration, the area efficiency can be further improved as compared with the case where one core wafer CC is composed of two sub wafers SC. In addition, the wiring length of signals that must be communicated in the core chip CC can be further shortened. 5. 6. Third modification of the fifth embodiment The semiconductor memory device according to the fifth embodiment has been described as an example in which two sub-chips SC included in different core chips CC are provided independently of each other on the same semiconductor substrate SS. But it is not limited to this. For example, two sub-chips SC provided on the same semiconductor substrate SS may share the function of a common circuit provided in an adjacent area. Fig. 58 is a plan view for explaining the layout pattern of the sub-chip of the semiconductor memory device according to the third modification of the fifth embodiment. As shown in FIG. 58 , for example, the subchips SC0A and SC0B share a common circuit provided in the subchip SC of each other. The shared circuit can also operate as a circuit of any one of the subchips SC0A and SC0B. With the above configuration, the functions that can be shared among different core chips CC can be handled by one common circuit. Thereby, the circuit area can be further reduced. 6. Others Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments or changes thereof are included in the scope or spirit of the invention, and are also included in the inventions described in the claims and their equivalents.

1: memory system 2: controller 3: semiconductor memory device 5: processor 6: built-in memory 7: NAND interface circuit 8: buffer memory 9: host interface circuit 10: interface chip 11: core chip group 12: Memory cell array 13: Data transfer circuit 13L: Data transfer circuit 13R: Data transfer circuit 14: Logic control circuit 14L: Logic control circuit 14R: Logic control circuit 15: Sequencer 15L: Sequencer 15R: Sequencer 16: Voltage generating circuit 16L: Voltage generating circuit 16R: Voltage generating circuit 17: Driver set 17D, 17U: Driver set 17DL, 17UL: Driver set 17DR, 17UR: Driver set 18: Column decoder 18-0 to 18-3: Column decoding 19: sense amplifiers 19-0 to 19-3: sense amplifiers 20: semiconductor substrate 21: element layers 22-1 to 22-4: through holes 23-1 to 23-4: bumps 24-1 to 24 -4: Pad 25: Logic element layer 26: Logic element layer 27 to 33: Wiring layer 40: Semiconductor substrate 41: Element layer 42-1 to 42-4: Through hole 43 (43-1 to 43-4): Bumps 44-1 to 44-4: Pads 45: Logic element layer 46: Logic element layers 47 to 53: Wiring layer 60: Semiconductor substrate 61: Element layers 62L-1 to 62L-4: Through holes 62R-1 to 62R-4: Through hole 62R-3B: Through hole 63 (63L-1～63L-4, 63R-1～63R-4): Bump 63R-3B: Bump 64L-1～64L-4: Pad 64R -1 to 64R-4: Pad 64R-3B: Pad 65 to 67: Logic element layer 66A: Logic element layer 68 to 80: Wiring layer 70A to 73A: Wiring layer 74: Wiring layer 75: Wiring layer 76B: Wiring Layer 90: Semiconductor substrate 91: Element layers 92L-1 to 92L-4: Through holes 92R-1 to 92R-4: Through holes 93L-1 to 93L-4: Bumps 93R-1 to 93R-4: Bumps 94L -1 to 94L-4: Pads 94R-1 to 94R-4: Pads 95 to 97: Logic element layers 98 to 110: Wiring layer 120: Semiconductor substrate 121: Element layers 122-1 to 122-4: Through holes 123-1 to 123-4: bumps 124-1 to 124-4: pads 125: logic element layer 126: logic element layer 127 to 133: wiring layer 140: semiconductor substrate 141: element layer 142-1 to 142- 4: Through holes 142-3B: Through holes 143-1 to 143-4: Bumps 143-3B: Bumps 144-1 to 144-4: Pads 144-3B: Pads 145: Logic element layers 146 to 151 : Wiring layer 149B: Wiring layer 160: Semiconductor substrate 161: Element layers 162-1 to 162-4: Through holes 163-1 to 163-4: Bumps 164-1 to 164-4: Pads 165: Logic element layers 166 to 171: wiring layer 180: semiconductor substrate 181: element layers 182-1 to 182-4: through holes 183-1 to 183-4: bumps 184-1 to 184-4: pads 185: logic Element layer 186 : Logic element layers 187 to 193 : Wiring layer ADD : Address AreaA : Area AreaB : Area AreaC : Area B1 : Arrangement pattern B2 : Arrangement pattern B3 : Arrangement pattern B4 : Arrangement pattern CC0 to CC3 : Core wafer CC0A: Core Chip CC0B: Core Chip CC1A: Core Chip CC1B: Core Chip /CE,CLE,ALE,/WE,/RE,RE,/WP,/RB,DQS,/DQS,I/O<7:0>:Signal CMD: Command CS: Wafer Set CSa: Wafer Set CSb: Wafer Set DAT: Data DS1: Pin Contact Position DS2: Pin Contact Position DS3: Pin Contact Position DSU: Repeat Unit d1: Distance d2: Distance d3: Distance d4: Distance d5 : distance d6: distance d7: distance d8: distance d9: distance d10: distance d11: distance d11B: distance d12: distance d13: distance d14: distance d15: distance d16: distance GND: ground voltage LGA, LGA1, LGA2: logic circuit LGB, LGB1, LGB2: Logic Circuit MS1: Mask Set MS2: Mask Set MS3: Mask Set MS3a: Mask Set MS3b: Mask Set MS3c: Mask Set MS3d: Mask Set MS4: Mask Set MS6: mask set P1:symbol P2:symbol P3:symbol P4:symbol P5:symbol P6:symbol P7:symbol P8:symbol P9:symbol P10:symbol P11:symbol P12:symbol P13:symbol Q1:dot Q2:dot Q3: Point Q4: Point SC0 to SC3: Subwafer SC0A to SC3A: Subwafer SC0B to SC3B: Subwafer SL1 to SL8: Signal path SS0: Semiconductor substrate SS1: Semiconductor substrate SS2: Semiconductor substrate SS3: Semiconductor substrate T1a to T8a: Terminal T1b ~T8b: Terminal W1: Wafer W2: Wafer x: Direction y: Direction z: Direction

FIG. 1 is a block diagram for explaining the structure of the memory system of the first embodiment. FIG. 2 is a block diagram for explaining the structure of the semiconductor memory device of the first embodiment. FIG. 3 is a circuit diagram for explaining the configuration of the core chip group of the semiconductor memory device of the first embodiment. Fig. 4 is a plan view for explaining the structure of the core chip of the semiconductor memory device of the first embodiment. FIG. 5 is a cross-sectional view for explaining the structure of the core chip of the semiconductor memory device of the first embodiment. FIG. 6 is a plan view for explaining the structure of the core chip of the semiconductor memory device of the first embodiment. FIG. 7 is a cross-sectional view for explaining the structure of the core chip of the semiconductor memory device of the first embodiment. FIG. 8 is a cross-sectional view for explaining the structure of the core chip group of the semiconductor memory device of the first embodiment. FIG. 9 is a schematic diagram for explaining the method of manufacturing the semiconductor memory device of the first embodiment. FIG. 10 is a flowchart for explaining the method of manufacturing the semiconductor memory device of the first embodiment. FIG. 11 is a schematic diagram for explaining the method of manufacturing the semiconductor memory device of the first embodiment. Fig. 12 is a schematic diagram for explaining the method of manufacturing the semiconductor memory device of the first embodiment. FIG. 13 is a schematic diagram for explaining the method of manufacturing the semiconductor memory device of the first embodiment. Fig. 14 is a plan view for explaining the structure of a core chip of a semiconductor memory device according to a modification of the first embodiment. FIG. 15 is a schematic diagram for explaining a method of manufacturing a semiconductor memory device according to a modification of the first embodiment. FIG. 16 is a schematic diagram for explaining a method of manufacturing a semiconductor memory device according to a modification of the first embodiment. FIG. 17 is a schematic diagram for explaining a method of manufacturing a semiconductor memory device according to a modification of the first embodiment. Fig. 18 is a circuit diagram for explaining the configuration of the core chip group of the semiconductor memory device of the second embodiment. Fig. 19 is a cross-sectional view for explaining the structure of the core chip of the semiconductor memory device of the second embodiment. Fig. 20 is a cross-sectional view for explaining the structure of the core chip of the semiconductor memory device of the second embodiment. Fig. 21 is a cross-sectional view for explaining the structure of the core chip group of the semiconductor memory device of the second embodiment. FIG. 22 is a schematic diagram for explaining a method of manufacturing the semiconductor memory device of the second embodiment. Fig. 23 is a schematic diagram for explaining a method of manufacturing the semiconductor memory device of the second embodiment. FIG. 24 is a cross-sectional view for explaining the structure of the core chip of the semiconductor memory device according to the first modification of the second embodiment. FIG. 25 is a cross-sectional view for explaining the structure of the core chip of the semiconductor memory device according to the first modification of the second embodiment. FIG. 26 is a cross-sectional view for explaining the configuration of the core chip group of the semiconductor memory device according to the first modification of the second embodiment. FIG. 27 is a schematic diagram for explaining a method of manufacturing a semiconductor memory device according to a first modification of the second embodiment. 28(A) and (B) are schematic diagrams for explaining a method of manufacturing a semiconductor memory device according to a first modification of the second embodiment. Fig. 29 is a cross-sectional view for explaining the structure of the core chip of the semiconductor memory device of the third embodiment. Fig. 30 is a cross-sectional view for explaining the structure of the core chip of the semiconductor memory device of the third embodiment. Fig. 31 is a cross-sectional view for explaining the structure of the core chip of the semiconductor memory device of the third embodiment. Fig. 32 is a cross-sectional view for explaining the structure of the core chip of the semiconductor memory device of the third embodiment. Fig. 33 is a cross-sectional view for explaining the structure of the core chip group of the semiconductor memory device of the third embodiment. Fig. 34 is a schematic diagram for explaining the method of manufacturing the semiconductor memory device of the third embodiment. Fig. 35 is a block diagram for explaining the configuration of the core chip group of the semiconductor memory device of the fourth embodiment. Fig. 36 is a circuit diagram for explaining the configuration of the core chip group of the semiconductor memory device of the fourth embodiment. Fig. 37 is a plan view for explaining the structure of the core chip of the semiconductor memory device of the fourth embodiment. Fig. 38 is a cross-sectional view for explaining the structure of the core chip of the semiconductor memory device of the fourth embodiment. Fig. 39 is a plan view for explaining the structure of the core chip of the semiconductor memory device of the fourth embodiment. Fig. 40 is a cross-sectional view for explaining the structure of the core chip of the semiconductor memory device of the fourth embodiment. Fig. 41 is a cross-sectional view for explaining the structure of the core chip group of the semiconductor memory device of the fourth embodiment. Fig. 42 is a schematic diagram for explaining a method of manufacturing the semiconductor memory device of the fourth embodiment. 43(A) and (B) are schematic diagrams for explaining the effect of the semiconductor memory device of the fourth embodiment. 44(A) and (B) are schematic diagrams for explaining the effect of the semiconductor memory device of the fourth embodiment. Fig. 45 is a cross-sectional view for explaining the structure of the core chip of the semiconductor memory device according to the first modification of the fourth embodiment. Fig. 46 is a cross-sectional view for explaining the structure of the core chip of the semiconductor memory device according to the first modification of the fourth embodiment. Fig. 47 is a cross-sectional view for explaining the structure of the core chip of the semiconductor memory device according to the first modification of the fourth embodiment. Fig. 48 is a cross-sectional view for explaining the structure of the core chip group of the semiconductor memory device according to the first modification of the fourth embodiment. Fig. 49 is a cross-sectional view for explaining the structure of a core chip group of a semiconductor memory device according to a second modification of the fourth embodiment. Fig. 50 is a plan view for explaining the structure of a core chip of a semiconductor memory device according to a third modification of the fourth embodiment. Fig. 51 is a plan view for explaining the structure of a core chip of a semiconductor memory device according to a third modification of the fourth embodiment. Fig. 52 is a block diagram for explaining the configuration of the core chip group of the semiconductor memory device of the fifth embodiment. Fig. 53 is a plan view for explaining the structure of the core chip of the semiconductor memory device of the fifth embodiment. Fig. 54 is a cross-sectional view for explaining the structure of the core chip group of the semiconductor memory device of the fifth embodiment. Fig. 55 is a schematic diagram for explaining a method of manufacturing the semiconductor memory device of the fifth embodiment. Fig. 56 is a cross-sectional view for explaining the configuration of the core chip group of the semiconductor memory device according to the first modification of the fifth embodiment. Fig. 57 is a cross-sectional view for explaining the structure of a core chip group of a semiconductor memory device according to a second modification of the fifth embodiment. Fig. 58 is a plan view for explaining the structure of a core chip of a semiconductor memory device according to a third modification of the fifth embodiment.

11: Core chip group

CC0~CC3: core chip

CS:Chipset

SL1~SL4: Signal path

x: direction

y: direction

z: direction

Claims (33)

A semiconductor memory device includes a first chip and a second chip, the first chip includes: a first substrate including a first through hole and a second through hole; and a first element layer disposed on the first substrate On the upper surface, and including the first bonding pad and the second bonding pad on the upper surface; The above-mentioned 2nd chip is provided with: The 2nd substrate, it comprises the 3rd through hole and the 4th through hole; And The 2nd element layer, its be arranged on the upper surface of the above-mentioned second substrate, and include a third pad and a fourth pad on the upper surface; the upper surface of the above-mentioned second element layer is oppositely arranged on the upper surface of the above-mentioned first element layer; The first pad and the third pad, and the second pad and the fourth pad are arranged symmetrically with respect to the surfaces of the first element layer and the second element layer facing each other, and are electrically conductive to each other. Connecting; The first element layer and the second element layer further include: A first signal line, which is electrically connected to the first through hole and the third through hole via the first pad and the third pad between; and a second signal line, which is electrically connected between the second through hole and the fourth through hole through the second pad and the fourth pad without passing through a logic circuit; the first element The layer further includes a first logic circuit, the first logic circuit is disposed on the path of the first signal line, and includes an input terminal electrically connected to the first through hole, and an input terminal electrically connected to the first pad an output end; the second element layer further includes a second logic circuit, the second logic circuit is disposed on the path of the first signal line, and includes the first pad and the second pad electrically connected to the above The input end of the output end of the first logic circuit is electrically connected to the output end of the second through hole. The semiconductor memory device of claim 1, wherein the first logic circuit and the second logic circuit are arranged symmetrically with respect to the surfaces of the first element layer and the second element layer facing each other. The semiconductor memory device of claim 1, wherein the first logic circuit and the second logic circuit are arranged asymmetrically with respect to the surfaces of the first element layer and the second element layer that face each other. The semiconductor memory device of claim 3, wherein the first element layer and the second element layer are provided with the same layout pattern. The semiconductor memory device of claim 3, wherein the first element layer and the second element layer are provided with different layout patterns. The semiconductor memory device of claim 1, wherein each of the first element layer and the second element layer is contained in core chips different from each other. The semiconductor memory device of claim 1, wherein the first element layer and the second element layer are contained in the same core chip. The semiconductor memory device of claim 1, further comprising a third chip, the third chip further comprising: a third substrate including a fifth through hole and a sixth through hole; and a third element layer disposed on the above-mentioned first 3 on the upper surface of the substrate, and the upper surface includes a fifth pad and a sixth pad; The lower surface of the third substrate is oppositely disposed on the lower surface of the second substrate; The third through hole and The fifth through hole, the fourth through hole, and the sixth through hole are symmetrically arranged with respect to the opposing surfaces of the second substrate and the third substrate, and are electrically connected to each other; The first signal line Further, through the third through hole and the fifth through hole, it is electrically connected between the first through hole and the fifth pad; the second signal line is further passed through the fourth through hole and the sixth through hole , which is electrically connected between the second through hole and the sixth pad without going through a logic circuit. The semiconductor memory device according to claim 8, wherein the third pad and the fifth pad, and the fourth pad and the sixth pad are surfaces opposed to the second substrate and the third substrate And set symmetrically. The semiconductor memory device of claim 9, further comprising a fourth chip, the above-mentioned fourth chip further comprising: a fourth substrate including a seventh through hole and an eighth through hole; and a fourth element layer disposed on the above-mentioned first 4 on the upper surface of the substrate, and the upper surface includes the seventh pad and the eighth pad; The upper surface of the fourth element layer is oppositely disposed on the upper surface of the third element layer; The fifth solder The pads, the seventh pad, and the sixth pad and the eighth pad are arranged symmetrically with respect to the opposite surfaces of the third element layer and the fourth element layer, and are electrically connected to each other; The first signal line is electrically connected between the first through hole and the seventh through hole through the fifth bonding pad and the seventh bonding pad; the second signal line is further connected through the sixth bonding pad and the seventh through hole. 8 pads are electrically connected between the second through hole and the eighth through hole without going through a logic circuit. The semiconductor memory device of claim 10, wherein the first pad and the seventh pad, and the second pad and the eighth pad are surfaces facing the second substrate and the third substrate And set symmetrically. The semiconductor memory device of claim 11, wherein the first through hole and the third through hole, and the second through hole and the fourth through hole are opposed to the first element layer and the second element layer. arranged symmetrically. The semiconductor memory device of claim 11, wherein the first through hole and the third through hole, and the second through hole and the fourth through hole are opposed to the first element layer and the second element layer. The faces are set asymmetrically. The semiconductor memory device of claim 8, wherein the first element layer, the second element layer, and the third element layer are contained in the same core wafer. The semiconductor memory device of claim 8, wherein the first element layer and the third element layer are provided with the same layout pattern. The semiconductor memory device of claim 8, wherein the first element layer and the third element layer are provided with different layout patterns. The semiconductor memory device of claim 1, wherein the first substrate further includes a ninth through hole and a tenth through hole; the first element layer further includes a ninth pad and a tenth pad, and the ninth pad is provided On the upper surface of the first element layer, at a position symmetrical to the first pad with respect to the center of the first element layer, the tenth pad is disposed on the upper surface of the first element layer. The center of the first element layer is symmetrical with the second pad; The second substrate further includes an 11th through hole and a 12th through hole; The second element layer further includes an 11th pad and a 12th solder pad pad, the 11th pad is arranged on the upper surface of the above-mentioned second element layer at a position symmetrical to the above-mentioned third pad relative to the center of the above-mentioned second element layer, and the 12th solder pad is arranged on the above-mentioned 1st pad 2 on the upper surface of the element layer at a position that is symmetrical with respect to the center of the second element layer and the fourth pad; the ninth and eleventh pads, and the tenth and the twelfth The pads are arranged symmetrically with respect to the opposite surfaces of the first element layer and the second element layer, and are electrically connected to each other; the first element layer and the second element layer further comprise: a third signal line, It is electrically connected between the ninth through hole and the eleventh through hole through the ninth pad and the eleventh pad; at least one logic circuit disposed on the path of the third signal line; and the first 4. The signal line is electrically connected between the tenth through hole and the twelfth through hole through the tenth pad and the twelfth pad without going through a logic circuit. The semiconductor memory device of claim 17, wherein said first through hole, said second through hole, said third through hole, said fourth through hole, said first pad, said second pad, and said third pad The pad and the fourth pad are contained in the first core wafer; The ninth through hole, the tenth through hole, the eleventh through hole, the twelfth through hole, the ninth through hole, the tenth through hole , the 11th bonding pad and the 12th bonding pad are contained in the second core chip. The semiconductor memory device of claim 4 or 5, wherein the first element layer further includes a first peripheral circuit electrically connected to the first signal line, the second element layer further includes a peripheral circuit corresponding to the first peripheral circuit, and A second peripheral circuit electrically disconnected from the second signal line. The semiconductor memory device of claim 7, wherein the first element layer further includes a first portion of a peripheral circuit electrically connected to the first signal line, and the second element layer further includes a peripheral circuit that is electrically connected to the second signal line The second part of the above-mentioned peripheral circuit, the first part of the above-mentioned peripheral circuit and the second part of the above-mentioned peripheral circuit are included in the overlapping area in the stacking direction. The semiconductor memory device of claim 17, wherein the first element layer further includes a shared circuit, and the shared circuit is shared by the first part of the first element layer and the second part of the first element layer. The semiconductor memory device of claim 17, wherein the second element layer further includes a third logic circuit, and the third logic circuit is disposed on the path of the third signal line and includes a circuit electrically connected to the eleventh through hole. an input end, and an output end electrically connected to the eleventh pad; the first element layer further includes a fourth logic circuit, the fourth logic circuit is disposed on the path of the third signal line, and includes a path through the first The ninth pad and the eleventh pad are electrically connected to the input end of the output end of the third logic circuit, and are electrically connected to the output end of the ninth through hole. A method of manufacturing a semiconductor memory device, comprising the following steps: disposing a first element layer on the upper surface of a first wafer, and forming a second element layer on the upper surface of the second wafer; The upper surface is opposite to the upper surface of the second element layer, and the first wafer and the second wafer are bonded together; The lower surface of the bonded first wafer and the lower surface of the second wafer are bonded together. The surface is probed; and the probed first wafer and the second wafer are diced at the same time to produce two or more wafer sets; and the arrangement of the first element layer and the second element layer includes the following Steps: Form a first pad and a second pad on the upper surface of the first element layer; On the upper surface of the second element layer, opposite to the first element layer and the second element layer On the surface, a third pad is formed at a position symmetrical with the first pad, and a fourth pad is formed at a position symmetrical with the second pad; Form: a first signal line electrically connected to the first pad The first part of the second signal line is electrically connected to the second pad, the second part of the first signal line is electrically connected to the third pad, and the fourth Pad the second portion of the second signal line electrically connected; and at least one logic circuit is formed on the path of the first signal line. The method for manufacturing a semiconductor memory device of claim 23, wherein the first element layer and the second element layer are provided by the same mask set. The method for manufacturing a semiconductor memory device of claim 24, wherein in one of the two or more chip sets, the first element layer and the second element layer are provided with different layout patterns. The method for manufacturing a semiconductor memory device according to claim 25, wherein in one of the two or more wafer sets, the first element layer and the second element layer are relative to the first element layer and the second element layer. Symmetrically arranged with respect to the opposite face. The method for manufacturing a semiconductor memory device according to claim 26, wherein in one of the two or more wafer sets, the first element layer and the second element layer are provided with different wiring patterns. The method for manufacturing a semiconductor memory device according to claim 24, wherein in one of the two or more chip sets, the first element layer and the second element layer are provided with the same layout pattern. The method for manufacturing a semiconductor memory device according to claim 23, wherein in one of the two or more wafer sets, the arrangement pattern of the terminals used for probing the lower surface of the first wafer is different from that of the second wafer. The arrangement patterns of the terminals used for probing on the lower surface of the wafer are different from each other. The method for manufacturing a semiconductor memory device according to claim 23, wherein in one of the two or more wafer sets, the arrangement pattern of the terminals used for probing the lower surface of the first wafer is different from that of the second wafer. The configuration pattern of the terminals used for probing on the lower surface of the wafer is the same. The method for manufacturing a semiconductor memory device according to claim 23, wherein in one of the two or more chip sets, the first element layer and the second element layer are contained in core chips that are different from each other. The method for manufacturing a semiconductor memory device according to claim 23, wherein in one of the two or more wafer sets, the first element layer and the second element layer are contained in the same core wafer. The method for manufacturing a semiconductor memory device of claim 23, wherein in one of the two or more chip sets, the first element layer includes the first part of the first core chip and the first part of the second core chip, The above-mentioned second element layer includes the second part of the first core chip and the second part of the second core chip.

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