TW202226615A - Light-emitting device and manufacturing method thereof - Google Patents

Abstract

A light emitting device is disclosed. The light emitting device includes: a support substrate; a semiconductor stack located on the support substrate and including a first type semiconductor layer, a second type semiconductor layer, an active layer located between the first type semiconductor layer and the second type semiconductor layer, and an undoped semiconductor layer located on the first type semiconductor layer; and a first electrode located on the undoped semiconductor layer and the first type semiconductor layer, wherein the first type semiconductor layer includes a first region and a second region, the undoped semiconductor layer is located on the first region, the second region is not covered by the undoped semiconductor layer, the undoped semiconductor layer includes a first rough structure, the first type semiconductor layer includes a second rough structure in the second region, and the first electrode contacts with the second rough structure.

Description

Light-emitting element and method of manufacturing the same

The present application relates to a light-emitting element, more specifically, to a light-emitting element with improved brightness.

Light-emitting diodes (LEDs) in solid-state light-emitting devices have low power consumption, low heat generation, long life, small size, fast response and good optoelectronic properties, such as stable emission wavelengths, so they have been widely used. It is used in household devices, indicator lights and optoelectronic products, etc.

A conventional light-emitting diode includes a substrate, an n-type semiconductor layer, an active layer and a p-type semiconductor layer formed on the substrate, and p and n-electrodes formed on the p-type/n-type semiconductor layers, respectively. When the light-emitting diode is energized through the electrode, and the forward bias is at a certain value, the holes from the p-type semiconductor layer and the electrons from the n-type semiconductor layer combine in the active layer to emit light. However, with the application of light-emitting diodes to different optoelectronic products, the brightness specifications of light-emitting diodes are also improved. How to improve the brightness is one of the research and development goals of those skilled in the art.

The present application discloses a wafer carrier, which includes a support substrate; a semiconductor stack is disposed on the support substrate, and includes a first-type semiconductor layer, a second-type semiconductor layer, and an active layer on the first-type semiconductor layer and the second-type semiconductor layer and the undoped semiconductor layer is arranged on the first type semiconductor layer; and the first electrode is arranged on the undoped semiconductor layer and the first type semiconductor layer; wherein, the first type semiconductor layer includes a first region and a second region, the undoped semiconductor layer is disposed on the first region, the second region is not covered by the undoped semiconductor layer, the undoped semiconductor layer has a first roughness structure and the first type semiconductor layer has a second roughness in the second region structure, the first electrode contacts the second rough structure.

The present application discloses a method for manufacturing a light-emitting device, which includes providing a growth substrate; sequentially forming a buffer layer, an undoped semiconductor layer, a first-type semiconductor layer, an active layer and a second-type semiconductor layer on the growth substrate; forming A reflective metal layer and a barrier layer are placed on the second type semiconductor layer; a supporting substrate is provided; a connecting layer is formed to connect the barrier layer and the supporting substrate; the growth substrate and the buffer layer are removed; the undoped semiconductor layer is patterned to form a first roughness structure; forming an insulating layer on the undoped semiconductor layer; patterning the insulating layer and the undoped semiconductor layer to form a recessed area to expose the upper surface of the first type semiconductor layer; and forming a first electrode to fill the recessed area to contact the upper surface .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art of the present invention can fully understand the spirit of the present invention. The present invention is not limited to the following embodiments, but may be implemented in other forms. In this specification, there are some identical symbols, which represent elements having the same or similar structures, functions, and principles, and those with general knowledge in the industry can infer them according to the teachings of this specification. For the sake of brevity of the description, elements with the same symbols will not be repeated.

FIG. 1 shows a schematic cross-sectional view of a light-emitting device 1 according to an embodiment of the present application. The light-emitting element 1 includes a support substrate 100 , a semiconductor stack 110 is formed on the support substrate 100 and includes an upper surface S and a first surface S1 away from the support substrate 100 , and a patterned dielectric layer 120 is formed on the semiconductor stack 110 facing the support substrate 100 . On the other surface, the reflective metal layer 130 covers the patterned dielectric layer 120, and the barrier layer 132 covers the reflective metal layer 130 and the patterned dielectric layer 120. In one embodiment, the barrier layer 132 can cover the reflective metal layer At the edge of the barrier layer 130 , a cross-sectional width of the barrier layer 132 may be slightly wider than that of the semiconductor stack 110 . The connection layer 134 covers the barrier layer 132 and is connected to the support substrate 100 , and the insulating layer 140 and the first electrode 150 are formed on the semiconductor stack 110 .

As shown in FIG. 1 , in this embodiment, the semiconductor stack 110 includes an undoped semiconductor layer 112 , a first-type semiconductor layer 114 , an active layer 116 , and a second-type semiconductor layer 118 . The layers are stacked sequentially from top to bottom, wherein the first type semiconductor layer 114 includes the upper surface S of the semiconductor stack 110 , the undoped semiconductor layer 112 is formed on the first type semiconductor layer 114 , and the undoped semiconductor layer 112 has a first surface S1, the first type semiconductor layer 114 includes a first region R1 covered by the undoped semiconductor layer 112 and a second region R2 not covered by the undoped semiconductor layer 112, wherein the second region R2 has the first type semiconductor layer 114 The upper surface S of the first electrode 150 is formed on the first type semiconductor layer 114 and the undoped semiconductor layer 112 and contacts the upper surface S of the first type semiconductor layer 114 , and the insulating layer 140 can conform to the shape of the semiconductor stack 110 to cover On the first surface S1 of the undoped semiconductor layer 112 and covering the side surface of the undoped semiconductor layer 112 and the side surface of the semiconductor stack 110 , the lower end of the insulating layer 140 is connected to the patterned dielectric layer 120 .

In one embodiment, the first-type semiconductor layer 114 and the second-type semiconductor layer 118, such as a cladding layer or a confinement layer, have different conductivity types, electrical properties, polarities or uses. Doping elements that provide electrons or holes. For example, the first-type semiconductor layer 114 is an n-type semiconductor, and the second-type semiconductor layer 118 is a p-type semiconductor. The active layer 116 is formed between the first type semiconductor layer 114 and the second type semiconductor layer 118 . Electrons and holes are combined in the active layer 116 under the driving of current, converting electrical energy into light energy to emit light. The wavelength of light emitted by the light emitting element 1 or the semiconductor stack 110 can be adjusted by changing the physical properties and chemical composition of one or more layers in the semiconductor stack 110 . The material of the semiconductor stack 110 may comprise a III-V semiconductor material of _AlxInyGa (1- _{xy )} N or _AlxInyGa (1- _{xy )} P, where 0≤x, y≤1; x+ y≤1. When the material of the semiconductor stack 110 is AlInGaP series, red light having a wavelength between 610 nm and 650 nm or yellow light having a wavelength between 550 nm and 570 nm can be emitted. When the material of the semiconductor stack 110 is InGaN series, blue light or deep blue light with a wavelength between 400 nm and 490 nm or green light with a wavelength between 490 nm and 550 nm can be emitted. When the material of the semiconductor stack 110 is AlGaN series, UV light with a wavelength between 400 nm and 250 nm can be emitted. The active layer 116 may be a single heterostructure (single heterostructure; SH), a double heterostructure (DH), a double-side double heterostructure (DDH), a multi-quantum well (MQW) ). The material of the active layer 116 may be an i-type, p-type or n-type semiconductor. The material of the undoped semiconductor layer 112 may include GaN, AlGaN or AlN.

As shown in FIG. 1 , in this embodiment, the first surface S1 of the undoped semiconductor layer 112 has a first roughness structure P1 , the upper surface S of the first-type semiconductor layer 114 has a second roughness structure P2 , the first roughness The structure P1 and the second rough structure P2 can respectively include angular cones, cones, domes and other shapes, wherein the pyramids can include polygonal pyramids such as triangular pyramids and quadrangular pyramids, the cones can include regular cones or/and elliptical cones, and the domes can include positive For a dome or/and an elliptical top, the shapes of the first roughness structure P1 and the second roughness structure P2 may be different or the same, and the dimensions of the first roughness structure P1 and the second roughness structure P2 may be different or the same. In one embodiment, the insulating layer 140 has a concave-convex surface S2 conforming to the first roughness structure P1. The undoped semiconductor layer 112 covers the first region R1 on both sides of the first-type semiconductor layer 114 , and does not cover the second region R2 in the middle of the first-type semiconductor layer 114 . The light-emitting element 1 has a recessed area corresponding to the second region R2 G, the first electrode 150 is formed on the second region R2 and part of the first region R1, the first electrode 150 has a recess C corresponding to the second region R2, the insulating layer 140 is located on the first region and formed on the first electrode 150 and Between the undoped semiconductor layers 112 , the first electrode 150 covers a part of the insulating layer 140 . In one embodiment, the first electrode 150 corresponding to the first region R1 and the second region R2 has concave-convex surfaces corresponding to the first roughness structure P1 and the second roughness structure P2 respectively.

In one embodiment, the material of the patterned dielectric layer 120 may include an insulating oxide, nitride, silicon oxide, titanium oxide, aluminum oxide, magnesium fluoride, or silicon nitride. The material of the insulating layer 140 may include silicon nitride or silicon oxide. The material of the patterned dielectric layer 120 may be different from the material of the insulating layer 140 . In one embodiment, the material of the patterned dielectric layer 120 may be titanium dioxide (TiO ₂ ), and the material of the insulating layer 140 may be silicon dioxide (SiO ₂ ) or silicon nitride (SiN _x or Si ₃ N ₄ ). The material of the first electrode 150 may include silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt), ruthenium ( Ru), tungsten (W) or an alloy or stack of the above materials, the material of the reflective metal layer 130 may include silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt), ruthenium (Ru) or alloys or laminates of the above materials. In one embodiment, the light-emitting element 1 may include a transparent conductive layer (not shown) formed between the patterned dielectric layer 120 and the reflective metal layer 130 . The material of the transparent conductive layer may include graphene, indium tin oxide (ITO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc oxide (ZnO), or indium zinc oxide (IZO). The material of the barrier layer 132 may include chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), zinc (Zn), or alloys or stacks of the above materials. In one embodiment, when the barrier layer 132 is a metal stack, the barrier layer 132 is formed by alternately stacking two or more layers of metals, such as Cr/Pt, Cr/Ti, Cr/TiW, Cr /W, Cr/Zn, Ti/Pt, Ti/W, Ti/TiW, Ti/Zn, Pt/TiW, Pt/W, Pt/Zn, TiW/W, TiW/Zn, or W/Zn, etc. The material of the connection layer 134 may include gold (Au), titanium (Ti), chromium (Cr), tungsten (W), zinc (Zn), platinum (Pt) or alloys or stacks of the above materials. In one embodiment, when the connection layer 134 is a metal stack, the connection layer 134 is formed by alternately stacking two or more layers of metals, such as Ti/Au, Cr/Pt, Cr/Ti, Cr/TiW , Cr/W, Cr/Zn, Ti/Pt, Ti/W, Ti/TiW, Ti/Zn, Pt/TiW, Pt/W, Pt/Zn, TiW/W, TiW/Zn, or W/Zn, etc. . The material of the support substrate 100 may include a conductive substrate or an insulating substrate; the material of the conductive substrate may include a metal material or a semiconductor material, wherein the metal material includes copper (Cu), gold (Au), nickel (Ni), molybdenum (Mo), tungsten Copper (Cu-W) or alloys or stacks of the above materials, and semiconductor materials include Si, Ge, GaAs, ZnO, SiC, or SiSe. The material of the insulating substrate may include sapphire (Sapphire) or aluminum nitride (AlN). In one embodiment, when the support substrate 100 is a conductive substrate, the support substrate 100 can be used as an electrode to provide electrical energy to the light-emitting element 1 , or a second electrode (not shown) is formed on a side of the support substrate 100 away from the semiconductor stack 110 . on the surface. When the supporting substrate 100 is an insulating substrate, a yellow light developing process may be used to remove part of the first-type semiconductor layer 114 and the active layer 116 to expose part of the second-type semiconductor layer 118 or the reflective metal layer 130 , and the exposed A second electrode (not shown) is formed on the region to be electrically connected to the second-type semiconductor layer 118 .

2A to FIG. 2K are schematic cross-sectional views at various stages in the manufacturing method of the light-emitting device 2 according to an embodiment of the present application. In the embodiments shown in FIGS. 2A to 2K , the structure and material of the light-emitting element 2 are substantially the same as those of the light-emitting element 1 shown in FIG. 1 , and thus will not be repeated here. The process steps of the light-emitting element 2 described below are also applicable to the relevant embodiments of the light-emitting element 1 described above, and thus are not repeated here.

As shown in FIG. 2A , first, a buffer layer 211 , an undoped semiconductor layer 212 , a first-type semiconductor layer 214 , an active layer 216 and a second-type semiconductor layer 218 are sequentially formed on the growth substrate 201 . The growth substrate 201 may include Gallium arsenide (GaAs) substrates for the growth of gallium indium phosphide (AlGaInP), and gallium phosphide (GaP) substrates, or sapphire ( Al2O3) substrate, gallium nitride (GaN) substrate, silicon carbide (SiC) substrate, and aluminum nitride (AlN) substrate. The growth substrate 201 may be a patterned substrate, that is, the growth substrate 201 has a patterned structure. In one embodiment, the patterned structure slows down or suppresses the dislocation caused by lattice mismatch between the growth substrate 201 and the semiconductor stack 210 , thereby improving the epitaxial quality of the semiconductor stack 210 . In one embodiment, the method of forming the semiconductor stack 210 on the growth substrate 201 includes metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or ion plating , such as sputtering or vapor deposition. The buffer layer 211 can reduce the above-mentioned lattice mismatch and suppress dislocation, thereby improving the epitaxial quality. The material of the buffer layer 211 may include GaN, AlGaN or AlN. In one embodiment, the buffer layer 211 includes a plurality of sub-layers (not shown), and the sub-layers include the same material or different materials. In one embodiment, the buffer layer 211 includes two sub-layers, wherein the growth method of the first sub-layer is sputtering, and the growth method of the second sub-layer is MOCVD. In one embodiment, the buffer layer 211 further includes a third sublayer. The growth mode of the third sublayer is MOCVD, and the growth temperature of the second sublayer is higher or lower than the growth temperature of the third sublayer. In one embodiment, the first, second and third sublayers comprise the same material or different materials, eg, AlN, GaN, AlGaN. In one embodiment, the buffer layer 211 includes two sub-layers of AlN and GaN, wherein the AlN sub-layer can be grown by sputtering, and the GaN sub-layer can be grown by MOCVD. In one embodiment, both the AlN sublayer and the GaN sublayer are grown by MOCVD. Next, referring to FIG. 2A , a patterned dielectric layer 220 , a reflective metal layer 230 and a barrier layer 232 are sequentially formed on the second-type semiconductor layer 218 .

As shown in FIG. 2B , the support substrate 200 can be connected to the semiconductor stack 210 through a connection layer 234 , the barrier layer 232 can be interposed between the connection layer 234 and the reflective metal layer 230 , and the connection layer 234 can be interposed between the barrier layers between the layer 232 and the support substrate 200 . In one embodiment, the connection layer 234 connects the barrier layer 232 and the support substrate 200 to be bonded through a high temperature and high pressure process. Next, as shown in FIGS. 2C-2D , after the support substrate 200 is connected to the semiconductor stack 210 , the growth substrate 201 can be removed to expose the buffer layer 211 . The exposed buffer layer 211 after the growth substrate 201 is removed will form a patterned surface due to the transfer of the patterned structure of the growth substrate 201 to the surface of the buffer layer 211 . The manner of removing the growth substrate 201 includes laser lift off (LLO) or grinding, wherein the grinding may include chemical mechanical polishing/planarization (CMP). The material of the support substrate 200 may include a conductive substrate or an insulating substrate; the material of the conductive substrate may include a metal material or a semiconductor material, wherein the metal material includes copper (Cu), gold (Au), nickel (Ni), molybdenum (Mo), tungsten Copper (Cu-W) or alloys or stacks of the above materials, and semiconductor materials include Si, Ge, GaAs, ZnO, SiC, or SiSe. The material of the insulating substrate may include sapphire (Sapphire) or aluminum nitride (AlN). In one embodiment, when the supporting substrate 200 is a conductive substrate, the supporting substrate 200 can be used as an electrode to provide electrical energy to the light-emitting element 1 , or a second electrode (not shown) is formed on a side of the supporting substrate 200 away from the semiconductor stack 210 . on the surface. When the supporting substrate 200 is an insulating substrate, part of the first-type semiconductor layer 214 and the active layer 216 may be removed by a yellow light developing process, and a part of the second-type semiconductor layer 218 or the reflective metal layer 230 may be exposed. A second electrode (not shown) is formed on the region to be electrically connected to the second type semiconductor layer 218 .

As shown in FIG. 2E, the buffer layer 211 is removed to expose the undoped semiconductor layer 212. The method of removing the buffer layer 211 may include dry etching or wet etching, wherein the dry etching is, for example, inductively coupled plasma , ICP) etching, reactive ion etching (reactive ion etching, RIE), etc., the etching solution for wet etching is, for example, hydrofluoric acid (HF), phosphoric acid (HPO ₃ ), sulfuric acid (H ₂ SO ₄ ), potassium hydroxide ( KOH) etc. In one embodiment, before removing the buffer layer 211, the patterned structure on the surface of the buffer layer 211 may be smoothed first, and the smoothing method may include grinding, dry etching, etc. Mechanical polishing/planarization, CMP), dry etching may include inductively coupled nuclear plasma etching, reactive ion etching, etc., so that the height difference on the surface of the buffer layer 211 can be reduced, for example, the height difference is between 0 and 0.5 μm, so as to reduce the subsequent The etching process produces over-etching. In one embodiment, the surface of the undoped semiconductor layer 212 exposed by removing the buffer layer 211 becomes a non-planar surface due to the etching process for removing the buffer layer 211 .

Next, as shown in FIG. 2F , the undoped semiconductor layer 212 is patterned from the surface to form a first rough structure P1 , wherein the surface of the first rough structure P1 constitutes the first surface S1 of the patterned undoped semiconductor layer 212 , And the first surface S1 is a roughened surface. The light extraction rate can be improved by the first rough structure P1. The method of patterning the undoped semiconductor layer 212 may include dry etching and/or wet etching, wherein the dry etching is, for example, inductively coupled nuclear plasma etching, reactive ion etching, etc., and the etching solution of the wet etching is, for example, hydrofluoric acid, phosphoric acid, etc. , sulfuric acid, potassium hydroxide, etc. In one embodiment, before patterning the undoped semiconductor layer 212, the thickness of the undoped semiconductor layer 212 can be thinned first, and the thinning method can include grinding, dry etching, etc., wherein the dry etching is, for example, an inductively coupled nuclear power plant. Plasma etching, reactive ion etching, etc., polishing such as chemical mechanical polishing/planarization, etc. In one embodiment, the thickness of the undoped semiconductor layer 212 after patterning is about 0.5 to 2.5 μm. The thickness of the undoped semiconductor layer 212 after thinning and patterning is about 0.1 times to 0.7 times the thickness of the first electrode 250 in FIG. 2J . In one embodiment, the thickness of the undoped semiconductor layer 212 is about the thickness of the first electrode 250 . An electrode 250 is 0.12 times to 0.63 times the thickness. By adjusting the height difference of the undoped semiconductor layer 212, when the first electrode 250 is formed on the undoped semiconductor layer 212 and the first type semiconductor layer 214, the coverage of the first electrode 250 can be improved, so as to improve the subsequent electrical conductivity. reliability of sexual connection.

As shown in FIG. 2G , by patterning the semiconductor stack 210 and removing part of the semiconductor stack 210 to expose the patterned dielectric layer 220 , a wafer separation region is formed, wherein the wafer separation region defines the periphery of the light-emitting element 2 . The method of patterning the semiconductor stack 210 may include dry etching or wet etching, wherein the dry etching is, for example, inductively coupled nuclear plasma etching, reactive ion etching, etc., and the etching solution of the wet etching is, for example, hydrofluoric acid, phosphoric acid, sulfuric acid, hydrogen Potassium oxide etc. In one embodiment, the thickness of the exposed patterned dielectric layer 220 is less than the thickness of the unexposed patterned dielectric layer 220 . Next, as shown in FIG. 2H , an insulating layer 240 is formed on the undoped semiconductor layer 212 , the insulating layer 240 covers the first surface S1 of the undoped semiconductor layer 212 and the side surfaces of the semiconductor stack 210 , and the insulating layer 240 can be The concave-convex surface S2 is formed according to the first rough structure P1 of the undoped semiconductor layer 212 , and the method of forming the insulating layer 240 may include plasma-enhanced chemical vapor deposition (PECVD).

As shown in FIG. 2I , the patterned insulating layer 240 and the undoped semiconductor layer 212 form a recessed region G to expose the upper surface S of the first type semiconductor layer 214 , wherein the first type semiconductor layer 214 has the insulating layer 240 and the undoped semiconductor layer 214 . The first region R1 covered by the doped semiconductor layer 212 and the second region R2 not covered by the insulating layer 240 and the undoped semiconductor layer 212, and the second region R2 corresponds to the recessed region G, the patterned insulating layer 240 and the undoped semiconductor The method of the layer 212 may include dry etching or wet etching, wherein the dry etching is such as inductively coupled nuclear plasma etching, reactive ion etching, etc., and the etching solution of the wet etching is, for example, hydrofluoric acid, phosphoric acid, sulfuric acid, potassium hydroxide, etc. The thickness of the first type semiconductor layer 214 in the first region R1 is about 0.1 times to 0.6 times the thickness of the first electrode 250 , preferably 0.12 times to 0.5 times, and the thickness of the first type semiconductor layer 214 in the second region R2 is about It is 0.1 times to 0.5 times the thickness of the first electrode 250, preferably 0.12 times to 0.45 times, wherein the thickness of the first type semiconductor layer 214 in the second region R2 is smaller than the thickness of the first type semiconductor layer 214 in the first region R1 . In one embodiment, the thickness of the first type semiconductor layer 214 in the first region R1 is about 0.5 to 2 μm, and the thickness of the first type semiconductor layer 214 in the second region R2 is about 0.5 to 1.8 μm.

As shown in FIG. 2J , a first electrode 250 is formed to fill the recessed region G to contact the upper surface S of the first-type semiconductor layer 214 , wherein the first electrode 250 covers part of the insulating layer 240 on the first region R1 and is not doped The semiconductor layer 212, and the first electrode 250 has a recess C in the corresponding recessed region G (ie, the second region R2), the method of forming the first electrode 250 may include sputtering or/and electron-beam deposition (electron-beam) gun evaporation). In one embodiment, before the first electrode 250 is formed, the photoresist opening can be defined by a yellow photolithography process, and then the first electrode 250 is formed by sputtering or/and evaporation, and the patterned insulating layer 240 and the undoped Before forming the recessed region G in the hetero semiconductor layer 212 , a photoresist opening can also be defined by a yellow photolithography process, wherein the photoresist opening for forming the first electrode 250 is larger than the photoresist opening for patterning the insulating layer 240 and the undoped semiconductor layer 212 , the first electrode 250 can completely cover the first type semiconductor layer 214 , and the anti-moisture effect can be improved. Finally, the support substrate 200 and the stacked layers thereon are cut along the wafer separation area, and divided into individual wafers to form the light-emitting element 2 as shown in FIG. 2K .

FIG. 3 shows a cross-sectional view of a light-emitting element 3 according to an embodiment of the present application. In the embodiment of FIG. 3 , the structure, material and process steps of the light emitting element 3 are substantially the same as those of the light emitting element 1 shown in FIG. 1 and the light emitting element 2 shown in FIG. The difference is that the insulating layer 340 of the light-emitting element 3 is formed on the first electrode 350 and covers the upper surface of the first electrode 350 and side surface.

However, the above-mentioned embodiments are merely illustrative to illustrate the principles and effects of the present application, and are not intended to limit the present application. Anyone with ordinary knowledge in the technical field to which this application pertains can make modifications and changes to the above embodiments without departing from the technical principles and spirit of this application. All equivalent changes and modifications made in accordance with the shape, structure, feature and spirit described in the scope of the patent application of the present application shall be included in the scope of the patent application of the present application.

1, 2, 3: Light-emitting element 100, 200, 300: support substrate 201: Growth substrate 211: Buffer layer 112, 212, 312: undoped semiconductor layer 114, 214, 314: first type semiconductor layer 116, 216, 316: Active layer 118, 218, 318: second type semiconductor layer 120, 220, 320: Patterned dielectric layers 130, 230, 330: Reflective metal layer 132, 232, 332: Barrier layer 134, 234, 334: connection layer 140, 240, 340: insulating layer 150, 250, 350: the first electrode C: Sag G: Depressed area P1: first rough structure P2: Second rough structure R1: The first area R2: The second area S: upper surface S1: first surface S2: Concave and convex surface

﹝ FIG. 1 ﹞ shows a schematic cross-sectional view of a light-emitting device 1 according to an embodiment of the present application. ﹝ FIG. 2A to FIG. 2K ﹞ are schematic cross-sectional views at various stages in the manufacturing method of the light-emitting device 2 according to an embodiment of the present application. ﹝ FIG. 3 ﹞ shows a schematic cross-sectional view of a light-emitting element 3 according to an embodiment of the present application.

1: Light-emitting element

100: Support substrate

110: Semiconductor stack

112: undoped semiconductor layer

114: first type semiconductor layer

116: Active layer

118: second type semiconductor layer

120: Patterned Dielectric Layer

130: Reflective metal layer

132: Barrier Layer

134: Connection layer

140: Insulation layer

150: first electrode

C: Sag

G: Depressed area

P1: first rough structure

P2: Second rough structure

R1: The first area

R2: The second area

S: upper surface

S1: first surface

S2: Concave and convex surface

Claims (10)

A light-emitting element, comprising: a support substrate; A semiconductor stack is disposed on the support substrate, including a first-type semiconductor layer, a second-type semiconductor layer, an active layer between the first-type semiconductor layer and the second-type semiconductor layer, and an undoped semiconductor layer. a semiconductor layer disposed on the first type semiconductor layer; and a first electrode is disposed on the undoped semiconductor layer and the first type semiconductor layer; The first-type semiconductor layer includes a first region and a second region, the undoped semiconductor layer is disposed on the first region, the second region is not covered by the undoped semiconductor layer, and the undoped semiconductor layer is not covered by the undoped semiconductor layer. The hetero semiconductor layer has a first roughness structure, and the first type semiconductor layer has a second roughness structure in the second region, and the first electrode contacts the second roughness structure. The light-emitting device as claimed in claim 1, wherein the first rough structure includes a plurality of corners. The light-emitting element according to claim 1, wherein the second rough structure includes a plurality of domes. The light-emitting device as described in claim 1, further comprising an insulating layer disposed between the undoped semiconductor layer and the first electrode, and the first electrode covers a part of the insulating layer. The light-emitting device as described in claim 1, further comprising an insulating layer disposed on the undoped semiconductor layer and the first electrode, and the insulating layer covers a part of the first electrode. The light-emitting element according to claim 4 or 5, wherein the insulating layer covers one side surface of the semiconductor stack. The light-emitting element according to claim 4 or 5, wherein the insulating layer has a concave-convex surface conforming to the first roughness. The light-emitting element according to claim 1, wherein the first electrode has a recess corresponding to the second region. The light-emitting device as described in item 1 of the claimed scope further comprises a reflective metal layer disposed between the second-type semiconductor layer and the supporting substrate, and a barrier layer disposed between the reflective metal layer and the supporting substrate wherein the barrier layer covers an edge of the reflective metal layer. A method for manufacturing a light-emitting element, comprising: providing a growth substrate; forming a buffer layer, an undoped semiconductor layer, a first-type semiconductor layer, an active layer and a second-type semiconductor layer on the growth substrate in sequence; forming a reflective metal layer and a barrier layer on the second type semiconductor layer in sequence; providing a support substrate; forming a connection layer to connect the barrier layer and the support substrate; removing the growth substrate and the buffer layer; patterning the undoped semiconductor layer to form a first roughness; forming an insulating layer on the undoped semiconductor layer; patterning the insulating layer and the undoped semiconductor layer to form a recessed region to expose an upper surface of the first type semiconductor layer; and A first electrode is formed to fill the recessed area to contact the upper surface.

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