TW202236594A - Interposer structure and method for manufacturing thereof - Google Patents

Abstract

An interposer structure is provided. The interposer structure includes a plurality of interposer units in an array arrangement from a top view perspective. Each of the interposer units includes a first region and a plurality of second regions. The first region has a capacitor structure. Each of the plurality of second regions is free of the capacitor structure. The first region surrounds the plurality of second regions. A method for manufacturing an interposer structure is also provided.

Description

Interposer structure and manufacturing method thereof

The present disclosure relates to an interposer structure and a manufacturing method thereof, in particular, the disclosed interposer structure has a plurality of three-dimensional (3D) capacitors located in a middle-end-of-line (MOL/MEOL) structure.

2.5D assembly is a packaging technique used to contain multiple integrated circuit (IC) dies in a single package. This approach is typically used in applications with high demands on performance and low power consumption. In the technical category of 2.5D assembly, the communication between IC dies is realized through a silicon interposer or an organic interposer. Currently, 2.5D packaging technology using silicon interposers is being widely developed based on the use of high-performance applications and the continued increase in demand for miniaturization and higher component density.

An embodiment of the disclosure relates to an interposer structure. The interposer structure includes a substrate part, a line part, an interconnection part, a through hole and a capacitor structure. The circuit part is arranged on the substrate part. The interconnection part is arranged on the line part. The through hole penetrates the substrate part and the circuit part. The capacitive structure is embedded in the circuit part. The interconnection part includes a first metal line electrically coupled to the capacitor structure.

Another embodiment of the present disclosure relates to an interposer structure. The interposer structure includes a plurality of interposer units arranged in an array from a top view. Each of the interposer units includes a first area and a plurality of second areas. The first region has a capacitor structure. Each of the second regions does not have the capacitor structure. The first area surrounds the second areas.

Yet another embodiment of the present disclosure relates to a method of manufacturing an interposer structure. The method comprises the steps of: forming a circuit part on a front side of a substrate part; and forming a capacitance structure in the circuit part during forming the circuit part. And the capacitance structure is formed through a dynamic random access memory process.

This application claims priority to U.S. Patent Application No. 17/085,770, filed October 30, 2020, the entire disclosure of which is incorporated herein by reference in its entirety. This application also claims priority to U.S. Provisional Patent Application No. 63/209,923, filed June 11, 2021, the entire disclosure of which is incorporated by reference in its entirety into this disclosure.

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the following description, the first member is formed on the second member or the first member is formed on the second member, may include an embodiment in which the first member and the second member are in direct contact, and may also Embodiments comprising an additional member formed between the first member and the second member such that the first member and the second member may not be in direct contact. In addition, the present disclosure may repeat element symbols and/or letters in various examples. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and/or configurations discussed.

In addition, for ease of description, spatially relative terms such as "under", "under", "below", "above", "on" and the like may be used in the present disclosure to describe an element or The relationship of a component to another element(s) or component, as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used in this disclosure interpreted accordingly.

If terms such as "first", "second" and "third" are used in this disclosure to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or regions Sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Terms such as "first," "second," and "third" when used in the present disclosure do not imply a sequence or order unless clearly indicated by the context.

FIG. 1 shows an interposer structure, which includes a plurality of 3D capacitors embedded in a MOL/MOEL structure of the interposer structure. As shown, the interposer structure 10 includes a substrate portion 100 having a front side 100A and a back side 100B opposite to the front side 100A. The interposer structure 10 further includes a circuit portion 102 located on the front side 100A of the substrate portion 100 .

In some embodiments, the substrate portion 100 is a semiconductor wafer for accommodating semiconductor device components. In some embodiments, the substrate portion 100 is an insulating substrate to minimize parasitic resistance and inductance. In some embodiments, the substrate portion 100 is made of silicon or glass. In some embodiments, the substrate portion 100 includes active or passive device components. For example, the device components may include memory structures or power regulators.

The existing capacitor structure can be formed on the substrate portion of the interposer structure, wherein a plurality of trenches can be formed on the substrate portion 100 . Each trench (or so-called deep trench) may have a depth between about 10 microns and about 30 microns, or between about 20 microns and about 30 microns. However, the depth of the groove weakens the mechanical strength of the substrate portion of the interposer structure to a certain extent. On the other hand, in the case where the substrate is partially made of an insulating material, compared to the case where the material is a semiconductor, the economical efficiency of forming a deep trench is lower and thus not attractive.

Therefore, in one aspect of the present disclosure, the purpose is to change the structure of the layers above the substrate portion 100 of the interposer structure 10 to solve the problems caused by the existing deep trench capacitor structure, and to effectively utilize the interposer structure 10 Space. Still referring to FIG. 1 , the wiring portion 102 is located on the front side 100A of the substrate portion 100 . Line portion 102 is a structure formed “before” forming a first metal layer (M1) in a semiconductor structure; that is, line portion 102 is referred to as a mid-end-of-line (MOL/MEOL) structure, which is earlier than back-end-of-line (back-end-of-line (BEOL)) structure formed. In some embodiments, the line portion 102 is made of a dielectric material, which may be called a pre-metal dielectric (PMD). In other words, the line portion 102 can be distinguished from the underlying substrate portion 100 and the BEOL structure above it through various process parameters such as selection of basic materials and metal selection. For example, the material of the circuit part 102 can be a low-k dielectric material, that is, its dielectric constant is smaller than that of silicon dioxide; similarly, the metal used for electrical connection in the circuit part 102 is usually tungsten , and the metal usually used in the BEOL structure is copper. These are a few exemplary methods of distinguishing stacked layers in the interposer structure 10, but embodiments of the present disclosure are not limited to these exemplary methods.

In some embodiments, a plurality of capacitive structures 106 are embedded in the circuit portion 102 . In some embodiments, the capacitor structure 106 can be a 3D metal-insulator-metal (MIM) capacitor, and this non-planar structure can be used to increase the effective MIM area and corresponding capacitor density. In some embodiments, the capacitive structures of the present disclosure can have a very high density, for example, greater than about 1 microfarad/square millimeter (μF/mm ² ). In some embodiments, the 3D capacitor can be a cylindrical capacitor.

As shown in FIG. 2 , in some embodiments, each capacitor structure includes a metal bottom plate 108 , a metal top plate 110 on the metal bottom plate 108 , and a plurality of capacitor units 112 formed between the metal bottom plate 108 and the metal top plate 110 . In some embodiments, a distance D1 between the metal bottom plate 108 and the metal top plate 110 is between about 1 micron and about 2 microns, which is larger than the aforementioned active or passive device components formed in the deep trenches of the substrate portion 100. Examples are much thinner.

The configuration of the capacitor unit 112 may have a crown-type capacitor structure or a concave-type capacitor structure. As shown in FIG. 2 , in the embodiment where each capacitor unit 112 is crown-shaped, the capacitor unit 112 includes a first conductive film 114 and a second conductive film 116 stacked between the metal bottom plate 108 and the metal top plate 110 . In some embodiments, the first conductive film 114 includes a first portion 114A connected to the metal bottom plate 108 , and a second portion 114B connected to the first portion 114A and extending from the metal bottom plate 108 to the metal top plate 110 . In some embodiments, the second conductive film 116 is disposed adjacent to the first conductive film 114 and connected to the metal top plate 110 , and extends from the metal top plate 110 to the metal bottom plate 108 . In some embodiments, the second conductive film 116 is vertically interleaved with the second portion 114B of the first conductive film 114 . For example, as shown in the cross-sectional view, the second conductive film 116 is disposed adjacent to the inner side and the outer side of an accommodating space 104 . The accommodating space 104 is surrounded by the first conductive film 114 .

In addition, the capacitor unit 112 further includes a first insulating film 128 for isolating the first conductive film 114 and the second conductive film 116 . In other words, the MIM feature of the capacitor structure 106 is realized by stacking the first conductive film 114 , the first insulating film 128 and the second conductive film 116 . As shown in FIG. 2 , in some embodiments, a second insulating film 130 is optionally used to fill the space between the second conductive film 116 and the metal top plate 110 . In some embodiments, the first insulating film 128 and the second insulating film 130 are made of high-k dielectric material. For example, the high-k dielectric material may include at least one of oxides of metals such as lanthanum (La), hafnium (Hf), and zirconium (Zr).

As shown in FIG. 3 , in other embodiments, the capacitor unit 112 is formed in a concave shape, and the capacitor unit 112 also includes a first conductive film 114 and a second conductive film 116 stacked between the metal bottom plate 108 and the metal top plate 110 . In these embodiments, the second conductive film 116 is formed adjacent to the first conductive film 114 and connected to the top metal plate 110 , and extends from the top metal plate 110 to the bottom metal plate 108 . Compared with the crown shape shown in FIG. 2, the second conductive film 116 of the embodiment shown in FIG. It is completely adjacent to the inner side and the outer side of the accommodating space 104 surrounded by the first conductive film 114 .

4A and 4B are top views of a plurality of capacitor units 112 (concave type) according to some embodiments of the present disclosure. As shown in FIG. 4A, in some embodiments, a plurality of capacitive units 112 can be arranged between the metal plates of the capacitor (ie, the metal bottom plate 108 and the metal top plate 110 shown in FIGS. 2 and 3) as viewed from above. The angles are presented as a rectangular array. Alternatively, in other embodiments, as shown in FIG. 4B , the capacitor units 112 may be arranged between the metal plates of the capacitor in a hexagonal array viewed from above. In general, a hexagonal array arrangement can provide a higher density cluster of capacitor units 112 . The arrangement of the capacitor units 112 of the present disclosure is not limited to the embodiments shown in FIGS. 4A and 4B , because the capacitor units 112 can be arranged in any symmetrical shape as required.

As in the embodiments shown in FIGS. 1 to 3, the capacitive structure 106 embedded in the circuit portion 102 is on the metal bottom plate 108 and the metal top plate 110, and does not have metal contacts that directly contact the metal bottom plate 108 and the metal top plate 110 ( metal contact). In the case of providing the interposer structure 10 to the downstream manufacturer for further processing, for example, forming an interconnection part on the line part 102 (this will be discussed later), then at this time, the metal contact must be perfectly placed on the metal On the surface of the bottom plate 108 and the metal top plate 110, there are actually certain difficulties.

In detail, referring to the embodiment shown in FIG. 5 , the interposer structure 10 may further include a first metal contact 118 and a second metal contact 120 . The first metal contact 118 directly lands on the top surface of the metal top plate 110 , and the second metal contact 120 directly lands on an uncovered area 122 of the metal bottom plate 108 not covered by the metal top plate 110 . In this embodiment, the vertical lengths of the first metal contact 118 and the second metal contact 120 are different.

The distance difference between the metal bottom plate 108 and the metal top plate 110 and the top surface of the line part 102 (ie, the difference between the distances D2 and D3 ) may cause relatively complicated landing of the first and second metal contacts 118 and 120 . In particular, the previously mentioned downstream manufacturer must accurately locate the non-covered area 122 where the metal bottom plate 108 is not covered by the metal top plate 110, and the area of this non-covered area 122 is much smaller than the area of the top surface of the top metal plate 110, As a result, the positioning operation may fail and the metal contacts may shift undesirably.

Therefore, in other embodiments, the interposer structure 10 provided in the present disclosure may further include a plurality of capacitive electrode structures 124 located on the metal bottom plate 108 and the metal top plate 110 . As shown in FIG. 6 , the interposer structure 10 may include a first capacitor electrode structure 124A contacting the non-covered area 122 of the metal bottom plate 108 , and a second capacitor electrode structure 124B contacting the top surface of the metal top plate 110 . In these embodiments, the first capacitive electrode structure 124A and the second capacitive electrode structure 124B can provide a coplanar contact surface 126 on the capacitive structure 106 for contacting and landing of metal contacts. That is, in these embodiments, the vertical lengths of the first metal contact 118 and the second metal contact 120 are substantially the same. In some embodiments, each first capacitive electrode structure 124A or each second capacitive electrode structure 124B includes a combination of a capacitive contact and a capacitive spacer. In some embodiments, the height of the first capacitive electrode structure 124A is greater than the height of the second capacitive electrode structure 124B.

On the other hand, the first capacitive electrode structure 124A may have a top area larger than that of the non-covered area 122 of the metal base plate 108, so that the first metal contact 118 may be more easily placed on the non-covered area 122 than the non-covered area 122. The first capacitive electrode structure 124A, and improve the yield of products.

In some implementations, in addition to the capacitor structure 106, the interposer structure 10 may further include a memory structure in the circuit portion 102, because both the capacitor structure 106 and the memory structure can pass through a compatible dynamic random access memory (DRAM) process, which means that the capacitor structure 106 and the memory structure can be formed by using a semiconductor process compatible with the general DRAM manufacturing process, so that high density, thinner thickness and low cost can be achieved. In common DRAM semiconductor process technology, capacitors can be formed without using structures formed under the surface of the silicon substrate (such as deep trench capacitors), and are also very suitable for reducing the vertical size of capacitor devices. In addition, by introducing general-purpose DRAM semiconductor process technology, process R&D costs can also be reduced. The memory structure formed in the line portion 102 can be used as a cache for the die disposed above the interposer structure 10 .

FIG. 7 is a top view of the layout of the interposer structure 10 according to some embodiments of the present disclosure. In the embodiment shown in FIG. 7 , the interposer structure 10 includes a plurality of interposer units 20 , and the interposer units 20 are arranged in an array in a top view. Each interposer unit 20 includes a first area 202 and a plurality of second areas 204 . In some embodiments, the first region 202 may have a mesh feature in a top view because the shapes of the second regions 204 are substantially the same. The second regions 204 are arranged in an array, or distributed in the interposer unit 20 in a periodic manner. In some implementations, the first region 202 surrounds each second region 204 . In some embodiments, the interposer structure 10 is in the form of a semiconductor wafer carrying a plurality of interposer units 20 as shown in FIG. 7 .

The first region 202 of the interposer unit 20 is used to accommodate the capacitor structure 106, and each second region 204 is reserved for forming a through via therein, such as a through silicon via (TSV). TSV). That is, each second region 204 is used for accommodating a through hole penetrating through the interposer structure. Since only a part of the area (i.e., the second area 204) is reserved for forming TSVs, the rest of the interposer unit 20 can be filled with 3D capacitors to effectively utilize the line portion 102 of the interposer unit 20 (i.e., the MOL/MOEL structure). Space. In some embodiments, the capacitive structure 106 can cover more than half of the interposer structure 10 at a top view angle. In some embodiments, an area ratio of the first region 202 to one of the interposer units 20 exceeds 50%. In some embodiments, an area ratio of the first region 202 to one of the interposer units 20 is about 50% to about 80%.

In some embodiments, a pitch P between adjacent second regions 204 is less than about 100 microns. In some embodiments, a length L of a side of one of the interposer units 20 is about 0.5 mm to 1 mm. In addition, as shown in FIG. 7 , adjacent interposer units 20 are separated by cutting lines 206 . Cutting lanes 206 allow any number of interposer units 20 to be divided into different groups by cutting along appropriate cutting lanes 206, for example, 2 by 2 interposer units 20 can be cut for use with a first For one type of semiconductor die or die stack bonding, the 4×4 interposer unit 20 can be used for bonding with a second type of semiconductor die or die stack via dicing. The array arrangement of the interposer units 20 can provide a modular product geometry suitable for various types of interposer applications. The width of the cutting line 206 is sufficient to allow the interposer structure to be cut into a plurality of block units, and each block unit includes one or more interposer units 20 . A plurality of interposer units 20 in a single block unit can be arranged in a row or an array, and the size of the block unit depends on the size and number of IC dies to be bonded on the single block unit. In other words, since the size of the interposer structure is highly related to the purpose of the 2.5D packaging technology, IC packaging companies can flexibly use the disclosed interposer structure 10 to cut the interposer structure 10 to fit their IC packaging The ideal size for your needs.

Referring to FIG. 8A , in the case where the interposer structure is applied to a semiconductor structure processed by packaging technology, the interposer structure 30 may include an interconnection portion 300 on the circuit portion 102 . Accordingly, the capacitor structure 106 is located between the substrate portion 100 and the interconnection portion 300 of the interposer structure 30 in a cross-sectional view. Generally, the interconnection part 300 is used for bonding with one or more semiconductor dies 80 on the interposer structure 30 , and the substrate part 100 is used for bonding with a packaging substrate 90 under the interposer structure 30 . The semiconductor die 80 on the interposer structure 30 has a critical dimension smaller than that of the interposer structure 30 . In some embodiments, the interconnection portion 300 is referred to as a BEOL-on-MOL/MEOL structure, so the interconnection portion 300 includes a first metal layer 302 directly contacting the top surface of the wiring portion 102 . In the interconnection portion 300 , in addition to the first metal layer ( M1 ) 302 , more metal levels, such as M2 , M3 , etc., may be included. These metal levels or metal layers can be electrically coupled through metal vias, and the uppermost metal layer can provide bonding points for connecting with the chip/die to be packaged. In one way, in some embodiments, a plurality of metal lines are formed in the interconnection portion 300, wherein each metal line may be composed of a metal via and one or more metal layers (ie, M1, M2, M3, etc.). The configuration and the arrangement of the metal lines can be used to determine the connection between the semiconductor die 80 and the packaging substrate 90 .

In addition, as shown in FIG. 8A, the interposer structure 30 may include one or more through holes 304, or called through-silicon vias (TSVs), which penetrate the substrate portion 100 and the circuit portion 102 to electrically couple the semiconductor Die 80 and packaging substrate 90 . The TSVs 304 and the capacitor structures 106 are interleaved in the circuit portion 102 . As previously shown and described in FIG. 7 , each second region 204 is reserved to form a TSV therein, so that the capacitor structure 106 embedded in the circuit portion 102 does not interfere with the circuit arrangement in the interposer structure 30 .

Still referring to FIG. 8A , the first metal layer 302 is not only electrically coupled to the TSV 304 , but also electrically coupled to the capacitor structure 106 . In some embodiments, the capacitor structure 106 can be electrically coupled to the first metal via the first metal contact 118 and the second metal contact 120 (marked in FIG. 5 ) on the metal top plate 110 and the metal bottom plate 108 respectively. Layer 302. In the embodiment shown in FIG. 8A , the vertical lengths of the first metal contact 118 and the second metal contact 120 are different, because no capacitive electrode structure is pre-formed in the line portion 102 to serve as the first metal contact 118 and the second metal contact. 120 provides a flat contact surface.

In contrast, referring to other embodiments shown in FIG. 8B , the capacitive electrode structure 124 is formed in the circuit portion 102 to reduce the difficulty of the first metal contact 118 and the second metal contact 120 landing on the capacitive structure 106 . The details of the capacitive electrode structure 124 can be referred to the previous description in FIG. 6 , which is omitted here for the sake of brevity, and will not be repeated here.

As shown in FIGS. 8A and 8B , the interconnection portion 300 can be electrically connected to the semiconductor die 80 on the interposer structure 30 via a first conductive terminal 306 . The first conductive terminal 306 may include a plurality of conductive pillars (such as copper pillars) or other suitable bump connection forms, wherein the first conductive terminal 306 may be surrounded by a suitable protection or passivation material (not shown in the figure). In other embodiments, a hybrid bonding structure may be implemented to electrically connect the interconnect portion 300 and the semiconductor die 80 . On the opposite surface of the interposer structure 30 , a second conductive terminal 308 may be implemented between the package substrate 90 and the substrate portion 100 of the interposer structure 30 . In some embodiments, the second conductive terminals 308 may include C4 bumps, solder balls, or similar structures. In some embodiments, the semiconductor die 80 may include a system on a chip (SOC), a high bandwidth memory (high bandwidth memory, HBM), a logic die, a memory die, or a graphics processing unit (GPU). , central processing unit (CPU) or similar elements. In some embodiments, semiconductor die 80 may be replaced by chiplets. In some embodiments, an interconnection portion (not shown) of the semiconductor die 80 has a line size smaller than that of the interconnection portion 300 of the interposer structure 30 .

As shown in FIG. 9A , in some embodiments, the interconnection portion 300 includes a first metal line 316 . The first metal line 316 includes a portion of the first metal layer 302 , and the first metal line 316 is electrically coupled to the capacitor structure 106 . In some embodiments, the first metal line 316 is disposed on the TSV 304 , and the first metal line 316 is electrically coupled to the TSV 304 and the capacitor structure 106 .

In some embodiments, a first semiconductor die 81 and a second semiconductor die 82 may be bonded on the interposer structure 30 . In some embodiments, the first semiconductor structure 81 is identical to the second semiconductor die 82 . In other embodiments, the first semiconductor structure 81 is different from the second semiconductor die 82 . The first semiconductor die 81 can be electrically coupled to the second semiconductor die 82 via the interconnection portion 300 . As shown in FIG. 9A, in some embodiments, the interconnection portion 300 includes a second metal line 318 located in the interconnection portion 300, and the second metal line 318 is electrically connected to the first semiconductor die 81 and the second semiconductor die 81. Semiconductor die 82 . In some embodiments, part of the second metal line 318 may include a portion of the first metal layer 302 , such as the second metal line 318 b shown in the figure. In other examples, some of the second metal lines 318a may be completely on the first metal lines 302 . In some embodiments, the second metal line 318 is disconnected from the first metal line 316 or the TSV 304 . In other words, the second metal line 318 is used to transmit electrical signals between the first semiconductor die 81 and the second semiconductor die 82 without detours to the TSV 304 or the capacitor structure 106 . As shown in FIG. 9A , the portion of the circuit portion 102 directly below the second metal circuit 318 does not have the capacitor structure 106 . The staggered arrangement of the second metal lines 318 and the capacitor structures 106 can reduce the interference caused by the capacitor structures 106 in the lower layer to the signals in the second metal lines 318 . However, this is not a limitation to the embodiment. When the interference requirement of the capacitor structure 106 in the lower layer on the signal in the second metal line 318 is relatively loose, the capacitor structure 106 in the line part 102 can also be formed on the second metal line 318 directly below the .

As shown in FIG. 9B , in some embodiments, the TSV 304 can penetrate the substrate portion 100 , the wiring portion 102 and the interconnection portion 300 , and the TSV 304 is disconnected from the first metal line 316 and the second metal line 318 . In these embodiments, the TSV 304 is formed after the interconnect portion 300 is formed on the line portion 102 . The top surfaces of the first metal line 316 , the second metal line 318 and the TSV 304 are all aligned with the top surface of the interconnection portion 300 . Additionally, in these embodiments, the first metal layer 302 is not located on the TSV 304 , so the TSV 304 is disconnected from the first metal layer 302 .

FIG. 9A and FIG. 9B are used to illustrate the characteristics of various metal lines specially designed for signal transmission, as well as extended via holes that can be disconnected from other lines for high-speed signal transmission. In some embodiments, as shown in FIG. 9C and FIG. 9D , the capacitive structure 106 with the capacitive electrode structure 124 can be applied to the structures shown in the above-mentioned FIG. 9A and FIG. 9B . For a detailed description of the capacitive structure 106 with the capacitive electrode structure 124 , please refer to the content described in FIG. 6 and FIG. 8B , which is omitted here for the sake of brevity.

When manufacturing the interposer structure 10 shown in FIG. 1 , especially regarding the operation of forming the capacitor structure 106 in the circuit portion 102 , reference may be made to the disclosures in FIGS. 10A to 10I . As shown in Figure 10A, a semiconductor substrate or a glass substrate can be received as the substrate portion 100, and the front side 100A of the substrate portion 100 is covered by a first PMD layer 400, and the metal base plate 108 is formed on the first PMD layer 400 on. The first PMD layer 400 may include a low-k dielectric material.

As shown in FIG. 10B , a plurality of metal substrates may be formed on the top surface of the metal base plate 108 through deposition and patterning operations. These metal bases are identical to the first portion 114A of the first conductive film 114 previously shown in FIG. 6 . The first portion 114A may raise the second portion 114B of the first conductive film 114 formed subsequently to separate the second portion 114B from the metal base plate 108, and thus the bottom of the second portion 114B of the first conductive film 114 may be on the The lateral alignment is with the bottom of the second conductive film 116 formed later.

Referring to FIG. 10C , a first nitride film 402 , a second PMD layer 404 and a second nitride film 406 are successively formed on the metal base plate 108 . The second nitride film 406 is formed to prevent the capacitive structure from falling down in subsequent operations. Then, with reference to Figure 10D, the stacking system of the first nitride film 402, the second PMD layer 404 and the second nitride film 406 is patterned to form an opening 408, and the top surface of the first part 114A is thus exposed . Then, referring to FIG. 10E , a conductive layer 410 is formed on the second nitride film 406 and covers the outline of the opening 408 . The conductive layer 410 is used to form the second portion 114B of the first conductive film 114 .

Referring to FIG. 10F , the conductive layer 410 is patterned to remove a portion of the top of the conductive layer 410 . The pattern in this operation can determine the type of capacitive structure. For example, the embodiment shown in FIG. 10F can be used to form a crown-shaped capacitive structure 106 because there is an opening 414 etched between the vertical portions of the conductive layer 410; however, in other embodiments, based on There is still a small portion of the second PMD layer 404 not removed between the vertical portions of the conductive layer 410 , so that the concave capacitor structure 106 can be formed without the opening 414 . The present disclosure is exemplified using an embodiment in which the capacitive structure 106 is formed into a crown shape. In fact, other operations for forming the concave capacitive structure 106 are substantially the same as for forming the capacitive capacitive structure 106 , which are omitted here for the sake of brevity, and will not be repeated here.

Afterwards, as shown in FIG. 10G , an insulating film 416 is formed on the conductive layer 410 . The insulating film 416 may include a high-k dielectric material, such as oxides of metals such as lanthanum, hafnium, and zirconium. Referring to FIG. 10H , another conductive layer 412 is formed on the insulating film 416 . The conductive layer 412 is substantially the same as the second conductive film 416 , which is adjacent to the first conductive film 114 and connected to the metal top plate 110 , and extends from the metal top plate 110 to the metal bottom plate 108 . Therefore, by successively stacking the conductive layer 410 , the insulating film 416 and the conductive layer 412 , and performing a planarization operation, a MIM capacitor structure can be achieved as shown in FIG. 10I .

In some embodiments, before the operation of covering the capacitive structure 106 with PMD material to embed the capacitive structure 106 in the circuit portion 102, a plurality of capacitive electrode structures 124 can be formed on the capacitive structure 106 for subsequent operations. The formed metal contacts can rest thereon. In other embodiments without the capacitive electrode structure, PMD material can be formed on the capacitive structure 106 to embed the capacitive structure 106 in the circuit portion 102 .

When manufacturing the interposer structure 30 packaged with the semiconductor die 80 (or the first and second semiconductor die 81, 82) and the packaging substrate 90 as shown in FIGS. 8A, 8B, 9A and 9C, the The operation can refer to the embodiment disclosed in FIGS. 11A to 11H . 11A to 11C, the interposer structure 30 is received after the line portion 102 is formed on the front side 100A of the substrate portion 100, and the capacitor structure 106 is formed on the line portion 102 during the formation of the line portion 102. among. A photoresist layer 50 can be disposed on the wiring portion 102 . By performing a TSV etch operation, a trench 502 can be formed. As shown, the trench 502 penetrates the wiring portion 102 and extends toward the substrate portion 100 . The position of the trench 502 bypasses the capacitor structure 106 so that the subsequently formed vias do not overlap the capacitor structure 106 . Trench 502 may then be filled via a via filling operation. In some embodiments, an oxide pad 504 may be formed in the trench 502 prior to filling the trench 502 with a conductive material such as copper. A bottom end of the TSV 304 will not be exposed until the substrate portion 100 is thinned by a polishing or lapping operation from its back side 100B.

After the via filling operation, a chemical mechanical polishing operation may be performed on the top surface of the circuit portion 102 to form a planar surface before forming the interconnection portion 300 on the circuit portion 102 . In addition, since the capacitor structure 106 embedded in the circuit portion 102 must also be electrically connected, it is possible to form the first metal contact 118 and the second metal contact 118 on the capacitor structure 106 by performing at least one via etching operation and a via filling operation. Metal contacts 120 . The aforementioned CMP operation may be performed after the formation of the TSV 304 , the first metal contact 118 and the second metal contact 120 .

Referring to FIG. 11D , the interconnection portion 300 is successively formed on the line portion 102 . The formation of the interconnection portion 300 may include a plurality of interlayer dielectric (ILD) layers, metal layers and metal vias formed through a BEOL process. The first metal layer 302 in the interconnection portion 300 can be electrically coupled to the TSV 304 and the capacitor structure 106 through a BEOL process.

Next, referring to FIG. 11E , a bumping operation may be performed on the top surface of the interconnection portion 300 to form the first conductive terminal 306 . In some embodiments, the first conductive terminal 306 may include a plurality of conductive pillars (such as copper pillars), or other suitable bump connection structures. In some embodiments, the first conductive terminal 306 further includes an under bump metallization (UBM) 310 located under the bump connection structure. By utilizing the first conductive terminal 306 , both the TSV 304 and the capacitive structure 106 are incorporated into a conductive path extending to the front side 30A of the interposer structure 30 . The TSV 304 and the capacitor structure 106 can be electrically connected to the semiconductor die 80 in a subsequent packaging operation.

As shown in FIG. 11F , prior to bonding the semiconductor die 80 to the interposer structure 30 , a TSV reveal operation may be performed such that the substrate portion 100 is thinned from its backside 100B to one end 304 a of the TSV 304 . Subsequently, as shown in FIG. 11G , a reflow operation may be performed on the backside 100B of the substrate portion 100 to form second conductive terminals such as C4 bumps 312 . In this embodiment, the C4 bump 312 is in contact with another UBM 314 disposed on the backside 100B of the substrate portion 100 .

Thereafter, as shown in FIG. 11H , a 2.5D assembly operation may be performed to bond the semiconductor die 80 to the front side 30A of the interposer structure 30 and to bond the package substrate 90 to a backside 30B of the interposer structure 30 ( equivalent to the back side 100B of the substrate portion 100). The package substrate 90 may further include a plurality of solder balls 901 on the backside 90B thereof.

In other embodiments, the interposer structure 10 as shown in FIG. The second capacitive electrode structure 124B, and the manufacturing method of encapsulating the interposer structure 10 with the semiconductor die 80 and the package substrate 90 are roughly the same as the steps shown in FIGS. 11A to 11H described above.

In the embodiment in which the TSV 304 penetrates the substrate portion 100, the wiring portion 102, and the interconnection portion 300 (i.e., the embodiment previously disclosed in FIG. 9B and FIG. 9D), the via etching operation and via filling for forming the TSV 304 The operation may be performed after the interconnection part 300 is formed.

As shown in FIGS. 12A to 12D , in the case where the capacitive structure 106 has a first capacitive electrode structure 124A and a second capacitive electrode structure 124B located thereon, the via etching operation and via filling operation can still be performed to provide the capacitive structure The first metal contact 118 and the second metal contact 120 are formed on the 106; and these operations are relatively easy, because the first capacitive electrode structure 124A and the second capacitive electrode structure 124B can provide a coplanar contact surface 126 on the capacitive structure 106, It is used to make the metal contact accessible, and the first capacitive electrode structure 124A can provide a larger top area to make the placement of the first metal contact 118 easier, thereby improving the yield rate of the product. In the method for manufacturing the interposer structure, other steps related to packaging the interposer structure, the semiconductor die 80 and the package substrate 90 are the same as those in the previous embodiments shown in FIGS. 11A to 11H . Omit, no more details.

In short, the present disclosure provides an interposer structure with 3D capacitance in a MOL/MOEL structure. By effectively utilizing the space of the interposer structure, a large amount of capacitance can be added to the 2.5D package structure. In addition, the MOL/MOEL structure in the interposer structure is very close to the packaged semiconductor die, such as an SOC, compared to adding capacitors to other spaces in the 2.5D package structure, so these capacitors can more effectively reduce the parasitic resistance. and inductance is minimized.

In an exemplary aspect, the present disclosure provides an interposer structure. The interposer structure includes a substrate part, a line part, an interconnection part, a through hole and a capacitor structure. The circuit part is arranged on the substrate part. The interconnection part is arranged on the line part. The through hole penetrates the substrate part and the circuit part. The capacitive structure is embedded in the circuit part. The interconnection part includes a first metal line electrically coupled to the capacitor structure.

In another exemplary aspect, the present disclosure provides an interposer structure. The interposer structure includes a plurality of interposer units arranged in an array from a top view. Each of the interposer units includes a first area and a plurality of second areas. The first region has a capacitor structure. Each of the second regions does not have the capacitor structure. The first area surrounds the second areas.

In yet another exemplary aspect, the present disclosure provides a method of fabricating an interposer structure. The method comprises the steps of: forming a circuit part on a front side of a substrate part; and forming a capacitance structure in the circuit part during forming the circuit part. And the capacitance structure is formed through a dynamic random access memory process.

The above content outlines the structures of several embodiments, so that those skilled in the art can better understand the aspect of the present disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to carry out the same purposes and/or achieve the same advantages of the embodiments described in this disclosure. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and changes in the present disclosure without departing from the spirit and scope of the present disclosure. .

10: Interposer structure 20:Intermediate board unit 30:Intermediate board structure 30A: front side 30B: dorsal side 50: photoresist layer 80: Semiconductor grain 81: Second semiconductor grain 82: The first semiconductor die 90: Package substrate 90B: dorsal side 100: Substrate part 100A: front side 100B: dorsal side 102: Line part 104:Accommodating space 106:Capacitance structure 108: metal bottom plate 110: metal top plate 112: capacitor unit 114: the first conductive film 114A: Part I 114B: Part Two 116: second conductive film 118: First metal contact 120: second metal contact 122: Non-coverage area 124:Capacitive electrode structure 124A: The first capacitive electrode structure 124B: The second capacitive electrode structure 126: Coplanar contact surface 128: first insulating film 130: second insulating film 202: The first area 204: Second area 206: Cutting Road 300: interconnection part 302: the first metal layer 304: Through hole / TSV 306: the first conductive terminal 308: second conductive terminal 310:UBM 312: C4 bump 314:UBM 316: The first metal line 318: Second metal circuit 318a: Second metal line 318b: Second metal line 400: The first PMD layer 402: first nitride film 404: The second PMD layer 406: second nitride film 408: opening 410: conductive layer 412: conductive layer 414: opening 416: insulating film 502: Groove 504: oxide pad 901: solder ball D1: Spacing D2: Spacing D3: Spacing L: Length P: Pitch

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with the standard practice in the industry, various structures are not drawn to scale. In fact, the dimensions of the various structures may be arbitrarily increased or decreased for clarity of discussion.

FIG. 1 illustrates a cross-sectional view of an interposer structure according to some embodiments of the present disclosure.

FIG. 2 illustrates a cross-sectional view of a capacitor structure according to some embodiments of the present disclosure.

3 illustrates a cross-sectional view of a capacitor structure according to some embodiments of the present disclosure.

FIG. 4A illustrates a top view of capacitor units arranged in a rectangular array according to some embodiments of the present disclosure.

FIG. 4B illustrates a top view of capacitor units arranged in a hexagonal array according to some embodiments of the present disclosure.

5 illustrates a cross-sectional view of a capacitor structure according to some embodiments of the present disclosure.

6 illustrates a cross-sectional view of a capacitor structure according to some embodiments of the present disclosure.

7 illustrates a top view of a layout of an interposer structure according to some embodiments of the present disclosure.

8A illustrates a cross-sectional view of a packaged interposer structure according to some embodiments of the present disclosure.

8B illustrates a cross-sectional view of a packaged interposer structure according to some embodiments of the present disclosure.

9A illustrates a cross-sectional view of a packaged interposer structure according to some embodiments of the present disclosure.

9B illustrates a cross-sectional view of a packaged interposer structure according to some embodiments of the present disclosure.

9C illustrates a cross-sectional view of a packaged interposer structure according to some embodiments of the present disclosure.

9D illustrates a cross-sectional view of a packaged interposer structure according to some embodiments of the present disclosure.

10A-10I illustrate cross-sectional views of capacitor structures formed in an interposer structure according to some embodiments of the present disclosure.

11A-11H illustrate cross-sectional views of packaged interposer structures formed according to some embodiments of the present disclosure.

12A-12D illustrate cross-sectional views of packaged interposer structures formed according to some embodiments of the present disclosure.

10: Interposer structure

100: Substrate part

100A: front side

100B: dorsal side

102: Line part

106:Capacitance structure

D1: Spacing

Claims (24)

A kind of interposer structure, it comprises: a substrate portion; a circuit part, which is located on the substrate part; an interconnection portion located on the line portion; a through hole penetrating the substrate portion and the wiring portion; and a capacitive structure embedded in the line portion; Wherein, the interconnection part includes a first metal line electrically coupled to the capacitor structure. The interposer structure as claimed in claim 1, wherein the first metal line is disposed on the through hole, and the first metal line is electrically coupled to the through hole and the capacitor structure. The interposer structure as claimed in claim 1, wherein the through hole penetrates the substrate part, the circuit part and the interconnection part, and the through hole is disconnected from the first metal circuit. The interposer structure as claimed in claim 1, wherein the interconnection portion is used for bonding with a first semiconductor die, and the substrate portion is used for bonding with a packaging substrate. The interposer structure as claimed in item 4, wherein the interconnection part is further used for bonding with a second semiconductor die, and the interconnection part further comprises a second metal line electrically connected to the first semiconductor die grain and the second semiconductor grain. The interposer structure as claimed in claim 5, wherein the second metal line is disconnected from the first metal line or the through hole. The interposer structure as claimed in claim 1, wherein the substrate part is made of semiconductor or insulator. The interposer structure as described in claim 1, wherein the capacitor structure includes: a metal base; a metal top plate on the metal bottom plate; and A plurality of capacitor units are located between the metal bottom plate and the metal top plate. The interposer structure as described in claim item 8, wherein each of the capacitor units includes: A first conductive film comprising: a first part, which is connected to the metal base; and a second portion connected to the first portion and extending from the metal bottom plate to the metal top plate; and a second conductive film adjacent to the first conductive film and connected to the metal top plate and extending from the metal top plate to the metal bottom plate; Wherein, the second conductive film vertically intersects with the second portion of the first conductive film. The interposer structure as described in claim item 8, which further includes: a first contact connecting a first metal layer of the interconnect and the metal top plate; and a second contact connecting the first metal layer and the metal base; Wherein, the vertical lengths of the first contact and the second contact are substantially the same. The interposer structure as described in claim item 8, which further includes: a first contact connecting a first metal layer of the interconnect and the metal top plate; and a second contact connecting the first metal layer and the metal base; Wherein, the vertical lengths of the first contact and the second contact are different. The interposer structure as claimed in claim 8, wherein a distance between the metal bottom plate and the metal top plate is between about 1 micron and about 2 microns. The interposer structure as described in claim item 1, which further includes: A memory structure is located in the circuit portion. A kind of interposer structure, it comprises: A plurality of intermediate board units are arranged in an array from a top view, and each of these intermediate board units includes: a first region having a capacitive structure; and For a plurality of second regions, each of the second regions does not have the capacitor structure, and the first region surrounds the second regions. The interposer structure as claimed in claim 14, wherein the adjacent interposer units are separated by a cutting line. The interposer structure as claimed in claim 14, wherein an area ratio of the first region to one of the interposer units is about 50% to about 80%. The interposer structure as claimed in claim 14, wherein a pitch between adjacent second regions is less than about 100 microns, and a length of a side of one of the interposer units is between From about 0.5 mm to 1 mm. The interposer structure as claimed in claim 14, wherein each of the interposer units is used for accommodating a through hole penetrating the interposer structure. The interposer structure as claimed in claim 14, wherein a height of the capacitive structure is between about 1 micron and about 2 microns, and the capacitive structure is located on a substrate portion and a portion of the interposer structure from a cross-sectional view between interconnected parts. A method of manufacturing an interposer structure, the method comprising: forming a wiring portion on a front side of a substrate portion; and During forming the line portion, forming a capacitive structure in the line portion; Wherein, the capacitor structure is formed through a dynamic random access memory process. The method as described in claim item 20, which further comprises: forming a via hole penetrating through the circuit portion and extending to the substrate portion, wherein the via hole does not overlap with the capacitor structure; forming an interconnection on the wiring portion, wherein a first metal layer of the interconnection is electrically coupled to the capacitor structure and the via; and The substrate portion is thinned from a back side of the substrate portion to expose an end of the through hole. The method as claimed in claim 20, wherein the step of forming the capacitive structure in the circuit portion comprises: forming a plurality of capacitive electrode structures coupled to the capacitive structures; Wherein the capacitive electrode structures include a coplanar top surface. The method as described in claim item 22, which further comprises: forming a plurality of metal contacts extending from a top surface of the line portion to connect the capacitive electrode structures; and An interconnection part is formed on the line part. The method of claim 20, wherein a height of the capacitive structure is between about 1 micron and about 2 microns.

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