TW202247403A - Electrostatic discharge protection element - Google Patents

Abstract

The present disclosure relates to an electrostatic discharge protection element, including a first source/drain region, a second source/drain region, a base region, a plurality of discharge doped regions and a first well region. The first source/drain region and the second source/drain region have a first type dopant, and are not in contact with each other. The base region and the discharge doped regions have a second type dopant. The discharge doped regions are arranged in the first source/drain regions along a first direction, and have a first interval between each other. The first well region has the first type dopant, and surrounds the discharge doped regions with the first source/drain region, so that the first source/drain region, the discharge doped regions, the first well region, and the base region is configured to form a plurality of silicon controlled rectifiers.

Description

ESD protection components

The present disclosure relates to an electrostatic discharge protection device having a structure of a silicon controlled rectifier to assist discharge.

In the design of semiconductor components, due to the factors of human body discharge or machine discharge, the current caused by electrostatic discharge is easy to cause damage to the inside of the circuit. Therefore, an electrostatic discharge protection circuit needs to be provided in the semiconductor element to achieve the purpose of electrostatic protection.

The disclosure relates to an electrostatic discharge protection element, which includes a first source/drain region, a second source/drain region, a base region, a plurality of discharge doped regions and a first well region. The first source/drain region has a first type dopant. The second source/drain region has a first type dopant. The base region has dopants of the second type. The first source/drain region and the second source/drain region are formed in the base region and are not in contact with each other. The plurality of discharge doped regions have second type dopants. The discharge doped regions are disposed in the first source/drain region along the first direction, and have a first interval between them. The discharge doped regions have a first length along the first direction, and the first interval is greater than or equal to the first length. The first interval is between 1 and 5 times the first length. The first well region has a first type dopant. The first well region and the first source/drain region surround the discharge doped regions, and the first source/drain region, the discharge doped regions, the first well region and the base region are used to form a plurality of silicon controlled rectifier.

The disclosure also relates to an electrostatic discharge protection device, which includes a first source/drain region, a second source/drain region, a base region, a plurality of discharge doped regions, and a first well region. The first source/drain region has a first type dopant. The second source/drain region has a first type dopant. The first source/drain region and the second source/drain region are not in contact with each other. The base region has a second type of dopant. The plurality of discharge doped regions have the second type of dopant and are not in direct contact with the base region. The discharge doped regions are arranged in the first source/drain region and arranged at intervals along a first direction. The discharge doped regions have a first interval between each other and have a first length along a first direction. The first interval is greater than or equal to the first length, and the first interval is between 1 and 5 times the first length. The first well region has a first type dopant. The discharge doped regions are in contact with the base region through the first well region.

Accordingly, through the electrostatic discharge path formed by the first source/drain region, the discharge doped regions, the first well region and the base region, abnormal voltage or current can be discharged to ensure the application of electrostatic discharge protection components The integrated circuit will not be damaged by abnormal voltage or current.

Several embodiments of the present invention will be disclosed in the following figures. For the sake of clarity, many practical details will be described together in the following description. It should be understood, however, that these practical details should not be used to limit the invention. That is, in some embodiments of the present invention, these practical details are unnecessary. In addition, for the sake of simplifying the drawings, some well-known structures and components will be shown in a simple and schematic manner in the drawings.

Herein, when an element is referred to as "connected" or "coupled", it may mean "electrically connected" or "electrically coupled". "Connected" or "coupled" may also be used to indicate that two or more elements cooperate or interact with each other. In addition, although terms such as “first”, “second”, . Unless clearly indicated by the context, the terms do not imply any particular order or sequence, nor are they intended to be limiting of the invention.

FIG. 1 is a schematic diagram of an ESD protection device 100 according to some embodiments of the present disclosure. In some embodiments, the electrostatic discharge protection device 100 can be applied in integrated circuits to eliminate abnormal current or abnormal voltage. For example, when a signal is input to an integrated circuit, if the input signal is abnormal (such as electrostatic voltage or abnormally large current), the input signal will pass through the ESD protection element 100 first, and will not be conducted to the integrated circuit. The operation circuit in the circuit is used to prevent the operation function of the integrated circuit from being damaged. Since those skilled in the art can understand the principle of Electro Static Discharge, it will not be repeated here.

The electrostatic discharge protection device 100 at least includes a first source/drain region 110, a second source/drain region 120, a base region 130, a plurality of discharge doped regions 140 and a first well region 150, and can be integrated into one semiconductor components. In one embodiment, the first source/drain region 110 , the second source/drain region 120 and the first well region 150 respectively have dopants of a first type (eg, N type). The base region 130 and the discharge doped region 140 have dopants of the second type (eg, P type). In some other embodiments, the dopant of the first type and the dopant of the second type may be interchanged. That is, the dopant of the first type can be P-type, and the dopant of the second type can be N-type.

As shown in FIG. 1 , the first source/drain region 110 and the second source/drain region 120 are formed in the base region 130 and are not in contact with each other. The discharge doped regions 140 are formed (embedded) in the first source/drain region 110 . In some embodiments, the discharge doped regions 140 are arranged at intervals along the first direction X, so that each discharge doped region 140 does not contact each other, and the discharge doped regions 140 do not directly contact with each other. base region 130 . In other words, each discharge doped region 140 is separated by the first source/drain region 110 containing the first type dopant.

The base region 130 serves as a substrate of the ESD protection device 100 . In one embodiment, the ESD protection device 100 further includes a heavily doped region 131 , the heavily doped region 131 is electrically connected (contacted) to the base region 130 and has a second type of dopant. The heavily doped region 131 serves as a base contact of the ESD protection device 100 .

The first well region 150 may be an N-well, which is formed in the base region 130 at a position corresponding to the bottom of the first source/drain region 110 . The cross-sectional width of the first well region 150 is greater than the cross-sectional width of the discharge doped region 140 (as shown in Figure 2B), so that the first well region 150 and the first source/drain region 130 can surround and surround these discharge doped regions. impurity region 140 , and the discharge doped region 140 is only exposed on the top surface of the ESD protection device 100 . In one embodiment, in another direction substantially perpendicular to the X direction, the cross-sectional width of the first well region 150 is smaller than the cross-sectional width of the first source/drain region 130, but greater than or equal to the discharge doped region 140. The cross-sectional width (as shown in FIG. 2A ) can isolate the discharge doped region 140 from the base region 130 . In other words, the discharge doped region 140 contacts the base region 130 through the first well region 150 .

In some embodiments, the position of the discharge doped region 140 corresponds to the middle of the first source/drain region 110 , and its doping depth is equal to or smaller than the depth of the first source/drain region 110 . The length of the discharge doped region 140 along the first direction X is smaller than the length of the first source/drain region 110 along the first direction X. The length of the discharge doped region 140 along the first direction X can be adjusted arbitrarily according to the requirements of the protection function.

2A and 2B are schematic cross-sectional views of the ESD protection device 100 along the section lines A-A' and B-B' according to some embodiments of the present disclosure. In some embodiments, the ESD protection device 100 further includes a gate region 170 . The gate region 170 is disposed between the first source/drain region 110 and the second source/drain region 120 . As shown in FIG. 2A, the first source/drain region 110, the second source/drain region 120 and the base region 130 form a typical Metal-Oxide-Semiconductor Field-Effect Transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFETs). When the first source/drain region 110 receives an abnormal voltage, the abnormal voltage will break down the semiconductor channel between the first source/drain region 110 and the second source/drain region 120, but this breakdown path May not provide satisfactory electrostatic discharge protection.

As shown in FIG. 2B , in addition to the breakdown path, the base region 130 , the first well region 150 , the discharge doped region 140 and the first source/drain region will form a "P-N-P-N" semiconductor structure in their order. This semiconductor structure can be equivalent to a silicon controlled rectifier (Silicon Controlled Rectifier, SCR). When the first source/drain region 110 receives an abnormal signal, the "P-N-P-N" silicon controlled rectifier will be turned on to discharge the abnormal voltage or current. As shown in FIG. 1 , in one embodiment, each discharge doped region 140 embedded in the first source/drain region 110 of the ESD protection device 100 can form a silicon controlled rectifier structure. In other words, the discharge doped regions 140 can form a plurality of silicon-controlled rectifiers connected in parallel in the ESD protection device 100 to serve as ESD paths.

FIG. 3 is a schematic diagram of an equivalent protection circuit 200 of the ESD protection device 100 according to some embodiments of the present disclosure. The protection circuit 200 includes at least one semiconductor switch M1 and a plurality of bleeder circuits 210 . The semiconductor switch M1 is the metal oxide half field effect transistor structure (in this embodiment, the N-type MOS).

When the first source/drain region 110 of the ESD protection device 100 receives the input signal Vin, if the input signal Vin exceeds the preset working range (such as: abnormal voltage), the semiconductor switch M1 will be broken down to form The first discharge path P1 (the structure is shown in Fig. 2A).

The discharge circuit 210 is connected in parallel with the semiconductor switch M1 and includes two phase-connected protection switches M21 and M22 , such as bipolar junction transistors (BJT). The two connected protection switches M21 and M22 are silicon-controlled rectifiers corresponding to the base region 130, the first well region 150, the discharge doped region 140 and the first source/drain region "P-N-P-N" shown in Fig. 2B Equivalent circuit of the structure. In detail, the protection switch M21 represented by the PNP transistor is formed by the discharge doped region 140, the first well region 150 and the base region 130, and the protection switch M22 represented by the NPN transistor is formed by the first source/ The drain region 110 , the second well region 160 and the second source/drain region 120 are formed. When the first source/drain region 110 of the ESD protection device 100 receives an abnormal input signal Vin, the silicon-controlled rectifier structure formed by two phase-connected protection switches M2 will be turned on by the input signal Vin to form a second discharge Path P2. The number of the second discharge paths P2 is equal to the number of the discharge doped regions. In some embodiments, after the semiconductor switch M1 is broken down to form the first discharge path P1, the silicon-controlled rectifier structure formed by the two connected protection switches M2 is then turned on to form the second discharge path P2.

Please refer to FIGS. 2A and 2B , in some embodiments, the ESD protection device 100 further includes a second well region 160 . The second well region 160 has the second type dopant and surrounds the second source/drain region 120 . The second well region 160 is in contact with the first source/drain region 110 and the first well region 150 .

In some embodiments, multiple ESD protection components can be integrated on the same substrate. FIG. 2B shows a partial structure of another ESD protection device 300 . The structure of the ESD protection device 300 can be the same as that of the ESD protection device 100 , including the second source/drain region 320 and also using the base region 130 as a substrate.

FIG. 4 is a schematic diagram of another viewing angle of the ESD protection device 100 according to some embodiments of the present disclosure. In one embodiment, the doped discharge regions 140 have a first distance D1 between them, and the doped discharge regions 140 have a first length D2 along the first direction (ie, the vertical direction in FIG. 4 ). The first interval D1 is greater than or equal to the first length D2. In one embodiment, the first interval D1 is equal to the first length D2. That is, the discharge doped regions 140 are arranged at regular intervals, and the first interval D1 is equal to the first length D2 of the exposed discharge doped regions 140 . In other partial embodiments, the first interval D1 is between 1 and 5 times the first length D2.

FIG. 5A is a waveform diagram of a Transmission Line Pulse (TLP) test of the ESD protection device 100 according to some embodiments of the present disclosure. FIG. 5B is a transmission line pulse test waveform diagram of an ESD protection device without the silicon controlled rectifier structure shown in FIG. 3 (that is, without forming the second discharge path P2). The horizontal axis of Figures 5A and 5B is the signal voltage received by the ESD protection device, and the vertical axis is the current on the ESD protection device.

As shown in FIG. 5A , there are two snapback points 51 and 52 (snapback points) in the waveform diagram. The turning point 51 represents that the ESD protection element 100 is broken down, and the first discharge path P1 (as shown in FIG. 3 ) is turned on. The turning point 52 represents that the silicon-controlled rectifier structure formed between the first source/drain region 110 , the discharge doped region 140 , the first well region 150 and the base region 130 is turned on to form the second discharge path P2 .

When the voltage received by the ESD protection device 100 is greater than the voltage corresponding to the turning point 51 but lower than the voltage corresponding to the turning point 52 , the characteristic of the ESD protection device 100 is represented by a trend line L1 . It can be seen from the curve L1 that when the ESD protection component 100 receives noise in the electronic system, the second discharge path P2 will not be accidentally triggered and the ESD protection component 100 will not be burned, which increases the reliability of the ESD protection component 100 . On the other hand, when the voltage received by the ESD protection device 100 is greater than the voltage corresponding to the turning point 52 , its characteristics are represented by a trend line L2 . In some embodiments, the slope of the trend line L2 is greater than the slope of the trend line L1. In other words, after the turnaround point 52 (that is, after an ESD event occurs and the second discharge path P2 is turned on), under the same current variation range, the ESD protection element 100 can quickly discharge the current to change the voltage of the trend line L2 Smaller to avoid damage to the integrated circuit from excessive breakdown voltage.

As shown in FIG. 5B, if the ESD protection component does not have the second discharge path P2 shown in FIG. 3, it also has turning points 53 and 54. The turning points 53 and 54 represent multiple breakdowns of the semiconductor channel between the first source/drain region 110 and the second source/drain region 120 , which can also be represented by trend lines L3 and L4 . In some embodiments, the slopes of the trend lines L3 and L4 are substantially the same.

In addition, in some embodiments, the first source/drain region 110 , the second source/drain region 120 and the discharge doped region 14 are all heavily doped regions. That is, the first type/second type dopant ratio of the first source/drain region 110 , the second source/drain region 120 and the discharge doped region 14 is greater than that of the base region 130 .

Various components, method steps or technical features in the above-mentioned embodiments can be combined with each other, and are not limited by the order of description in words or presentation in drawings in the present disclosure.

Although the content of this disclosure has been disclosed above in terms of implementation, it is not intended to limit the content of this disclosure. Anyone who is skilled in this art can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, this disclosure The scope of protection of the content shall be defined by the scope of the attached patent application.

100: Electrostatic discharge protection components 110: the first source/drain region 120: Second source/drain region 130: base region 131: heavily doped region 140: discharge doped area 150: The first well area 160: The second well area 170: gate area 200: Equivalent protection circuit 210: Bleeding circuit 300: Electrostatic discharge protection components 320: the second source/drain region M1: semiconductor switch M2: protection switch P1: The first discharge path P2: Second discharge path X: first direction A-A': hatching B-B': hatching D1: the first distance D2: first length 51: turning point 52: turning point L1: Trendline L2: Trendline L3: Trendline L4: Trendline

FIG. 1 is a schematic diagram of an ESD protection device according to some embodiments of the present disclosure. 2A and 2B are schematic cross-sectional views of an electrostatic discharge protection device along a section line according to some embodiments of the present disclosure. FIG. 3 is a schematic diagram of an equivalent protection circuit of an ESD protection device according to some embodiments of the present disclosure. FIG. 4 is a schematic diagram of another viewing angle of an ESD protection device according to some embodiments of the present disclosure. FIG. 5A is a waveform diagram of a transmission line pulse test of an ESD protection device according to some embodiments of the present disclosure. FIG. 5B is a waveform diagram of a transmission line pulse test of an ESD protection device without a silicon controlled rectifier structure.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

100: Electrostatic discharge protection components

110: the first source/drain region

120: Second source/drain region

130: base region

131: heavily doped region

140: discharge doped area

150: The first well area

160: The second well area

170: gate area

X: first direction

A-A': hatching

B-B': hatching

Claims (10)

An electrostatic discharge protection element, comprising: a first source/drain region having a first type dopant; a second source/drain region with the first type dopant; a base region having a second type of dopant, wherein the first source/drain region and the second source/drain region are formed in the base region without contacting each other; A plurality of discharge doped regions have the second type of dopant, wherein the discharge doped regions are arranged in the first source/drain region along a first direction, and have a first Intervals, the discharge doped regions have a first length along the first direction, and the first interval is greater than or equal to the first length, and the first interval is between 1 and 5 times the first length; as well as A first well region with the first type dopant, wherein the first well region and the first source/drain region surround the discharge doped regions, and the first source/drain region, the The discharge doped regions, the first well region and the base region are used to form a plurality of silicon controlled rectifiers. The electrostatic discharge protection device according to claim 1, further comprising: a second well region having the second type dopant, wherein the second well region surrounds the second source/drain region and is connected to the The first source/drain region is in contact with the first well region. The electrostatic discharge protection device as claimed in claim 1, wherein a cross-sectional width of the first well region is smaller than a cross-sectional width of the first source/drain region. The electrostatic discharge protection device as claimed in claim 3, wherein the cross-sectional width of the first well region is greater than a cross-sectional width of the discharge doped regions. The electrostatic discharge protection component as described in claim 1, further comprising: A gate region is disposed between the first source/drain region and the second source/drain region. An electrostatic discharge protection component, comprising: a first source/drain region with a first type dopant; a second source/drain region having the first type dopant, wherein the first source/drain region and the second source/drain region are not in contact with each other; a base region with a second type of dopant; A plurality of discharge doped regions have the second type of dopant and are not directly in contact with the base region, wherein the discharge doped regions are arranged in the first source/drain region along the arranged at intervals in a first direction with a first interval between each other, the discharge doped regions have a first length along the first direction, and the first interval is greater than or equal to the first length, the first the interval is between 1 and 5 times the first length; and A first well region has the first type dopant, wherein the discharge doped regions are in contact with the base region through the first well region. The electrostatic discharge protection component as described in claim 6, further comprising: a second well region having the second type dopant, wherein the second well region surrounds the second source/drain region and is in contact with the first source/drain region and the first well region . The electrostatic discharge protection device as claimed in claim 6, wherein a cross-sectional width of the first well region is smaller than a cross-sectional width of the first source/drain region. The electrostatic discharge protection device as claimed in claim 8, wherein the cross-sectional width of the first well region is larger than a cross-sectional width of the discharge doped regions. The electrostatic discharge protection component as described in claim 6, further comprising: A gate region is disposed between the first source/drain region and the second source/drain region.

Images