TW504674B - CD-ROM drive with data reading system of the most probable data detecting circuit - Google Patents

Abstract

A kind of CD-ROM drive with data reading system of the most probable data detecting circuit is proposed in the present invention. The invention includes a signal duplicating apparatus, an A/D converter, a filter, a Viterbi decoder, an adjustment device for adjusting reference level, and a phase lock loop apparatus. By using the CD-ROM drive with data reading system of the most probable data detecting circuit, high-speed partial response equalizer is not required for the system. The Viterbi decoder can be operated at high speed so as to decrease the gathering time of the reference level, and the adding-comparing-selecting circuit can be used to solve the bit overflow problem.

Description

504674 A7 B7 67 50twf. Doc / 006 V. Description of the invention (() The present invention relates to a data reading system in an optical disc drive, and in particular, to data of a data detection circuit in the optical disc drive having the highest probability Readout system. In recent years, technology has continued to advance, such as the optical disc drive has continued to improve the work efficiency and research its technology. As shown in the block diagram of the data readout system of the conventional optical disc drive shown in Figure 1, the read head (p1Ckup) (not shown) Read the data of the optical disc into RF signals and input them to the amplifier 102, and the amplifier 102 outputs the amplified RF signals to the equalizer 104. At this time, the equalizer 104 receives the RF signal Then, the analog signal is output to an analog / digital converter 106 and a binarizing circuit 108. The analog / digital converter 106 converts the analog signal into a digital signal, and outputs the digital signal to a Viterbi decoder 120. Viterbi The decoder 120 decodes the digital signal into bit data and outputs it to a demodulator 122, and the demodulator 122 demodulates the bit data to output the demodulated signal to a subsequent circuit. At the same time, After receiving the analog signal, the binarization circuit 108 outputs binary data to a phase locked loop 124. The phase lock loop 124 refers to the binary data to output a clock signal to the analog / digital converter 106 and the Viterbl decoder 12. The analog / digital converter 106 operates synchronously with the Viterbi decoder 120. In Figure 1, the data readout system of the optical disc drive has the characteristics of the channel model "1 + +". In order to make the equalizer ι04 more design-friendly It's simple. Its channel model is "1 + D". In this way, the characteristics of the Viterbi decoder 120 will be deteriorated, and the data read from the optical disc drive will not be decoded correctly. -The data readout system of optical disc drive. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297). (Please read the precautions on the back before filling this page) -1 ------ Order --------- Line · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 504674 A7 B7 6750twf.doc / 006 V. Description of the invention (z) Figure. In Figure 2, the reading head ( (Not shown) Read the data of the disc into a radio frequency signal Input to the amplifier 202, the amplifier 202 outputs the amplified RF signal to the analog / digital converter 204. The analog / digital converter 106 converts the RF signal to a digital signal, and outputs the digital signal to a partial response. 206. At this time, the partial response equalizer 206 outputs the data to the Viterbi decoder 208. The Viterbi decoder 120 decodes the received data into bit data and outputs it to the demodulator 210. The demodulator 210 demodulates the bit data into a demodulated signal and outputs it to the subsequent circuit. At the same time, the automatic gain controller 212 controls the gain of the amplifier 202 according to the data output from the partial response equalizer 206; the phase-locked loop 214 refers to the data output from the partial response equalizer 206 to output The clock signal is provided to the analog / digital converter 204 for use. In Figure 2, when the partial response equalizer 206 operates at a high speed, the partial response equalizer 206 becomes quite complicated. The partial response equalizer 206 is used to compensate the read head transfer function response and the optical disc transfer function response. However, for optical systems, different optical discs have different optical disc transfer functions. Therefore, it is very difficult to design the partial response equalizer 206 even if the problem of increased noise in the partial response equalizer 206 is not considered. Because the ACS unit is a feedback circuit, the ACS unit is a very important path. Therefore, when designing the ACS unit, it is necessary to ensure that the ACS unit has a sufficient number of memory bits. Avoid errors caused by data being overflowed from memory bits due to overflow. Moreover, the cost function of the ACS unit (cost functi〇n) is the sampling data and parameters. This paper size applies the Chinese National Standard (CNS) A4 specification (21〇x 297). ----------- ---------- I 丨 Order 丨 丨 丨 丨 丨 丨 _ < Please read the precautions on the back before filling out this page) Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 504674 A7 B7 6750twf · doc / 006 V. Description of the invention (3) The rates of the test ranks are then squared. Therefore, when the sampled data exceeds the margin, the Viterbi decoder's error rate will deteriorate. Figure 3 shows a block diagram of an unfamiliar Viterbi decoder. In FIG. 3, the Transition Metric computer 302 in the Viterbi decoder 300 receives reference information (ie, the reference level) and 2's complement sample data output by the equalizer (not shown), and outputs a calculation 値 (ie, branch mtric 値) to the Vitertbi ACS (Add-Compare-Select, ACS) unit 304. The Vitertbi ACS unit 304 receives the calculation to obtain detection data, and outputs the detection data to the Viterbi memory unit 306. The Viterbi memory unit 306 stores the detection data and outputs it to Transition Reference Measurement 308, which receives the detection data and the sampling data at the same time, and outputs a pulse to the Pulse Capture Unit 310, and The reference information is output to the subsequent circuit. The pulse capture unit 310 receives the pulse and outputs the pulse sample to the subsequent circuit. Figure 4 shows a block diagram of a conventional transfer reference measurement. In Figure 4, 5-bit is taken as an example. When the encoded data is input to the 5-bit string register 402, and the input path is selected to the 5-bit path register (5 bits path register) 406, the 5-bit stream register 402 then sends the encoded data to the 5-bit comparator (404), and the 5-bit path register 406 sends the path selection to the 5-bit comparator 404. 5 After the bit comparator 404 compares the encoded data with the path selection, it sends the comparison result to the gate 410 and the 10 bits counter 414, and then the 10 bit counter outputs a count to the microprocessor ( (Not shown). When the sampling data is input to the sampling delay of 408, the paper size will be delayed for a period of time. 5 paper sizes are applicable to Chinese National Standards (CNS) / U specifications (2) 0 X 297 mm. -I ----------- --------- ί I --- I-^ (Please read the notes on the back before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 504674 A7 B7 6750twf · doc / 006 5 2. Description of the invention (after noon) 'Sampling data is sent to the gate 410 and the pulse capture unit (not shown), and the gate 410 sends the sampling signal and the comparison result to the 5-bit stream register 412, respectively, and then the 5-bit The stream register 412 sends the sum to a microprocessor (not shown). The microprocessor (not shown) adjusts the reference information (that is, the reference level) according to the sum and the counting result, so that the Transitoion Metric computer 302 (refer to FIG. 3) performs calculation again based on the adjusted reference information to obtain a new calculation.値 (g 卩 branch mtric 値). When the reference level is sent to the Viterbi decoder for calculation, the required reference level is generated by the microprocessor. In this way, the working time of the microprocessor is occupied, the workload of the microprocessor is increased, and the convergence is achieved. The converge time becomes longer. Therefore, the present invention provides a data readout system with the most probable data detection circuit in the optical disc drive. The system does not require a high-speed partial response equalizer. The Viterbi decoder can operate at high speed and reduce the convergence time of the reference level. At the same time, the ACS circuit needs a larger number of bits due to the overflow problem. The invention provides a data readout system with the most probable data detection circuit in an optical disc drive. The data readout system includes: a signal reproduction device that can reset the data of the read optical disc to an RF signal. An analog digital converter is coupled to the signal reproduction device and can convert a radio frequency signal into a digital signal according to a high frequency clock signal. A filter coupled to the signal reproduction device, which can generate another digital signal by using a radio frequency signal according to a low-frequency clock signal to filter out the DC chirp in the digital signal of the analog digital converter to obtain a filter. Digital signals. A Viterbi decoder, coupled to the filter, 6 papers & degrees apply Chinese National Standard (CNS) A4 ------- I --- i 丨 丨 丨 ---- Order ----- _ _ -Line (Please read the precautions on the back before filling out this page> Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 504674 A7 6750twf. Doc / 006 ^ V. Description of the invention (f) (Please read the notes on the back first Please fill in this page for more information.) The filtered digital signal can be calculated, compared, selected, and decoded according to a reference level to obtain a decoded signal. An adjusted reference level adjuster is coupled to the Viterbi decoder, which can filter the digital signal with The decoded signals are compared to obtain a phase-locked confirmation level and a reference level. And a phase-locked loop device is coupled to the adaptive reference level adjuster to compare the filtered digital signal with the phase-locked confirmation level. The error is used to adjust the output of the high-frequency clock signal and the low-frequency clock signal. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics The present invention is to provide another data readout system with the most probable data detection circuit in the optical disc drive Including: a signal reproduction device, which can reset the read data of the optical disc to a radio frequency signal. An analog digital converter is coupled to the signal reproduction device, and can be based on an inverted high-frequency clock signal. The radio frequency signal is converted into a digital signal. A filter is coupled to the signal reproduction device, and can use the radio frequency signal to generate another digital signal according to a low frequency clock signal, and filter out the direct current in the digital signal of the analog digital converter.値 to obtain a filtered digital signal and generate a square wave signal corresponding to the RF signal at zero. A Viterbi decoder, coupled to the filter, performs the calculation, comparison, selection and decoding of the filtered digital signal according to a reference level, To obtain a decoded signal. An adaptive reference level adjuster is coupled to the VUerbi decoder, and the filtered digital signal is compared with the decoded signal to obtain the reference level. A phase-locked loop device is coupled to the chirper, which can The square wave signal is compared with the high-frequency clock signal output by the phase-locked loop device. The phase error generated is used to adjust the output high-frequency clock signal. Low frequency clock signal. An inverter coupled to the phase-locked loop device can invert the high frequency clock signal into an inverted high frequency clock signal. 7 This paper is sized to the Chinese National Standard (CNS) A4 Specifications (2) 0297 mm) 504674 A7 B7 6750twf. Doc / 0 06 V. Description of the Invention (The present invention) proposes a 'type of optical disc drive with the greatest number of possibilities _ 丨 data reading system for self-test circuit , Its system can have a Viterbi solution 粗 thick ^ adjust the reference level adjuster, this Viterbi decoder according to a reference bit | 5 all a digital signal to do operations, comparison, selection and decoding to get ~ decoded signal, this The adaptive reference level adjuster is coupled to the ViterlM decoder. The _ | ^ standing signal is compared with the decoded signal to obtain the reference level. The adaptive reference level adjuster includes a delay path unit, which is coupled to the VUerbi decoder. Digitally say 5 tigers delay to get ~ 'delayed digital signal. An animal feed and pattern memory are coupled to the VitrerM decoder and can send corresponding data patterns based on the decoded signal. A reference level memory coupled to the data pattern memory, sending all the reference levels stored in the reference level memory to the Viterbi decoder, receiving a new reference level to update the corresponding to the new reference level The reference level sends the reference level corresponding to the data pattern as a selection level signal. A reference comparator is coupled to the delay path unit to compare the delayed digital signal with the selected level signal to obtain a counting control signal. A low-pass filter is coupled to the reference comparator and receives a selection count 値, which can count up / down according to the count control signal. This selection count 値 is used to obtain a new count 値 and a one-level adjustment control signal. When the new count 値 exceeds a certain range, the level adjustment control signal adjusts the selection level, and the new count 値 is reset to 0. A reference count memory, which is coupled to the low-pass filter and the data pattern memory, can store this new count 値, and sends the corresponding selection count 値 according to the data pattern. And, a one-level adjuster is coupled to the low-pass filter, and the control signal can be adjusted according to the level to adjust the selected level signal to obtain a new reference level. 8 ^ Paper size applies to China National Standard (CNS) A4 (210 x 297 mm) " " -----------: ------- order ----- ---- 线 # (Please read the notes on the back before filling out this page) Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by 504674 A7 6750twf.doc / 006 β7 V. Invention Explanation (q) The present invention proposes a data readout system with the most probable data detection circuit in an optical disc drive. The system has a Vlterbl decoder. The Viterbi decoder has a force-comparison-selection unit. This force- The comparison-selection unit includes: several first addition-comparison-selection units 'can calculate a branch metric 値 and a path metric 値 to obtain a calculated path metric 値' and receive a reset signal to reset these first addition-comparisons -State of selection unit 'Receives a normalized signal to set the bit of this path metricpath. A plurality of second addition-comparison-selection units coupled to these first addition-comparison-selection units can calculate branch metric 値, path metric 値, and calculation path metric 値 to obtain a new calculated path metric 计算 and a The comparison signal receives a reset signal to reset the states of these second add-compare-select units, and receives a normalization signal to set a new bit for calculating a path metric 値. A logic gate coupled to the first addition-comparison-selection units and the second addition-comparison-selection units to determine the calculation path metnc 値 of the first addition-comparison-selection units with the second addition-comparison -Select the newly calculated bit of the path metnc 値 to send a logical decision signal. And, a flip-flop is coupled to the logic gate, receives a logic judgment signal, and sends a standardized signal after a delay. Where the first addition-comparison-selection unit and the second addition-comparison-selection unit perform an addition, comparison, and selection operation to generate an overflow, the path metric of the first addition-comparison-selection unit is calculated. When the bit of the newly calculated path metric 値 of these first addition-comparison-selection units is '1', the judgment of the logic gate and the flip-flop send a normalized signal to make these first additions of the overflow condition- Compare-Calculate the path metric of the selection unit 9 This paper size is applicable to China National Standard (CNS) A4 (2.10 x 297 mm) -------------------- Order- -------- Line · (Please read the note on the back? Matters before filling out this page) 504674 A7 B7 6750twf · doc / 006 V. Description of the invention ($) 値 Compare with these second additions-selections The new calculation of the unit of the path metnc 値 keeps the number of bits of the most connected I bought to '1'. The present invention provides a data readout system with the most probable data detection circuit in an optical disc drive. The system may have a Viterbi decoder. The Viterbi decoder includes: a Branch Metric unit, which can convert a digital signal according to a reference level. An operation is performed to obtain a branch metric 値. When the digital signal exceeds a range between a maximum reference level and a minimum reference level, the branch metric 値 is set to 0. One-click-comparison-selection unit, connected to the Branch Metric unit, can accumulate branch metric 値 to a path metnc 値 of several paths in a trellis graph, and compare the smallest path metric accumulated by these paths 値And choose the path with the smallest path metric 値 to become a residual path. And, a path memory unit is connected to the add-compare-selection unit, and can find a combining point according to the residual path, and decode the residual path according to the combining point to obtain a decoded signal. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, preferred embodiments are described below in detail with the accompanying drawings, as follows: Brief description of the drawings: FIG. 1 illustrates the exercises Figure 2 shows a block diagram of the data readout system of the optical disc drive; Figure 2 shows a block diagram of the data readout system of another known optical disc drive; Figure 3 shows a block diagram of the conventional Viterbi decoder; Figure 4 shows the conventional knowledge Transfer reference measurement block diagram; Figure 5 shows the block diagram of the data readout system of the optical disc drive of the present invention; 10 This paper size applies to China National Standard (CNS) / U specification (2) 0X 297 mm) (Please read first Note on the back? Please fill in this page for more information.) -------- Order --------- line 'Printed by the Intellectual Property Bureau of the Ministry of Economy Staff Consumer Cooperatives 504674 A7 B7 6750twf.doc / 006 5 Explanation of the invention (q) Figure 6 shows a block diagram of a Viterbi decoding detection system; Figure 7 shows a trellis diagram of a channel bit; Figure 8 shows a block diagram of an ACS unit; Figure 9A shows an 8 The block diagram of ACS_A in the figure; Figure 9B shows the block diagram of ACS__B in Figure 8; Figure 10 shows another light of the present invention Data readout system of the machine a block diagram; Figure 11 shows figure 10 rpm increases parallel converter block of FIG tandem. Explanation of symbols: 102, 202: Amplifier 104: Equalizer 106, 204, 510, 514, 1010, 1014: Analog / Digital Converter 108: Binarizing Circuit ) 120, 208, 300, 520, 600, 1020, 1106 · Viterbi Decoder (Viterbi Decoder) 122, 210: Demodulator (124, 214, 524, 1016): Phase Locked Loop (Phase Locked Loop) 206 : Partial Response Equalizer 302: Transition Metric Calculator 304: Viterbi ACS Unit (Viterbi ACS Unit) 306 ·· Viterbi Memory Unit (Viterbi Memory Unit) CNS) A4 specification (2) 0 X 297 mm) ------------------- t · —-- 11 (Please read the precautions on the back before filling this page ) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^) 4674 A7 6750twf. Doc / 006 V. Description of the Invention (r0) 308, 400: Transition Reference Measurement (Please read the notes on the back before filling (This page) 310 : Pulse Capture Unit 402, 412: 5 Bits Register (5 Bits String Register) 404: 5 Bits Comparator (406) · 5 Bit Path Register (5 Bits Path Register) 408: Sample Delay 410: Gate 414: 10 Bits Counter 502, 1002: Signal Reproduction Mean 504, 1004: Filter (Filtei *) 512, 1012: Analog Slicer 518, 1018, 1104: Subtractor 516, 610, 1024: Adaptive Reference Level Adjuster 602 · Branch Metric Unit (Branch Metric) Unit)

604, 806: ACS 606: Path Memory Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 612: Delay Path Unit 614: Data_patern Memory 616: Reference Comparator ( Reference Comparator) 618: Reference Level Memory 620: Low-pass Filter 622: Reference Counter Memory This paper standard applies to China National Standard (CNS) A4 specifications ( 210x297 mm) 504674 A7 B7 6750twf.doc / 006 V. Description of the invention (π) 624. Level g cycler (Level Adjuster) (Please read the precautions on the back before filling this page) 802, 908, 910, 912 914, 934, 942, 944, 936: AND Gate 804, 904, 906, 916, 928, 930, 932, 946: D-type Flip Flop

900: ACS_A 902, 920, 922 ·· Adder 924: Comparator 926 · Multiplexer

940: ACS-B 1102: Serial to Parallel Converter. First embodiment. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 5 shows a block diagram of the data reading system of the optical disc drive of the present invention. In Fig. 5, the signal reproduction device 502 resets the data of the read optical disc into a radio frequency signal. The analog-to-digital converter 510 is coupled to the signal reproduction device 502. The analog-to-digital converter 510 converts a radio frequency signal into a digital signal ADC1 according to the high-frequency clock signal CLK1. The filter 504 is coupled to the signal reproduction device 502. The filter 504 uses the radio frequency signal to generate another digital signal according to the low-frequency clock signal CLK2, so as to filter the DC signal in the digital signal ADC1 of the analog digital converter 510. A digital signal Vit_Din is obtained. The filter 504 has an analog divider 512, an analog digital converter 514, and a subtractor 518. The analog divider 512 is coupled to the signal reproduction device 502 and can convert the RF signal into a divided level signal. The paper size applies to the Chinese National Standard (CNS) A4 specification (2) 0X 297 mm.) U4674 A7 B7 6750twf. Doc / 006 i. Description of the invention (丨) Ratio converter 514 is coupled to the analog divider 512. The divided level signal can be converted into a digital signal ADC2 according to the low-frequency clock signal CLK2. The subtractor 518 is coupled to the analog-to-digital converter 514, and can perform a subtraction operation between the digital signal ADC1 and the digital signal ADC2 to eliminate the DC chirp in the digital signal ADC1 to obtain the digital signal V ^ Dm.

The Viterbi decoder 520 is coupled to the filter 504, and can perform calculation, comparison, selection and decoding of the digital signal Vit_Din according to a reference level to obtain a decoded signal Vit_Dout. The adaptive reference level adjuster 516 is coupled to the Viterbi decoder 520, and can compare the digital signal Vit_Din with the decoded signal VkDout to obtain a phase lock confirmation level and a reference level. The phase-locked loop device 524 is coupled to the adaptive reference level adjuster 516, and can compare the digital signal Vit_Din with the phase-locked confirmation level. The generated phase error adjusts the output high-frequency clock signal CLK1 and low-frequency clock signal CLK2. . In Figure 5, because there is no device using an equalizer, there are no disadvantages of the equalizer. For example, the circuit design is complicated, and the system is limited in high-speed operation. 'The system architecture of Figure 5 is simple in design. And can operate at high speed. Brother 6 Η draws the block diagram of Viterbi decoding detection system. In FIG. 6, the Branch Metric unit 602 in the Viterbi decoder 600 receives the digital signal Vit_Din output by the subtractor 518 (refer to FIG. 5), and the Branch Metnc unit 602 adjusts the reference level sent by the reference level adjuster 610 according to The digital signal Vit_Din is calculated to obtain a branch metric 値. When the digital signal Vlt_Din exceeds a maximum reference level or a minimum parameter, the paper size applies the Chinese National Standard (CNS) yVl specification (210 x 297 mm) ---- -------- · 11 ------------ Aw (Please read the precautions on the back before filling this page) The Intellectual Property Bureau of the Ministry of Economic Affairs, the Consumer Cooperatives, Clothing Printing, the Ministry of Economic Affairs, Wisdom Printed by the Property Cooperative Consumer Cooperative 504674 6750twf · doc / 006 _B7__ V. Description of the Invention (0) When the range of the rank is tested, the Branch Metric unit 602 sets the branch metric 値 of the corresponding maximum reference level or minimum reference level to 0 . The ACS unit 604 is connected to the Branch Metric unit 602. The branch metric can be accumulated to the path metric of the female paths in a trellis, and the smallest path metric accumulated by these paths can be compared, and the smallest can be selected. The path of the path metric is to become a survival path. The path memory unit 604 is coupled to the ACS unit 604, and can find a joint point according to the residual path, and decode the residual path according to the joint point to obtain a decoded signal Vit__Dout. The delay path unit 612 in the adaptive reference level adjuster 610 is coupled to the Vitrerbi decoder 600, and sends a digital signal Vit_Din_Delay after a delay. The data pattern memory 614 is connected to the Vitrerbi decoder 600, and can send the data pattern Spot_Pat corresponding to the decoded signal VhJDout according to the decoded signal Vit_Dcmt. The reference level memory 618 is coupled to the data pattern memory 614, and sends all the reference level Reference__Levels stored in the reference level memory 618 to the Branch Metric unit 602 in the Vitrerbi decoder 600. The reference level memory 618 receives the reference level New_Reference_Level ′ sent by the level adjuster 624 to update the reference level stored in the reference level memory 618 and corresponding to the reference level New_Reference__Level. The reference level memory 618 sends the reference level corresponding to the data pattern Spot „Pat as the signal Level-Selected. Among them, some signals of the reference level Reference-Levels are used as the phase lock confirmation level (as shown in Figure 5). Reference comparison The coupler 616 is coupled to the delay path unit 612, and can digitally signal Vit „Din_Delay and 15 $ paper ^ the scale is applicable to the Chinese national standard (CNSM4 specification ⑵〇X 297mm) Sincerity ----------- -· 11 ----- Order --------- Line (Please read the note on the back? Matters before filling out this page) 504674 A7 B7 6750twf.doc / 006 V. Description of the invention (/ Lp signal Level_Selected compares its magnitude to obtain a control signal Counter_Ctl that counts up or down. The low-pass filter 620 is coupled to the reference comparator 616 and can count a count according to the control signal Counter_Ctl that counts up or down. CNT_Sdected to get the new count 値 New_Cnt and the signal Level_Adjust-Ctl. When the new count 値 New_Cnt exceeds a certain range, the signal Level_Adjust_Ctl will adjust the signal Level_Selected and the new count 値 New_Cnt is reset to 0. Reference The number memory 622 is coupled to the low-pass filter 620, which can store a new count 値 New_Cnt, and send the corresponding count 値 CNT_Selected according to the data pattern Spot__Pat. The level adjuster 624 is coupled to the low-pass filter 620 and the data pattern memory The body 614 can adjust the signal Level_Selected according to the signal Levd_Adjiist_Ctl to obtain the reference level New_Reference_Level ° Figure 7 shows a trellis diagram of the channel bits. Here, the "state is A" is used to indicate that the current state The type of channel bits covered by the laser light spot is the center point of the light spot. Taking Figure 7 as an example, L-1Γ11000 "means that the laser light spot is the type of channel bits covered" 1100. ". The trellis diagram in Figure 7 is the Masrkoff state transition. When there are two or more states selecting the next state, only one of them has the highest probability to be transitioned to the next state. This transition The possibility is based on the following path metric estimation function (cost function): Defines the branch metric estimation function: is the estimation of transition to state L + 5. Shen '+ 3 is the transition to state 'Estimation. (Please read the notes on the back before filling out this page) I * inn II nntn B.— —Mm ί ϋ 1! Line i Printed on paper standards applicable to Chinese national standards (CNS) A4 specification (2〗 〇χ 297 mm) 504674 A7 B7 67 50twf. Doc / 006 V. Description of the invention (ec + 2 is an estimate of transition to state ι + 2. 5C + 1 is an estimate of transition to state L + 1. Redundant_5 is an estimate of transition to state L_5. BC_3 is an estimate of transition to state Z_3. This_2 is an estimate of the transition to state L_2. Is an estimate of transition to state L. Define the data that K inputs to the Viterbi decoder and 4 is the reference level of the state 5C + 5 ^ (F; -L + 5) 2 for ^ < ^ 3 = 0 for others. The above formula indicates when 7; When referring to the range of the rank, set the branch metric group: +5 値 to 0. BC + fiYi-LJ2 BC + 2 = (Yi-L + 2) 2 5C + 1 = (7? -4i) 2 BC_5 = (7, -L_5) 2 for 7,. ≫ Z_5 = 0 for others The formula indicates that when 6 値 is smaller than the range of the minimum reference level, branch metric 5 (: _ 5 値 is set to 0. bc_3 = (h) 2 BC_2 = (Yt-L “2) 2

Bc, (n'y- where BCs represents a branch metric. Definition path metnc: is the branch estimate accumulated at time ti (branch This paper scale applies Chinese National Standard (CNS) / V1 specification (2K) X 297 public %) »* I ------------ lull-- (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ^^ 074 ^^ 074 A7 B7 675〇twf · doc / 006 V. Description of the invention (cost) p; +5-^ c + 5 + min {p; 5? P; 3i} ^ 3〇 = ^ C + 3 + min {p; 55p; 3i} If 〇Ρ + 5 < P: 3]) hO = hl = l; else hO = hl: P ;; = BC + ^ p: u p " = bc + 2 ^ p: u P ^ -BC +] ^ nm {P; 30, Pi2} If (house + 3〇 < 〇h2: l; else h2 = 0

P!:! = BC ^ + P -10 P ^ = BC_5 + mm {P! 5, P: 3l} Pi; 10 = BC_3 + mm {P! 57P: 3l} If (P15 < P [3]) h4 = h5 = l; else h4 = h5 = 0 P ^ l-BC_ ^ p: u

P :: 1 = BC_0 + P -11

Pllo = BC_X + min {Pj30, P [2} If (Pls〇 < P: 2) h3 = l; else h3 = 0 10 (Please read the note on the back? Matters before filling out this page) Intellectual Property of the Ministry of Economic Affairs Printed by Bureau Consumers Cooperative

As a memory path, there are two methods, one is called register shuffle, and the other is called trace back. In the embodiment of the present invention, both methods can be used. In this embodiment, the register is used. The mixed method to explain is easier to understand. The memory path is controlled by hO, hi, h2, h3, h4, and h5. As shown in the block diagram of the ACS unit in Figure 8: Define C = max {e} Every path J at every time point i Every path J at every time point i

IX This paper size applies the Chinese National Standard (CNS) A4 specification (2〗 0 X 297 male f) 504674 A7 B7 6750twf. Doc / 006 V. Description of the invention (β) Meaning = Pmax _ Pmm For each time point i, The existence of a boundary 値 is a known theory. Definition + M = 2〃-1, where M ^ 0, N is the number of bits in the register. = > K + ~ 2 ^ nn + ((2N-1)-M) At that time, and 4 = 2 ~ + continents, among which 20 and P2 < 2〃 + Β0 + ((2Λ / -1)- (M), where for each path J, B 0 < £ C Li = nrnx (BCj) for (N + 1) bit ACS (add-compare-select (ACS) 806), when all inputs of AND gate 802 When both ends are 'Γ, it means that the most significant bit of all path metric 値 is' 1 ', then the AND gate 802 will send' Γ (ie high level) to the D-type flip-flop ( D-type flip flop) 804. After a delay, the D-type flip flop 804 sends a normalized signal to all ACS units in the ACS 806, so that the path metric calculated by all ACS units performs normalization. FIG. 9A shows a block diagram of ACS_A in FIG. 8. In Figure 9A, the adder 902 in the ACS-A 900 adds the path metric 値 PmJReg [Nl: 0] and the branch metric 値 BCi [Ml: 0] to obtain the path metric 値 Ρι [Ν-1 ·· 0] . The non-inverting input of the AND gate 908 receives the highest bit Pi [N-1] of the path metric 反相, the inverting input receives the normalized signal Normalize, and judges the situation of the highest bit PUN-1] and the normalized signal Normalize, at the output Output signal AND. The D-type flip-flop 904 receives the signal AND at the input D, and after a delay, the output Q is input to the paper. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------ ---- ^ 丨 丨 · 丨 丨 丨 丨 _ 丨 Order 丨 丨 丨 丨! -. (Please read the note on the back? Matters before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 504674 Α7 Β7 6750twf. Doc / 006 V. Description of the invention (work) The highest bit Pi_Reg of the path metric 値[Nl], receiving a setting signal SET_N-1 at the setting end S to set the path metric 値 highest bit PiJReg [Nl], and receiving a reset signal Viterbi_Reset at the reset end R to reset the highest bit of the path metric 値Pi_Reg [Nl]. The non-inverting input of the AND gate 910 receives the highest bit Pi_Reg [Nl] of the path metric 値, and the inverting input receives the normalized signal Normalize. When judging the highest bit Pijeg [Nl] and the normalized signal Normalize, it is output by the output The first input of the setting signal SET_N-Bu AND gate 912 receives the highest bit Pi_Reg [Nl] of path metric 値, and the second input receives the second highest bit Pi_Reg [N-2] of path metric 値. In the case of the most significant bit p! _Reg [Nl] and the second most significant bit PUleg [N-2], the output terminal outputs a setting signal SET_N-2. The input terminal D of the D-type flip-flop 906 receives path metric 値 the second highest bit Pi [N-2], and after a delay, the output terminal q outputs path metnc 値 the second highest bit Pi_Reg [N-2], Receive the setting signal SET_N-2 at the setting terminal S to set the path metric 値 the second highest bit Pi_Reg [N-2], and receive the reset signal Viterbi_Reset at the reset terminal R to reset the path metric 値 the second highest bit Pi [N-2]. By analogy, the first input terminal of AND gate 914 receives the second low-order bit P ^ Regfl] of path metric ，, the second input terminal receives the lowest bit Pi_Reg [〇] of path metric ，, and determines the second low-order bit pi_Reg [i] In the case of the lowest bit Pi_Reg [0], the setting signal SET_0 is output from the output terminal. The input terminal D of the D-type flip-flop 916 receives the path metric 値 the lowest bit Pi [〇] 'After a delay, the output terminal q outputs the path nietric 値 2 0 This paper size applies to China National Standard (CNS) A4 (2) 0x 297 mm) ----------------- 111 ^ .------ I-^ (Please read the note on the back? Matters before (Fill in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 504674 A7 B7 6750twf. Doc / 006 V. Description of the invention (θ) The lowest bit Pi_Reg [0] 'Receive the setting number SET—0 at the setting end S 'Set path metric 値 lowest bit PlReg [0], and receive a reset signal Viterb Reset at reset end R to reset path metric 値 lowest bit Pi [0]. In Figure 9A, when the ACS_A 900 is performing a normalization action, assuming that the path metric 値 Pni_Reg [N -1: 0] is' 1110 '' and the branch metric 値 BCi [Ml: 0] is' 111 ', at this time The path metric 値 Pm-Reg [Nl: 0] and branch metric 値 BCi [Ml: 0] add up to 010Γ, and an overflow occurs. At this time, the ACS_A 900 will make the path metric 値 Pm_Reg [N-1: 0] still maintain the largest 値 among several Pi_Regs, that is, the path metric 値 Pm_Reg [N-1: 0] is '1111'. In this way, the decoding characteristics of the Viterbi decoder (not shown) are completely unaffected, and because overflow conditions are allowed, and ACS can use fewer bits in the application, so the operation speed of ACS can be faster. . Figure 9B is a block diagram of ACS-B in Figure 8 of the city. In Figure 9B, the adder 920 in ACS-B 940 adds branch metric 値 BCi [M-1: 0] and path metric 値 Pm-Reg [Nl: 0] to get path metnc 値 P_- 1: 0]. The power mouth implement 922 adds the branch metnc 値 BCi [M-1: 0] and the path metric 値 Pn_Reg [N-1: 0] to obtain a path metric Ρ Pi2 [N-1 ·· 0]. The comparator 924 compares the magnitude of the path metric 値 Pm-Reg [N-l: 0] and the path metric 値 Pn-Reg [N-1: 0] to generate a comparison signal Camp. The multiplexer 926 receives path metric 値 Pi i [N-1: 0] and path metric 値 Pi2 [N-hO], and receives a comparison signal Camp to select one of them as the path metric Pi [N-1: 〇]. . The size of the original paper of AND brake 934 applies the Chinese National Standard (CNS) A4 specification (2〗 0 x 297 mm) ------- I ----- ------- ^ «11-- -11 (Please read the precautions on the back before filling this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 504674 A7 B7 6750twf. Doc / 006 V. Description of the invention (eg) Phase path input metric PUN-kO The highest bit Pi [Nl] of the], the inverting input terminal receives the normalized signal Normalize, the AND gate 934 judges the condition of the highest bit Pi [N-1] and the normalized signal Normalize, and the output terminal outputs the signal AND. The D-type flip-flop 930 receives the signal AND at the input terminal D. After a delay, the output terminal Q outputs the highest bit Pi_Reg [Nl] of the path metric 値, and receives the set setting signal SET_ > M at the setting terminal S. The highest bit Pi_Reg [Nl] of path metnc nc is set, and a reset signal Viterbi__Reset is received at the reset terminal R to reset the highest bit Pi_Reg [Nl] of path metric 値. The non-inverting input of AND gate 936 receives the highest bit Pi_Reg [Nl] of path metric 値, and the inverting input receives the normalized signal Normalize. AND 936 determines whether the highest bit Pi_Reg [Nl] and the normalized signal are Normalize. The output terminal outputs a setting signal SET_N-: l. The first input of AND gate 942 receives the highest bit Pi_Reg [Nl] of path metric 値, and the second input receives the second highest bit Pi_Re [N-2] of path metric 値, and determines the highest bit Pi_Reg [Nl] In the case of the second highest bit Pi_Reg [N-2], the output terminal outputs a setting signal SET_N-2. The input terminal D of the D-type flip-flop 932 receives the path metric 値 the second highest bit Pi [N-2], and after a delay, the output terminal Q outputs the path metric 値 the second highest bit P ^ Reg [N-2 ], Receiving the setting signal SET_N-2 at the setting end S to set the path metric 値 the second highest bit Pi_Reg [N-2], and receiving the reset signal Viterbi_Reset at the reset end R to reset the path metric 値 the second highest bit Pi [N-2]. By analogy, the first input terminal of the AND gate 944 receives path metric 22 This paper size is applicable to the Chinese National Standard (CNS) Al specification (2〗 0 X 297 mm) ------- I ---- -------- Order ---------- Line (Please read the precautions on the back before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 504674 A7 B7 6750twf. Doc / 006 5. Description of the invention (> |) The second low-order bit Pi_Reg [l] of 値, the second input terminal receives the lowest bit Pi_Reg [0] of path metric 値, and judges the second low-order bit PiRegn] and the lowest bit Pi_Reg In the case of [0], the setting signal SETJ is output from the output terminal. The input terminal D of the D-type flip-flop 946 receives the path metric 値 the lowest bit Pi [0], and after a delay, the output terminal Q outputs the path metric 値 the lowest bit Pi_Reg [0], and receives the setting at the setting terminal S. Signal SETJ) to set path metric 値 lowest bit Pi jeg [0], and receive a reset signal ViterbLReset at reset terminal R to reset path metric 値 lowest bit PU0]. The D-type flip-flop receives the comparison signal Camp at the input terminal D, and after a delay, outputs the comparison signal hx from the output terminal Q. In Figure 9B, when ACS_B 940 is performing a normalization action, if path metric 値 Pm_Reg [N_l: 0] is added to branch metric 値 BCi [N-1 · 0] or path metric 値 Pn_Reg [Nl: 0] and branch metric 値 BCi [Nl: 0], the overflow occurs. The processing method is the same as that in the case where the overflow occurs in Figure 9A, which is not described here. Second Embodiment FIG. 10 is a block diagram of a data reading system of another optical disc drive according to the present invention. In FIG. 10, the signal reproduction device ^ 02 resets the data of the read optical disc to a radio frequency signal. The analog-to-digital converter 1010 is coupled to the signal reproduction device 1002. The analog-to-digital converter 1010 converts a radio frequency signal into a digital signal ADC1 according to an inverted high-frequency clock signal. The filter 1004 is coupled to the signal reproduction device 1002. The wave filter 1004 uses the radio frequency signal to generate another digital signal based on the low-frequency clock signal CLK2. The paper size is in accordance with the Chinese National Standard (CNS) A4 specification (2 】 〇X 297 mm) ----- 丨 — 丨 丨 丨 丨 -------- Order 丨 丨 丨 丨 丨 丨 ·· Line (Please read the precautions on the back before filling this page) Economy Printed by the Employees ’Cooperative of the Ministry of Intellectual Property Bureau 504674 Printed by the Consumers’ Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 675 twf · doc / 006 ^ V. Description of the invention (ZI) Remove the DC voltage in the digital is 5 Tiger ADC 1, In order to obtain a digital signal Vit__Din, and generate a square wave signal EFM corresponding to the RF signal at zero. Among them, the filter 1004 has an analog divider 1012, an analog digital converter 1014, and a subtractor 1018. The analog divider 1012 is coupled to the signal reproduction device 1002, and can convert the radio frequency signal into a divided level signal and generate a square wave signal EFM corresponding to the radio frequency signal at zero. Analog The digital converter 1014 is coupled to the analog divider 1012, and can convert the divided level signal into a digital signal ADC2 according to the low-frequency clock signal CLK2. The subtractor 1018 is coupled to the analog-to-digital converter 1014, and can perform a subtraction operation between the digital signal ADC1 and the digital signal ADC2 to eliminate the direct current chirp in the digital signal ADC1 to obtain a digital signal VitJDm.

The Viterbi decoder 1020 is coupled to the filter 104, and can perform calculation, comparison, selection and decoding of the digital signal Vit_Din according to a reference level to obtain a decoded signal Vit_Dout. The adaptive reference level adjuster 1024 is connected to the Viterbi decoder 1020, and the digital signal VltJ3in can be compared with the decoded signal Vh-Dout to obtain the reference level. The phase-locked loop 1016 is coupled to the filter 1004, and compares the square wave signal EFM with the high-frequency clock signal CLK1 output by the phase-locked loop device. The phase error generated is used to adjust the output high-frequency clock. The signal CLK1 and the low-frequency clock signal CLK2. The inverter 1026 is coupled to the phase-locked loop 1016, receives the high-frequency clock CLK1 output from the phase-locked loop 1016, and outputs an inverted high-frequency clock signal ^ 1 to the analog-to-digital converter 1010. σ The biggest difference between the system architecture of Figure 10 and the system architecture of Figure 5 is that the signal source of the phase-locked loop receiving reference is different. In # 10_, 24 This paper standard applies to China National Standard (CNS) A4 specifications ⑵G χ 297 public meal) '--------— ---------—— !! ^ --------- (Please read the notes on the back before filling in this Page) 504674 A7 B7 675 0twf. Doc / 006 V. Description of the invention (¥) The reference signal of the phase-locked loop 1016 is the square wave signal EFM sent by the analog divider 1012, and the high-frequency of the phase-locked loop 1016 itself. Clock signal CLK1; In FIG. 5, the reference signal of the phase-locked loop 524 is the digital signal Vit_Din 'output from the subtractor 518 and the phase-locked confirmation level output from the adjustment reference level adjuster 516. The signal reset device 1002 in FIG. 10, the analog-to-digital converter 1010, the Viterbi decoder 1020 and the adaptive reference level adjuster 1024, and the signal reset device 502 in FIG. 5, the analog-to-digital converter 510, The Viterbi decoder 520 is substantially the same as the adaptive reference level adjuster 516. The system functional requirements of Figure 10 are consistent with the system functional requirements of Figure 5. Fig. 11 shows a block diagram of adding a serial-to-parallel converter in Fig. 10. In Fig. 11, a serial-to-parallel converter 1102 is added between the subtractor Π04 and the Viterbi decoder 1106. The purpose is to convert one bit of data output by the subtractor 1104 each time through serial-to-parallel conversion. The decoder 1102 converts two or more bit data to output to the Viterbi decoder 1106, which can increase the number of bit data received by the Viterbi decoder 1106. The function of the system in Figure 11 is the same as that described in Figure 10. Therefore, the advantage of the present invention is to provide a data readout system and method with the most probable data detection circuit in the optical disc drive. The system does not require a high-speed partial response equalizer, and the Viterbi decoder can operate at high speed and reduce reference levels. The convergence time also solves the need for more bits in the ACS circuit due to overflow issues. In summary, although the present invention has been disclosed in the preferred embodiment, the 25 paper sizes are applicable to the Chinese National Standard (CNS) A ·〗 Specifications (2) 0 × 297 mm. -------- I ----------- ^ ------ II (Please read the precautions on the back before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 504674 A7 B7 6750twf.doc / 006 V. Description of the invention (> f) Of course, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper applies Chinese national standards (CNS> A4 size (210x1) 97 mm)

Claims (1)

504674 A8 B8 6750twf.doc / 006 6. Scope of patent application 1. A data readout system with the most probable data detection circuit in an optical disc drive, including: a signal reproduction device, which can read one of the discs read The data is reset to a radio frequency signal; an analog digital converter is coupled to the signal reproduction device, and the radio frequency signal can be converted into a digital signal according to a high frequency clock signal; a filter is coupled to the The signal reproduction device can use the radio frequency signal to generate another digital signal according to a low-frequency clock signal, so as to filter out the DC chirp in the digital signal of the analog-to-digital converter to obtain a filtered digital signal; The VherM decoder is coupled to the filter, and the filtered digital signal can be calculated, compared, selected, and decoded according to a reference level to obtain a decoded signal. An adaptive reference level adjuster is coupled to the ViterM decoder. To compare the filtered digital signal with the decoded signal to obtain a phase-locked confirmation level and the reference level; and the Intellectual Property Bureau of the Ministry of Economic Affairs The industrial and consumer cooperative prints a phase-locked loop device, which is coupled to the adaptive reference level adjuster. The filtered digital signal can be compared with the phase-locked confirmation level. The phase error generated is used to adjust the high frequency output. The clock signal and the low-frequency clock signal. 2. The data readout system with the most probable data detection circuit in the optical disc drive described in item 1 of the patent application scope, wherein the Viterbi decoder further includes: a Branch Metric unit, the pot is connected to the filter, according to The 27 paper sizes are in accordance with Chinese National Standard (CNS) A4 specifications (210 X 297 male f) 504674 6750twf.doc / 006 False 6. Scope of patent application (please read the notes on the back before filling this page) The filtered digital signal is operated to obtain a branch metric 値. When the filtered digital signal exceeds a range between a maximum reference level and a minimum reference level, the branch metric 値 is set to 0; one plus-compare-select unit, coupled Connected to the Branch Metric unit, the branch metnc 値 can be accumulated to a path metric 値 of one of a plurality of paths in a trellis graph, the smallest path metric 値 accumulated by the paths can be compared, and the smallest path can be selected. metric 値 path to become a residual path; and a path memory unit coupled to the add-compare-selection unit, which can be found according to the residual path A combining point, and the residual path is decoded according to the combining point to obtain the decoded signal. 3. The data readout system with the most probable data detection circuit in the optical disc drive according to item 1 of the scope of patent application, wherein the adaptive reference level adjuster further includes: a delay path unit coupled to the filter , The filtered digital signal can be delayed to obtain a delayed digital signal; a data pattern memory is coupled to the VhrerM decoder, and a corresponding data pattern can be sent according to the decoded signal; employees of the Intellectual Property Bureau of the Ministry of Economic Affairs consume The cooperative prints a reference level memory, which is coupled to the data pattern memory, sends all the reference levels stored in the reference level memory to the Viterbi decoder, and receives a new reference level to update corresponding to the new level For the reference level of the reference level, the reference level corresponding to the data pattern is sent as a selection level signal, and a part of the reference levels of all the reference levels are used as the phase lock confirmation level; 2 8 This paper scale is applicable to China Standard (CNS) A4 specification (2) 0 X 297 male f) 504674 B8 675 0twf. Doc / 006 6. Scope of patent application A reference comparator, the pot is connected to the delay path unit, and the delayed digital signal can be compared with the selected level signal to obtain a counting control signal; a low-pass filter is connected to the reference comparator and receives a The selection count 値 can be counted up / down according to the count control signal to obtain a new count 値 and a one-level adjustment control signal; a reference count memory coupled to the low-pass filter and The data pattern memory can store the new count, and send the corresponding selection count according to the data pattern; and a one-level adjuster, coupled to the low-pass filter, can adjust the control signal according to the level to adjust the The level signal is selected to obtain the new reference level. 4. The data readout system with the most probable data detection circuit in the optical disc drive described in item 1 of the scope of patent application, wherein the filter further includes: an analog divider coupled to the signal reproduction device, The RF signal is converted into a split-level signal. A low-frequency analog-to-digital converter is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and is coupled to the analog splitter. The split-level signal can be converted according to the low-frequency clock signal. Is a low-frequency digital signal; and a subtractor, the pot is connected to the low-frequency analog digital converter, and the digital signal and the low-frequency digital signal can be subtracted to obtain the filtered digital signal. 5.-The data of the most probable data detection circuit in the optical disc drive 2 9 This paper size applies to China National Standard (CNS) A4 specifications (2) 0 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 504674 A8 B8 6750twf.doc / 006 £ | 6. The patent-reading range readout system includes: a signal reproduction device that resets the data of an optical disc read to an RF signal; an analog-to-digital converter , Coupled to the signal reproduction device, which can convert the radio frequency signal into a digital signal according to an inverting high frequency clock signal; a filter, which is coupled to the signal reproduction device, can perform a low frequency clock signal Using the radio frequency signal to generate another digital signal, filtering out the DC chirp in the digital signal of the analog digital converter to obtain a filtered digital signal, and generating a square wave signal corresponding to one of the radio frequency signals at zero; A ViterM decoder, coupled to the filter, performing calculation, comparison, selection and decoding of the filtered digital signal according to a reference level to obtain a decoded signal; Adapt a reference level adjuster, coupled to the Vherbi decoder, and compare the filtered digital signal with the decoded signal to obtain the reference level; a phase-locked loop device, coupled to the filter, can convert the square wave The signal is compared with the high-frequency clock signal output by the phase-locked loop device, and the phase error generated is used to adjust the output of the high-frequency clock signal and the low-frequency clock signal; and an inverter, coupled Connected to the phase-locked loop device, the high-frequency clock signal can be inverted into the inverted high-frequency clock signal. 6. The data readout system with the most probable data detection circuit in the optical disc drive described in item 5 of the scope of patent application, wherein the Viterbi decoder 3 0 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (2 ] 0 X 297 mm) IIIII 1 I--II ^ w ——— — — — I— · 111111! (Please read the notes on the back before filling out this page) 504674 §1 6750twf.doc / 006, Apply for a patent The range also includes: (Please read the notes on the back before filling out this page) A Branch Metric unit is connected to the filter, and the filtered digital signal can be calculated according to the reference level to obtain a branch metric 値, when When the filtered digital signal exceeds the range between a maximum reference level and a minimum reference level, the branch metric 値 is set to 0; a plus-compare-selection unit is coupled to the Branch Metric unit, and the branch metric 値 can be accumulated. To a path metric 値 of a plurality of paths in a trellis chart, compare the smallest path metric 値 accumulated by the paths, and select the smallest path metric 値 to become a residual Path; and a path memory unit, coupled to the plus - Comparison - selection means may look for a residual Merger according to the route point, decoding the residue path based on the path Merger point to obtain the decoded signal. 7. The data readout system with the most probable data detection circuit in the optical disc drive according to item 5 of the scope of patent application, wherein the adaptive reference level adjuster further includes: a delay path unit coupled to the filter , The filtered digital signal can be delayed to obtain a delayed digital signal; a data pattern memory is coupled to the VhrerH decoder, which can be printed according to the decoded signal and sent to the consumer clothing cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs to send a corresponding response A data pattern; a reference level memory coupled to the data pattern memory, sending all the reference levels stored in the reference level memory to the Viterbi decoder, receiving a new reference level to update corresponding to For the reference level of the new reference level, send the reference level corresponding to the data format. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (2) 0 X 297 male f) 504674 A8 B8 C8 D8 6750twf.doc / 006夂 The scope of patent application is used as a selection level signal; a reference comparator, coupled to the delay path unit, can delay the digits The signal is compared with the selection level signal to obtain a counting control signal. A low-pass filter is coupled to the reference comparator and receives a selection count. The counting control signal can be used to count up / down. Select count 値 to get a new count 値 and one-level adjustment control signal; a reference count memory, coupled to the low-pass filter and the data pattern memory, can store the new count 値 and send it out according to the data pattern Corresponding to the selection count 値; and a level adjuster coupled to the low-pass filter, which can adjust the control signal according to the level to adjust the selection level signal to obtain the new reference level. 8. The data readout system with the most probable data detection circuit in the optical disc drive described in item 5 of the scope of patent application, wherein the filter further includes: an analog divider coupled to the signal reproduction device, The radio frequency signal is converted into a split level signal, and the square wave signal corresponding to the radio frequency signal at zero is generated. A low frequency analog digital converter is coupled to the analog divider. According to the low frequency clock signal, The split-level signal is converted into a low-frequency digital signal; and a subtractor coupled to the low-frequency analog-to-digital converter can perform a subtraction operation between the digital signal and the low-frequency digital signal to obtain the filtered number of 32 paper scales. China National Standard (CNS) A4 Specification (210 X 297mm t) ----------- ^ ----- I-^-!! (Please read the notes on the back before filling (This page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, 504674 A8 B8 6750twf.doc / 006 6. The signal of the scope of patent application. 9. A data readout system with the most probable data detection circuit in an optical disc drive. The system may have a VUerM decoder and an adaptive reference level adjuster. The Vherb! Decoder performs a digital signal based on a reference level. Calculate, compare, select and decode to obtain a decoded signal. The adaptive reference level adjuster is coupled to the VherM decoder. The digital signal is compared with the decoded signal to obtain the reference level. The adjusted reference level is adjusted. The decoder includes: a delay path unit, coupled to the VherM decoder, which can delay the digital signal to obtain a delayed digital signal; a data pattern memory, which is coupled to the Vhrerbi decoder, and can be based on the decoded signal Send a corresponding data pattern; a reference level memory, coupled to the data pattern memory, send all the reference levels stored in the reference level memory to the Viterbi decoder, and receive a new reference level to update The reference level corresponding to the new reference level, the reference level corresponding to the data pattern is sent as a Level-selective signal; a reference comparator coupled to the delay path unit, which can compare the delayed digital signal with the level-selective signal to obtain a count control signal; a low-pass chirper coupled to the reference The comparator receives a selection count 値 and can count up / down the selection count 値 according to the count control signal to obtain a new count 値 and a first-order adjustment control signal; a reference count memory coupled to the Low-pass filter and this information (please read the precautions on the back before filling this page) f) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 504674 6750twf.doc / 006 £ | 6. The patent application scope style memory can store the new count card, and send the corresponding selected count card according to the data model; and a A level adjuster is coupled to the low-pass filter and can adjust the control signal according to the level to adjust the selected level signal to obtain the New reference level. 10. The data readout system with the most probable data detection circuit in the optical disc drive described in item 9 of the scope of the patent application, wherein the Viterbi decoder further includes: a Branch Metnc unit, which can digitize the digits according to the reference level The signal is operated to obtain a branch metnc 値. When the digital signal exceeds the range of a maximum reference level and a minimum reference level, the branch metric 値 is set to 0; a plus-compare-selection unit is connected to the Branch Metric unit, which can accumulate the branch metric 値 to one of a plurality of paths in a trellis, and compare the smallest path metnc 累 accumulated by the paths, and select the smallest path metnc 値The path becomes a residual path; and a path memory unit coupled to the add-compare-selection unit can find a composite point according to the residual path, and decode the residual path according to the composite point to obtain the Decode the signal. 11. A data readout system with the most probable data detection circuit in an optical disc drive. The system has a Viterbi decoder. The Viterbi decoder has a plus-compare-selection unit. The plus-compare-selection unit includes: One first addition-comparison-selection unit can calculate a branch metric 34 This paper size is applicable to China National Standard (CNS) A4 (210 χ 297 male f) ----------- install --- ----- Order ----- III (Please read the notes on the back before filling out this page) Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 504674 pQ 6750twf.doc / 006 gg 6. Scope of patent application A path metric 値 to obtain a calculated path metric 値, receive a reset signal to reset the states of the first add-compare-selection units, and receive a standardized signal to set the bits of the calculated path metric 値; a plurality of The second addition-comparison-selection unit, coupled to the first addition-comparison-selection units, can calculate the branch metric 値, the path metric 値, and the calculation path metric 値 to obtain a new calculated path metric 値 and A comparison signal, then The reset signal resets the states of the second add-compare-selection units, receives the standardized signal to set the bit of the newly calculated path metric 値; a logic gate, which is connected to the first add-compare- The selection unit and the second addition-comparison-selection units can determine the calculation path metric of the first addition-comparison-selection units and the new calculation path of the first addition-comparison-selection units. metric 値 bit to send a logical judgment signal; and a flip-flop, coupled to the logic gate, receives the logical judgment signal, and sends the standardized letter after a delay _; among which the first plus_ When the comparison-selection unit and the second addition-comparison-selection unit perform addition, comparison, and selection operations to generate overflow, the calculation path metnc 値 of the first addition-comparison-selection unit and the first The bit of the newly calculated path metnc 値 of the two-add-compare-selection unit is 1, when the logic gate judgement and the flip-flop send the standardized signal to make the first ones that produce an overflow condition. The calculation p of the add-compare-select unit The highest consecutive number of bits of the new calculated path metric 该 of the ath metric 第二 and the second add-compare-select units are kept as '丨'. The size of this paper is applicable to China National Standard (CNS) A4 specification (2) 0 × 297 mm. ------------ · Installation --------- Order · I (please first (Please read the notes on the back and fill in this page). • Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ U4674 6750twf.doc / 〇〇6 C8. __ D8 ___............ .. ...... /, Shen Jing Patent Scope12. The data readout system with the largest gastric energy data detection circuit in the optical disc drive described in item 11 of the patent application scope, where Each first addition-comparison-selection unit of the one-add_comparison-selection unit further includes: an adder that can add the branch metric 値 and the path metric 値 to obtain a total path metric 値; A sum gate has a non-inverting input terminal, an inverting input terminal and an output terminal. The non-inverting input terminal receives data of the highest bit of the total path metric 値, and the inverting input terminal receives the standardized signal. Judging the situation of the highest bit data and the standardized signal, and outputting a first sum gate signal at the output terminal; a first D-type flip-flop, There is an input terminal, a setting terminal, a reset terminal and the output terminal. The first and gate signals are received at the input terminal, and after a delay, the output terminal outputs the highest bit of the calculated path metric 値. Data, a first setting signal is received at the setting end to set the highest bit data of the calculated path metric 値, and a reset signal is received at the reset end to reset the highest bit of the calculated path metric 値A second sum gate having the non-inverting input terminal, the inverting input terminal and the output terminal, the non-inverting input terminal receiving data of the highest bit of the calculated path metric 値, and the inverting input terminal receiving The standardized signal judges the data of the most local bit and the situation of the standardized signal, and outputs the first setting signal at the output terminal; a plurality of AND gates, each of the AND gates has a first input A second input terminal and the output terminal. The paper size of the first and the brake pads of the brake pads is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this ) Installed 504674 A8 B8 C8 D8 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 6750twf · doc / 006 6. The first input terminal of the scope of patent application receives the highest bit data of the calculated path metric 値, the first and The second input terminal of the gate receives the data of the second highest bit of the calculated path metric, determines the data of the highest bit and the data of the second highest bit, and outputs a second at the first and the output of the gate. Set signals, and so on, the first input of the last gate and the first input of the gate receive the data of the second lowest bit of the calculated path metnc 値, and the second input terminal of the last and gate receive the calculated path The data of the lowest bit of metric ，, to judge the data of the second lowest bit and the data of the lowest bit, and output a least bit setting signal at the output of the last one and the gate; and a plurality of D-type flip-flops, Each of the D-type flip-flops has the input terminal, the setting terminal, the reset terminal, and the output terminal. In the first D-type flip-flops of the D-type flip-flops, Receiver at the input The data of the second most significant bit of the summed path metric ， is output by the output end of the first D-type flip-flop after a certain delay, and the data of the second most significant bit of the calculated path metric 在 is output in the first The setting end of the D-type flip-flops receives the second setting signal to set the data of the second highest bit of the calculated path metric 値, and receives the reset at the reset end of the first D-type flip-flops. Signal to reset the data of the second most significant bit of the calculated path metric 値, and so on, and receive the sum of the path metric 正 at the input end of the last D-type flip-flops The data of the lowest bit, after a delay, the output of the last D-type flip-flop outputs the data of the lowest bit of the calculated path metric 値, and at the setting end of the last D-type flip-flop Receive the lowest bit setting signal to set the lowest bit data of the calculated path metric 値. At the end of the D-type flip-flop, the paper size applies the Chinese National Standard (CNS) A4 specification (2) 〇χ 297 Mm) (Please read the notes on the back before filling (This page) 504674 67 50twf.doc / 006 A8 B8 C8 D8 I. The reset terminal printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs receives the reset signal to reset the lowest position of the calculated path metric 値. data. 13. The data readout system with the most probable data detection circuit in the optical disc drive as described in item 丨 丨 of the patent scope of the application, wherein each of the second additions of the second addition-comparison-selection unit- The comparison_selection unit further includes: a brother addition trace 1 'may add the branch metric 値 and an m-th calculated path metric 加 to obtain a first total path metric 値; a table and an adder' may The branch metric 値 is added to a n-th calculated path metric 値 to obtain a second total path metnc 値; a comparator may compare the m-th calculated path metric 値 with the n-th calculated the size of the path metric 比较 to generate a comparison result signal; a multiplexer 'receives the first total path metric 値 and the second total path metric 値, and receives the comparison result signal to select one of them as a A selection path metric 値; a first sum gate having a non-inverting input, an inverting input and an output, the non-inverting input receiving the highest bit data of the selected path metric 値, the inversion The input receives the standard Signal to judge the situation of the highest bit data and the standardized signal, and output a first sum gate signal at the output terminal; the first D-type flip-flop has an input terminal setting terminal reset terminal and the output terminal. The input terminal receives the first sum brake signal, and after a delay of a period of time, the g-buffer path metric 算 Z 3 8 is output from the output terminal. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (2) 〇X 297 mm) --------- 丨 丨 install ------- 丨 Order · 丨 丨! · ^ 9. (Please read the notes on the back before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 504674 B8 67 50twf. Doc / Ο06 Lu | The setting terminal receives a first setting signal to set the data of the highest bit of the calculated path metric 値, and receives the reset signal at the reset terminal, and resets the data of the highest bit of the calculated path metric 値; The second sum gate has the non-inverting input terminal, the inverting input terminal, and the output terminal. The non-inverting input terminal receives data of the highest bit of the calculated path metric 値, and the inverting input terminal receives the standardized signal. Judge the status of the highest bit data and the standardized signal, and output the first setting signal at the output terminal; a plurality of AND gates, each of the AND gates has a first input and a second input terminal With the output terminal, the first input terminal of the AND gate receives the highest bit data of the calculated path metric 値, and the second input terminal of the first AND gate receives the calculated path metric. The data of the second highest bit, the data of the highest bit and the data of the second highest bit are judged, and a second setting signal is output at the output terminal of the first and gate, and so on. The first input terminal of the last gate receives the data of the second lowest bit of the calculated path metric 値, and the second input terminal of the last gate receives the data of the lowest bit of the calculated path metric 値, and judges its first The data of the two low-order bits and the data of the lowest-order bits output a least-signal signal at the output of the last one and the gate; and a plurality of D-type flip-flops, each of the D-type flip-flops is -_ • The D-type flip-flops all have the input terminal, the setting terminal, the reset terminal and the output terminal, and the selection path metnc is received at the input terminal of the first D-type flip-flops of the D-type flip-flops. The data of the second highest bit of 在 is delayed --- some time 3 9 The paper size of the table is applicable to the Chinese National Standard (CNS) A4 specification (2) 〇χ 297 mm) (Please read the precautions on the back before filling (This page) 504674 B8 6750twf.doc / 006 6. Apply for a patent After that, the output end of the first D-type flip-flop outputs the calculated path metric (please read the precautions on the back before filling this page) 値 The data of the second highest bit is in the first D-type positive and negative The setting terminal of the inverter receives the second setting signal to set the data of the second highest bit of the calculated path metric 値, and receives the reset signal at the reset terminal of the first D-type flip-flop to reset the signal. Set the data of the second highest bit of the calculated path metnc 値, and so on. At the input of the last D-type flip-flop of the D-type flip-flops, receive the data of the lowest bit of the selected path metric 接收. After a delay, the output end of the last D-type flip-flop outputs the data of the lowest bit of the calculated path metric 値, and the setting end of the last D-type flip-flop receives the lowest bit setting Signal to set the lowest bit data of the calculated path metnc 値, and receive the reset signal at the reset end of the last D-type flip-flop to reset the lowest bit data of the calculated path metric 値; And a third D-type flip-flop with the The input terminal and the output terminal receive the comparison result signal at the input terminal, and after a delay, the output terminal outputs the comparison signal. 14. A data readout system with the most probable data detection circuit in an optical disc drive. The system may have a Viterbi decoder. The Viterbi decoder includes: a Branch Metric unit printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. , A digital signal can be calculated according to a reference level to obtain a branch metric 値. When the digital signal exceeds the range of a maximum reference level and a minimum reference level, the branch metric 値 is set to 0; ▲ plus- Comparison and selection unit, the pot is connected to the Branch Metric unit, 4 0 ^ paper size applies Chinese National Standard (CNS) A4 specifications (2) 〇χ 297 mm) ^ ~ 504674 B8 6750twf.doc / 006 £ | The scope of the patent can accumulate the branch metricpath to one of the multiple paths in a trellis graph, compare the smallest path metric 値 accumulated by the paths, and select the path with the smallest path metric 値 to Become a residual path; and a path memory unit coupled to the add-compare · selection unit, which can find a composite point according to the residual path , Decoding the residual path according to the combined point to obtain the decoded signal. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (2) 0 X 297 mm