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TW502440B - Semiconductor fuse device and the manufacturing method thereof - Google Patents

Semiconductor fuse device and the manufacturing method thereof Download PDF

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Publication number
TW502440B
TW502440B TW90122218A TW90122218A TW502440B TW 502440 B TW502440 B TW 502440B TW 90122218 A TW90122218 A TW 90122218A TW 90122218 A TW90122218 A TW 90122218A TW 502440 B TW502440 B TW 502440B
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layer
fuse
electrically connected
conductive layer
patent application
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TW90122218A
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Chinese (zh)
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Ta-Lee Yu
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Taiwan Semiconductor Mfg
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Abstract

A manufacturing method for a semiconductor fuse device includes the following steps: providing a substrate, which comprises a first conductive layer defined with a first and a second wirings, and the first wiring and the second wiring are isolated; forming a first and a second contact plugs on the substrate electrically connected to the first wiring and the second wiring; forming a second conductive layer electrically connected with the first contact plug; and, forming a fuse layer, which is connected with the second conductive layer and electrically connected with the second contact plug.

Description

502440 五、發明說明(1) 本發明係有關於一種半導體熔線(fuse)裝置及其製造 方法’特別有關於一種具有較小電路面積之半導體金屬熔 線(metal fuse)裝置及其製造方法。502440 V. Description of the invention (1) The present invention relates to a semiconductor fuse device and a manufacturing method thereof ', and more particularly to a semiconductor metal fuse device with a small circuit area and a manufacturing method thereof.

在積體電路及其製程中,係將許多個微小之半導體裝 置=置在一片石夕基底上,同時為了讓積體電路能夠依需求 進仃適當之電路運作,亦設有許多的連接裝置選擇性地將 某些電路單元做必要之電性連接,典型的方式係經由熔絲 做為連接之裝置。這些熔絲可經由通以電流或雷射之方式 ^決定是否將其熔斷而決定兩個電路單元間是否連接。以 ,態隨機存取記憶電路為例,熔絲還可以用以在製程中保 屢某些易受知之電晶體堆疊閘極之用,一旦電路製作完成 後,這些熔絲就必需被熔斷。 第1A圖顯示一傳統半導體雷射式金屬熔線(laser metal fuse)之上視圖;第16圖係第u圖沿線aa,之剖面 圖。傳統雷射式金屬熔線裝置包括一石夕基底丨丨、兩條多晶 2構成之導線12、與導線12電性連接之接觸插塞14及金 屬熔線層15。絕緣層13則填充於各層之間。在進行熔斷 ^,係利用雷射將熔線層15燒斷,而決定導線12間之連通 與否。In the integrated circuit and its manufacturing process, many tiny semiconductor devices are placed on a piece of stone substrate. At the same time, in order to enable the integrated circuit to perform appropriate circuit operation as required, there are also many connection device options. The necessary electrical connections are made to certain circuit units in a typical way, and the typical way is to use a fuse as a connection device. These fuses can be connected to each other by deciding whether to fuse them or not by passing current or laser. Taking the state random access memory circuit as an example, fuses can also be used to maintain certain well-known transistor stacked gates in the manufacturing process. Once the circuit is completed, these fuses must be blown. FIG. 1A shows an upper view of a conventional semiconductor laser metal fuse; FIG. 16 is a cross-sectional view along line aa of FIG. U. The conventional laser-type metal fuse device includes a stone substrate, a wire 12 composed of two polycrystals 2, a contact plug 14 electrically connected to the wire 12, and a metal fuse layer 15. The insulating layer 13 is filled between the layers. When fusing, the laser fuse is used to blow the fuse layer 15 to determine whether the wires 12 are connected or not.

此外,亦有另一種電子式之熔線裝置,其結構與上 ::射式?線雷同’但其熔斷之方式係產生一大電流流 觸插塞14及熔線層15。由於熔線裝置之熔斷 義成「H」形’使其兩端之寬度較中間In addition, there is another type of electronic fuse device. Its structure is similar to the above :: shoot type? The wires are the same, but the way of fusing is to generate a large current to contact the plug 14 and the fuse layer 15. Because the fuse of the fuse device is defined as "H" shape, its width at both ends is relatively middle.

502440 五、發明說明(2) 其中間部之電流密度較兩端之電流密度為高,此一高電流 密度所產生之高熱將使熔線層15之中間部最先被熔斷,而 不會在其他部位產生熔斷現象。 然而’上述傳統半導體雷射式金屬熔線裝置需要較大 之面積且其製程十分複雜。電子式之熔線裝置,由於其兩 端之寬度必需加大以在中間部產生較高之電流密度,使得 其用於銅製程時,必需增加額外之光罩,同時熔線裝置所 需之電路面積也因兩端寬度而增大,不利於節省製造成本 及電路面積之縮減。 為了解 積之半導體 代以平面寬 本發明 方法,包括 電層定義一 緣。在該基 及第二接觸 二導電層。 二接觸插塞 本發明 括一第一及 線層。其中 接觸插塞分 該第一接觸 利用垂直深度取 熔線裝置之製造 底具有一第一導 一導線相互絕 電性連接之第— 塞電性連接之第 層連接且與該第 體炫線裝置,包 塞、導電層及炫 。該第一及第二 線。該導電層與 導電層連接且與 決上述問題,本發明提供一種 金屬熔線裝置及其製造方法, 度來造成電流密度差之效果。 之一目的在於提供一種半導體 以下步驟。提供一基底,該基 第一及第二導線,該第一及第 底上形成與該第一及第二導線 插塞。形成一與該第一接觸插 形成一熔線層,與該第二導電 電性連接。 之另一目的在於提供一種半導 第二導線、第一及第二接觸插 ’該第一及第二導線相互絕緣 別電性連接至該第一及第二導 插塞電性連接。該熔線層與該502440 V. Description of the invention (2) The current density of the middle part is higher than the current density of the two ends. The high heat generated by this high current density will cause the middle part of the fuse layer 15 to be fused first, and will not be blown. Fused in other parts. However, the above-mentioned conventional semiconductor laser-type metal fuse device requires a relatively large area and its manufacturing process is very complicated. The electronic fuse device must have a wider width at both ends to produce a higher current density in the middle. When it is used in copper processing, it must add an additional photomask. At the same time, the circuit required by the fuse device The area also increases due to the width of the two ends, which is not conducive to saving manufacturing costs and reducing circuit area. In order to understand that the semiconductor is replaced by a plane width, the method of the present invention includes an electrical layer definition edge. The base and the second contact are two conductive layers. Two-contact plug The present invention includes a first and a wire layer. Wherein the contact plug is divided into the first contact, and the manufacturing device of the vertical fusing device is provided with a first conductive-conducting connection between the first layer and the second layer of the plug-type electrical connection, and the first body dazzling wire device. , Plugging, conductive layer and dazzle. The first and second lines. The conductive layer is connected to the conductive layer and solves the above-mentioned problems. The present invention provides a metal fuse device and a method for manufacturing the same, so as to cause the effect of a difference in current density. One object is to provide a semiconductor with the following steps. A base is provided, the base first and second wires, and plugs are formed on the first and second bases with the first and second wires. Forming a plug with the first contact, forming a fuse layer, and electrically connecting the second conductive layer. Another object is to provide a semiconducting second wire, first and second contact plugs. The first and second wires are insulated from each other and electrically connected to the first and second plugs. The fuse layer and the

0503-6586TW;TSMC2001-0486; Vincent, ptd 第5頁 5024400503-6586TW; TSMC2001-0486; Vincent, ptd Page 5 502440

該第一接觸插塞電性連接。 維斑ίί雷ΐ!:利用多個金屬層及介層插塞組成溶線兩 之連接柱,使其兩端具有較中間部大之 冰度而可在中間部產生較高之電流密度。 製造=之說明本發明之一種半導體溶線裝置及其 圖式簡單說明 第ΙΑ、1Β圖顯示一傳統半導體雷射式金屬熔線裝置; 第2Α〜2F圖顯示本發明一實施例中之半導體電子式金 屬熔線之製造流程; 第3圖顯示本發明一實施例中之半導體電子式金屬溶 線裝置; 第4Α及4Β圖顯示本發明另一實施例中之半導體電子式 金屬熔線裝置。 $ [符號說明] 11、21〜矽基底; 12、 22〜多晶矽導線層; 13、 2 3、2 5、2 7〜絕緣層; 14、 241〜接觸插塞; 261、281〜介層插塞; 242、262〜金屬導線層; 15、282〜金屬熔線層; 24、28〜金屬層。 實施例The first contact plug is electrically connected. Weiban ίί Lei !: The use of multiple metal layers and interposer plugs to form the connection column of the two melting lines, so that both ends have a larger ice degree than the middle part and can generate a higher current density in the middle part. Manufacture = Description of a semiconductor melting line device of the present invention and a brief description thereof Figures 1A and 1B show a conventional semiconductor laser-type metal fuse device; Figures 2A to 2F show a semiconductor electronic device according to an embodiment of the present invention The manufacturing process of a metal fuse line; FIG. 3 shows a semiconductor electronic metal wire melting device in one embodiment of the present invention; and FIGS. 4A and 4B show a semiconductor electronic metal wire melting device in another embodiment of the present invention. $ [Symbol description] 11, 21 ~ silicon substrate; 12, 22 ~ polycrystalline silicon wire layer; 13, 2 3, 2 5, 2 7 ~ insulation layer; 14, 241 ~ contact plug; 261, 281 ~ via plug 242, 262 ~ metal wire layer; 15,282 ~ metal fuse layer; 24,28 ~ metal layer. Examples

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502440 五、發明說明(4) 第2 A〜2F圖顯示本實施例中之半導體電子式金屬熔線 之製造流程。 首先,如第2A圖所示,提供一矽基底21,矽基底21中 具有兩相互絕緣之多晶矽導線層22。 接著,如第2B圖所示,沉積一氧化層23做為絕緣層之 用’並在氧化層23中,利用光阻層微影及蝕刻步驟形成對 準多晶矽導線層22之介層孔231。 然後,如第2C圖所示,沉積一金屬層24填滿介層孔 231並覆蓋氧化層23。502440 V. Description of the invention (4) Figures 2A to 2F show the manufacturing process of the semiconductor electronic metal fuse in this embodiment. First, as shown in FIG. 2A, a silicon substrate 21 is provided. The silicon substrate 21 has two polycrystalline silicon wire layers 22 insulated from each other. Next, as shown in FIG. 2B, an oxide layer 23 is deposited as an insulating layer 'and in the oxide layer 23, a via hole 231 is formed to align the polysilicon wire layer 22 with a photoresist lithography and etching steps. Then, as shown in FIG. 2C, a metal layer 24 is deposited to fill the via hole 231 and cover the oxide layer 23.

再者’如第2D圖所示,藉由光阻層微影及蝕刻而在金 屬層24中定義出相互絕緣之金屬導線242,位於介層孔23 j 中之金屬層24則形成接觸插塞241。 接著,如第2E圖所示,重複第2B~2D圖顯示之三個步 驟’依序形成氧化層25、位於氧化層25中且與金屬導線層 242接觸之介層插塞261、金屬導線層262、氧化層27、位θ 於氧化層27中之介層孔271。同時,再沉積一金屬層28填 滿介層孔271並覆蓋氧化層27。其中每一金層導線層242 \ 262及介層插塞241、261之寬度相同。Furthermore, as shown in FIG. 2D, a metal wire 242 insulated from each other is defined in the metal layer 24 by photolithography and etching of the photoresist layer, and the metal layer 24 in the via hole 23j forms a contact plug. 241. Next, as shown in Fig. 2E, the three steps shown in Figs. 2B to 2D are repeated to sequentially form the oxide layer 25, the interposer plug 261 located in the oxide layer 25 and contacting the metal wire layer 242, and the metal wire layer 262. The oxide layer 27. The via hole 271 located at θ in the oxide layer 27. At the same time, a metal layer 28 is deposited to fill the via hole 271 and cover the oxide layer 27. Each of the gold wire layers 242 \ 262 and the via plugs 241 and 261 have the same width.

最後,如第2F圖所示,藉由光阻層微影及蝕刻而在金 屬層28中定義出金屬熔線282,位於介層孔271中之金屬層 28則形成介層插塞281。 在本實施例之半導體金屬熔線裝置中,金屬導線 242、262與介層插塞241、261、281組成一與金屬熔線282 電性連接之連接柱結構,當一大電流由一端連接柱流經金Finally, as shown in FIG. 2F, a metal fuse 28 is defined in the metal layer 28 by lithography and etching of the photoresist layer, and the metal layer 28 in the via hole 271 forms a via plug 281. In the semiconductor metal fusible link device of this embodiment, the metal wires 242, 262 and the interposer plugs 241, 261, 281 form a connecting post structure electrically connected to the metal fusible link 282. When a large current is connected to the post from one end Gold flow

0503-6586TW;TSMC2001-0486;Vincent.ptd 第7頁 502440 五、發明說明(5) 屬熔線282到達另一連接柱時,由於連接柱之深度較金屬 溶線層之深度大,造成金屬熔線282中產生一高電流密 度,使得金屬熔線282將首先被熔斷。因此,在本實施例 中,金屬熔線之形狀可以是等寬之線條而不需將兩端加寬 成「Η」狀。 因此,本實施例可以以第3圖之結構顯示,其熔線層0503-6586TW; TSMC2001-0486; Vincent.ptd Page 7 502440 V. Description of the invention (5) When the fused wire 282 reaches another connecting post, the depth of the connecting post is greater than the depth of the metal melting wire layer, causing the metal fuse A high current density is generated in 282, so that the metal fuse 282 will be blown first. Therefore, in this embodiment, the shape of the metal fuse can be a line of equal width without widening the two ends into a "Η" shape. Therefore, this embodiment can be shown in the structure of FIG. 3, and its fuse layer

282兩端之連接柱291、292係由第η層之導線層、第η層之 介層插塞及第η-1層之導線層所組成,使其兩端之深度較 溶線層282深,而可以在熔線層282中產生極高之電流密 度’在實際的例子中,熔線層之深度可以是3· 5k而兩側連 接柱291、292之深度可以到達9k,如此可產生出約i〇:i之 電流密度差’以30mA之電流約20 //s即可在熔線層282中產 生熔斷現象。The connecting posts 291 and 292 at both ends of 282 are composed of the η-layer wire layer, the η-layer via plug, and the η-1-layer wire layer. An extremely high current density can be generated in the fuse layer 282. In a practical example, the depth of the fuse layer can be 3.5k and the depth of the connecting pillars 291 and 292 on both sides can reach 9k, which can produce about The current density difference of i0: i 'can cause a fuse phenomenon in the fuse layer 282 with a current of 30 mA for about 20 // s.

此外,本發明亦可以具有兩端不同深度之結構,如第 4A圖所示,在熔線層282 —侧之連接柱291係由第η層之導 線層、第η層之介層插塞及第η—1層之導線層所組成,而另 一侧之連接柱292則僅由第η層之導線層組成;或者,如第 4Β圖所示在熔線層282 —側之連接柱291係由第η層之導線 層、第η層之介層插塞及第n + 1層之導線層所組成,而另一 側之連接柱292則僅由第n層之導線層組成。 綜合上述,本發明藉由使用金屬内連線層中多個導線 層及介層插塞組成之連接柱,加大熔線兩端之深度,並以 此造成熔線之中間部與兩端之電流密度差,使得熔線之中In addition, the present invention may also have a structure with different depths at both ends. As shown in FIG. 4A, the connecting post 291 on the side of the fuse layer 282 is composed of the n-layer wire layer, the n-layer dielectric plug, and The η-1 layer is composed of the wire layer, and the connection post 292 on the other side is only composed of the η layer of the wire layer; or, as shown in FIG. 4B, the connection post 291 on the fuse layer 282 side It consists of the n-th wire layer, the n-th interposer plug, and the n + 1 layer wire layer, and the other side of the connecting post 292 is only composed of the n-th wire layer. To sum up, the present invention increases the depth of the two ends of the fuse wire by using a connecting post composed of a plurality of wire layers and via plugs in the metal interconnect layer, thereby creating a middle portion and two ends of the fuse wire. The difference in current density makes the fuse

間部得以較其他區域早—The section was earlier than the other areas—

0503-6586TW;TSMC2001-0486;Vincent.ptd 第8頁 5024400503-6586TW; TSMC2001-0486; Vincent.ptd Page 8 502440

Claims (1)

六、申請專利範圍 1· 一種半導體熔線裝置之 1 提供一基底,該基底具 包括以下步驟 導線,該第一及第二導後相5 導電層定義一第一及 4 冰相互絕絡· 在該基底上形成與該第一及 _、、 ’ 及第二接觸插塞; 一導線電性連接之第一 形成一與該第一接觸插塞電 及 1王連接之第二導 形成一熔線層,與該第二導 第 插塞電性連接 電層;以 1層連接且與該第二接觸 法,其中更包括以 2 ·如申請專利範圍第1項所述之方 下步驟·· 及 形成一與該第二接觸插塞電性連接 之第三導電層;以 使該熔線層與該第三導電層連接。 3.如申請專利範圍第}項所述之方法,其中該基底係 一矽基底。 4·如申請專利範圍第1項所述之方法,其中該第一導 電層係多晶矽層。 5·如申請專利範圍第1項所述之方法,其中該第二導 電層及該熔線層係金屬層。 6· —種半導體熔線裝置,包括· 一第一及第二導線,該第/及第二導線相互絕緣; 一第一及第二接觸插塞,分別電性連接至該第一及第Sixth, the scope of patent application 1. A semiconductor fuse device 1 provides a substrate, the substrate includes the following steps, the first and second lead phases 5 conductive layers define a first and 4 ice mutual insulation. A first contact electrically connected to the first contact plug and a second contact electrically connected to the first contact plug are formed on the substrate to form a fused wire. Layer, which is electrically connected to the second lead plug; an electrical layer connected to the second layer and the second contact method, which further includes the following steps: 2 as described in item 1 of the patent application scope; and Forming a third conductive layer electrically connected to the second contact plug; so that the fuse layer is connected to the third conductive layer. 3. The method according to item} of the patent application scope, wherein the substrate is a silicon substrate. 4. The method according to item 1 of the patent application, wherein the first conductive layer is a polycrystalline silicon layer. 5. The method according to item 1 of the scope of patent application, wherein the second conductive layer and the fusible link layer are metal layers. 6. A semiconductor fuse device comprising: a first and a second wire, the first and second wires are insulated from each other; a first and a second contact plug are electrically connected to the first and the second, respectively 0503-6586TW;TSMC2001.0486;Vincent.ptd 第 1〇 頁 502440 六、申請專利範圍 一導電層,與該第一接觸插塞電性連接;以及 一熔線層,與該導電層連接且與該第二接觸插塞電性 連接。 7. 如申請專利範圍第6項所述之裝置,其中更包括一 第三導電層,與該第二接觸插塞電性連接且與該熔線層連 8. 如申請專利範圍第6項所述之裝置,其中該基底係 一矽基底。 9. 如申請專利範圍第6項所述之裝置,其中該第一及 第二導線係多晶矽層。 10. 如申請專利範圍第6項所述之裝置,其中該導電層 及該熔線層係金屬層。0503-6586TW; TSMC2001.0486; Vincent.ptd Page 10 502440 6. Application scope: a conductive layer electrically connected to the first contact plug; and a fuse layer connected to the conductive layer and connected to the The second contact plug is electrically connected. 7. The device according to item 6 of the scope of patent application, which further includes a third conductive layer, which is electrically connected to the second contact plug and connected to the fuse layer. The device described above, wherein the substrate is a silicon substrate. 9. The device according to item 6 of the patent application scope, wherein the first and second wires are polycrystalline silicon layers. 10. The device according to item 6 of the scope of patent application, wherein the conductive layer and the fusible link layer are metal layers. 0503-6586TWF;TSMa〇01-0486;Vincent.ptd 第11頁0503-6586TWF; TSMa〇01-0486; Vincent.ptd Page 11
TW90122218A 2001-09-07 2001-09-07 Semiconductor fuse device and the manufacturing method thereof TW502440B (en)

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