559933559933
本發明是有關-種預防銅金屬層突起（Hillock)的 造方法，且特別是適用於—種銅金屬層經過化學機械研磨 平坦化製程之後_進行1切或碳切沉積製程，可以 預防銅金屬層突起。 發明背景 當積體電路的積集度增加，使得晶片的表面無法提供 足夠的面積以製作所需的内連線時，為了配合金氧半導體 (Metal Oxide Semiconductor)電晶體縮小後所需增加的内 連線#求，多重金屬化製程便逐漸成為許多積體電路元件 f採用的方式。對半導體元件後段製程而言，隨著金屬線 寬（Width of Metal Line)的日漸縮小，金屬線所承受之電流 密度（Current Density)，相對地逐漸增大。傳統以鋁金屬為 主所形成之金屬線’遭受到電遷移（E|ectr〇n Migration，EM) 效應的影響，進而導致元件之可靠度（Re|iabj丨jty)降低。而 且隨著金屬線寬的日漸縮小，金屬線的阻值（Resjst)也越來 越高。為解決上述半導體元件進入深次微米製程時所遭遇 之課題，使用電遷移效應極小及阻值較低之銅金屬，就成 了所有半導體元件製造者一致的選擇。 將金屬銅應用在金屬内連線的製程上，可提供無數的 優點，因為銅具有低阻值、高熔點、高抗電移能力 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公楚)The invention relates to a manufacturing method for preventing the copper metal layer from protruding (Hillock), and is particularly suitable for the copper metal layer that undergoes a chemical mechanical polishing and flattening process. A 1-cut or carbon-cut deposition process can be performed to prevent copper metal. Layer protruded. BACKGROUND OF THE INVENTION When the accumulation degree of integrated circuits is increased, so that the surface of the wafer cannot provide enough area to make the required interconnects, in order to cooperate with the shrinkage of Metal Oxide Semiconductor transistors, the increased internal The connection #requirement, the multiple metallization process has gradually become the method adopted by many integrated circuit components f. For the later stages of semiconductor device manufacturing, as the Width of Metal Line is shrinking, the current density that the metal line is subjected to has gradually increased. The traditionally formed metal wire ′ mainly composed of aluminum metal suffers from the effects of electromigration (EM), which leads to a decrease in the reliability of the device (Re | iabj 丨 jty). Moreover, as the width of the metal line is gradually reduced, the resistance value (Resjst) of the metal line becomes higher and higher. In order to solve the above-mentioned problems encountered when semiconductor devices enter the deep sub-micron process, the use of copper metal with minimal electromigration effect and low resistance has become a consistent choice for all semiconductor device manufacturers. Applying metal copper to the process of metal interconnects can provide countless advantages, because copper has low resistance, high melting point, and high resistance to electromigration. This paper is sized to the Chinese National Standard (CNS) A4 specification (210X297 cm) )
............... (請先閲讀背面之注意事項再場寫本頁} -一 tv 線 經濟部智慧財產局員工消費合作社印製 五、發明説明（） (Electro-Migration Resistance)等優點。而且銅的内連線電 路可以改善日日#的運作速率，與@相比較，銅内連線可以 提高約2倍的運作速率。利用金屬鎮嵌的製程來形成銅内 連線的結構，不但可以降低Rc延遲時間，還可以降低内 連線之間的靜電電容量。因此為了提高元件積集度，以及 元件導通速度，使用金屬銅來形成金屬内連線的結構已成 為一種趨勢。 在平坦化的過程中，化學機械研磨法是唯一能提供 VLSI (Very Large Scale Integration)，甚至 ULSI (Ultra............... (Please read the notes on the back before writing this page}-Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs of the TV. 5. Description of the Invention () ( Electro-Migration Resistance) and other advantages. And the copper interconnect circuit can improve the operating speed of Riri #. Compared with @, the copper interconnect can increase the operating rate by about 2 times. It is formed by the metal embedded process. The structure of the copper interconnects can not only reduce the Rc delay time, but also reduce the electrostatic capacitance between the interconnects. Therefore, in order to improve the component accumulation and the conduction speed of the components, metal copper is used to form the metal interconnects. Structure has become a trend. In the process of planarization, chemical mechanical polishing method is the only one that can provide VLSI (Very Large Scale Integration), or even ULSI (Ultra
Large Scale Integration )製程，達到全面性平坦化（G丨〇ba丨 Planarization)的一種技術。 、製^積體電路元件時，從元件的表面移除物質常須一 或多階段的製程，且在進行下一步製程前須將物質層平坦 化。隨著使用次數的增加，常用化學機械研磨法來完成物 質的移除和平坦化。化學機械研磨製程係利用壓力控制的 旋轉研磨表面（Rotating Polishing Surface)負載晶片， 使晶片表面朝下’並輸入研漿（Slurry )。研聚通常包括化 學活性組成（Chemically Active Component)比如酸或 鹼，和機械活性（Mechanically Active)比如二氧化石夕微 粒之研磨劑（Abrasive)。雖然正確的機制還未了解，但化 學反應和機械研磨促成研磨和平坦化等製程，且化學機械 研磨法已發展在銅金屬層和介電層的平坦化製程上。 習知的銅金屬鑲嵌製程，即是利用化學機械研磨進行 平坦化製程，研磨完成之後，銅金屬表面會暴露於大氣之 3 559933 A7 B7 五、發明説明（ 下而形成氧化銅材質於銅金屬表面之上。在後續沉積介電 層例如氮化石夕層或碳化矽層時，需先在沉積氮化矽或碳 化石夕的溫度下（約攝氏35〇度至400度）《以電漿移除此 氧化銅材質才能進行氮化矽或碳化矽的沉積以避免元件的 特性因氧化銅的存在而改變，因此，晶圓在氮化矽或碳化 夕沉積反應至中所待的時間因此而增加。經由電鍍成長的 銅金屬層在如此咼溫下會有再成長（Re-gr〇wth)的現象發 生，銅原子堆積的晶格會發生重排，因此，銅金屬層表面 會發生突起（Hillock)。 突起會影響銅金屬表面的平坦性而使後續的製程面臨 一個不平坦的表面而有很嚴重的影響，尤其是微影製程。 訂 另外，在最後品保檢測時，突起會產生黑點而被判定有瑕 疵而被刷掉，即使這些突起可能並未影響到元件的電性。 因此，如何避免銅金屬層表面產生突起成為一很重要的 題。 線 發明目的與概述 銅金屬層表面的突起，其實係因為一類似回火的製程 使銅金屬原子晶格重排所造成的。由實驗中亦發現單純二 氮化石夕層或碳化石夕層的沉積製程並不足以使銅金屬原子晶 格發生重排，但若是加上以電㈣除銅金屬層表面氧化= 的製程，則足以使銅金屬原子晶格重排而在銅金屬層表面 產生突起。 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公楚）Large Scale Integration) process, a technology to achieve comprehensive planarization (G 丨 〇ba 丨 Planarization). When manufacturing integrated circuit components, removing material from the surface of the component often requires one or more stages of processing, and the material layer must be planarized before proceeding to the next process. As the number of uses increases, chemical mechanical polishing is commonly used to complete the removal and planarization of the material. The chemical mechanical polishing process uses a pressure-controlled Rotating Polishing Surface to load a wafer so that the surface of the wafer faces downwards' and inputs the slurry. Research polymerization usually includes chemically active components (such as acids or bases) and mechanically active (such as abrasives of dioxide dioxide particles). Although the correct mechanism is not yet understood, chemical reactions and mechanical polishing facilitate processes such as polishing and planarization, and chemical mechanical polishing methods have been developed on the planarization process of copper metal layers and dielectric layers. The conventional copper metal inlay process is a planarization process using chemical mechanical polishing. After the polishing is completed, the copper metal surface will be exposed to the atmosphere. 3 559933 A7 B7 V. Description of the invention (The copper oxide material is formed on the copper metal surface. Above. In the subsequent deposition of a dielectric layer such as a nitride nitride layer or a silicon carbide layer, it is necessary to first remove the silicon nitride or carbide carbide layer at a temperature (approximately 35 to 400 degrees Celsius). This copper oxide material can only be used to deposit silicon nitride or silicon carbide to prevent the characteristics of the device from being changed by the presence of copper oxide. Therefore, the time required for the wafer to react to the silicon nitride or carbide during the deposition is increased. The copper metal layer grown by electroplating will re-grow at this high temperature, and the lattice of copper atoms will be rearranged. Therefore, the surface of the copper metal layer will be raised (Hillock). The protrusion will affect the flatness of the copper metal surface and make subsequent processes face an uneven surface, which has a serious impact, especially the lithography process. In addition, during the final quality assurance inspection The protrusions will be black spots and will be judged to be defective and brushed off, even if these protrusions may not affect the electrical properties of the device. Therefore, how to avoid the protrusions on the surface of the copper metal layer becomes a very important problem. The purpose of the invention and Summary The protrusions on the surface of the copper metal layer are actually caused by the rearrangement of the copper metal atomic lattice by a process similar to tempering. It was also found in the experiment that the deposition process of the pure dinitride layer or the carbide layer is not enough In order to rearrange the copper metal atomic lattice, but if the process of removing the oxidation of the surface of the copper metal layer by electrolysis is added, it is sufficient to rearrange the copper metal atomic lattice and generate protrusions on the surface of the copper metal layer. Applicable to China National Standard (CNS) A4 (210X297)
559933 五 、發明説明（559933 V. Description of Invention (
I 訂 一般移除氧化銅的製程溫度為配合後續的製程，約設 定在攝氏35G度至攝氏獅度。另外，為使電漿能移除銅 金屬層表面氧化銅，需要在晶圓片表面.加上一偏壓，以使 電聚中的帶電物質（離子）轟擊（BQmba — ent)晶圓片表 面，利用偏壓賦予帶電物質（離子）的動能使帶電物質（離 子）4里擊銅金屬層表面氧化銅以去除之。電漿轟擊晶圓片 表面的結果除了移除了銅金屬層表面氧化銅之外，帶電物 質（離子）所喪失的動能部分會轉化為熱而加熱晶圓片表 面，這也是單純一氮化矽層或碳化矽層的沉積製程並不足 以使銅金屬原子晶格發生重排，但若是加上以電漿移除銅 金屬層表面氧化銅的製程，則足以使銅金屬原子晶格重排 而在銅金屬層表面產生突起的主要原因。 有鑑於此，本發明的目的就是在提供一種銅金屬層的 製造方法，依此方法可以避免銅金屬層表面產生突起。 線 本發明的另一目的是在提供一種銅金屬層的製造方 法，依此方法係放棄以電漿轟擊的方法處理銅金屬層表面 的氧化銅，因而銅金屬層表面不會產生突起。 本發明的更進一步目的是在提供一種銅金屬層的製造 方法，依此方法利用反應性電漿處理銅金屬層表面的氧化 銅，因而銅金屬層表面不會產生突起。 根據本發明之上述目的，提出一種銅金屬層的製造方 法，即在化學機械研磨平坦化製程之後，將晶圓傳送至沉 積製程反應室。沉積製程反應室另外連接一遠端電漿產生 裝置。將含氫源（Proton Source)的氣體和惰性氣體一起 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 經濟部智慧財產局員工消費合作社印製 559933 五、發明説明（） 送入遠端電聚產生裝置，以一能量源例如無線電頻率電波 (Rad丨〇 Frequency wave)或微波（M丨cr〇㈧…句來產生且 有氫離子（H+)的電聚，再將電漿傳送進沉積製程反應^ 之内。沉積製程反應室維持在攝氏35〇度至攝氏4〇〇 =。 電敷中的氫離子會打斷二價銅離子（Cu2+)與氧離子（二 間的離子鍵而和氧離子結合成水（H2〇)，同時，電喂中具 有還原能力的物質可以將二價銅離子還原成銅（cu)。當； 有的氧化銅均被還原成銅之後，接著，可以在沉 應室中繼續進行介電材質的沉積製程。 反 由於本發明所揭露的去除氧化銅的方法不需要加入一 偏壓於晶圓片之上，係利用電漿中的氫離子和呈還原性的 物質來處理氧化銅，因此，電聚不會對晶圓片表面進 擊，可避免因為電激轟擊對晶圓片表面產生加熱的作用。 晶圓片在此一製程中面對的僅是攝氏35〇度至攝氏 度，因此，銅金屬原子晶格不會發生重排，而銅金屬層表 面也不會因銅金屬原子晶格發生重排而產生突起。曰 發明之詳細說明 現以一銅金屬鑲嵌製程為例，來說明本發明 銅金屬層的製造方法實際的應用。 八、 第1圖至第3圖所示，為根據本發明一較佳實施例之 一種雙金屬鑲嵌内連線的製造方法。 請參照第1圖，首先，提供一基底’ Q〇，在其上已 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公楚） ...............^.........^.........^ (請先閲讀背面之注意事項再填寫本頁；> 五、發明説明（） 形成有導線102以及元件（未繪示於圖上）等結構。接著， 在基底100上形成一層介電層104，其中，介電層1〇4例 如是以旋轉塗佈（spin coating)的方式所形成之有機介電材 料層，或是以化學氣相沉積法所形成之氟氧化梦層、碳氧 化矽層、多孔隙氧化矽層或是一般使用的無機材料層。 接著’於介電層104上形成一钱刻終止層]〇6，此 蝕刻終止層106對於介電層1〇4具有較大的蝕刻選擇比， 其例如是以化學氣相沉積法所形成之氮氧化矽層、氮化石夕 層、碳化>5夕層或是氧化;5夕層。 之後’定義蝕刻終止層106，以在對應於導線）〇2 之餘刻終止層1 06中形成一開口（未繪示於圖上），並裸露 出位於導線102上方之部分介電層彳04。 續之，於蝕刻終止層106以及裸露之介電層1〇4 上，形成一介電常數較低之介電層1〇8，此介電層1〇8對 於姓刻終止層106具有較大的蝕刻選擇比，其之材質係為 有機高分子介電材料，較佳的有機高分子介電材料包括 Allied Signal 之 FLARE(f 丨 uonirated p〇|y(ary 丨印㊀ ethers))、BCB (benzocyclobutene)、非晶系碳（am〇rph〇us carbon)或是Dow Chemica丨之SILK，且其形成方式例如是 旋塗法’或是以化學氣相沉積法所形成之氟氧化矽層、碳 氧化石夕層、多孔隙氧化石夕層或是一般使用的無機材料層。 接著，於介電層108上形成一層硬罩幕層彳1〇,此 硬罩幕層110例如是以化學氣相沉積法所形成之氮氧化矽 層、氧化矽層或是氮化矽層。之後，於硬罩幕層11〇上形 559933 A7 B7 五、發明説明（ 成一層圖案化光阻120,並裸露出部分硬罩幕層彳1〇。 接著’於硬罩幕層與介電層1〇8中形成溝渠122 與124，以及於蝕刻終止層1〇6與介電.層1〇4中形成與溝 渠124相連，並裸露出基底中欲導通之導線1〇2的介層窗 開口 126。 其中，形成溝渠122與124之方法包括以蝕刻終止 層106為蝕刻終點，去除部分硬罩幕層11〇以及介電層 108 ’直到裸露出部分蝕刻終止層彳〇6之表面，而形成介層 窗開口 126之方法係由蝕刻終止層1〇6之開口（未繪示於 圖上）去除部分介電層1 〇4，直到裸露出部分導線彳〇2之 表面。 續之，請參照第2圖，去除圖案化光阻120。接著， 於基底1〇〇上方形成一層共形的阻障層128，此阻障層128 之材質包括氮化鈕、鈕金屬、氮化鎢或是氮化鈦。此阻障 層128係保護介電層108與1〇4,於後續在溝渠122與124 以及介層窗開口 126中填滿導電材料時，不會受到導電材 料的擴散侵襲，造成元件電性問題，並藉此可以提高導電 材料與介電層彳04與1 〇6之間的黏著性。 之後，於阻障層128上形成一層銅晶種層]3〇，形 成銅晶種層130的方法係為一物理氣相沉積製程或是濺鑛 製程。接著，再以電鍍製程形成一銅金屬填滿溝渠124以 及介層窗開口 126。繼之，以一化學機械研磨移除位於介 電層108上之銅金屬及硬罩幕層而形成銅雙金屬鑲嵌 132。在化學機械研磨製程結束後，將基底1〇〇送入如第4 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) ............... (請先閲讀背面之注意事項再場寫本頁) -旬_ 經濟部智慧財產局員工消費合作社印製 559933 五、發明説明（ 圖所示之沉積製程反應室2〇〇,在， onn 在本實轭例中，此沉積製 可相於沉積介電材質，例如氮氧切、氮 化石夕、石厌化石夕或是氧化石夕等等。在此過程中，銅雙金 嵌132的表面會暴露在大氣中而產生氧化銅134。沉積製 程反應室·的溫度設定在約攝氏150度至攝氏55〇度， 較佳的溫度係介於約攝氏3〇0度至攝氏4〇〇度。 訂 線 經濟部智慧財產局員工消費合作社印製 請參照第4圖，第4圖係緣示依照本發明所揭露之去 除氧化銅的製造設傷之示意圖。適用於去除氧化銅的製造 設備包括一沉積製程反應t 2〇〇,—遠端冑聚產生裝置 202,兩者間以一通道2〇4連接。遠端電漿產生裝置2〇2 具有至少-氣體入口 206,適用於導入生成電漿之反應氣 體’儿積裝程反應室200尚具有一氣體出口 208連接一真 空系統210 ’真空系統210適用於在沉積製程反應室2〇〇 内的製程完成後經由氣體出口 2〇8移除沉積製程反應室 200内未的反應物質及尾氣。在基底彳〇〇送入沉積製程反 應至200之後’將反應氣體由氣體入口 2Q6送入遠端電焚 產生裝置202，此一反應氣體至少包括含氫源的氣體，在 遠端電漿產生裝置202中產生具有氫離子的電漿，此一氣 體可以為例如氫氣或是氨氣等等。遠端電漿產生裝置202 具有一能量源（未繪示於圖上）可將反應氣體打成電漿， 此一能量源可以為無線電電波、微波等等，在本實施例中 利用能量源產生低場高熱電漿（Low Field Torroidal Plasma)來裂解反應氣體。另外，此反應氣體可以混和一 惰性氣體，例如氬氣，惰性氣體可以降低產生電漿所需要 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 559933 A7I Order The process temperature for removing copper oxide is generally set to approximately 35G Celsius to Lion Celsius to match subsequent processes. In addition, in order for the plasma to remove the copper oxide on the surface of the copper metal layer, a bias voltage needs to be added to the wafer surface to enable the charged substance (ion) in the polymerization to bombard the surface of the wafer (BQmba — ent). , The kinetic energy imparted to the charged substance (ion) by the bias voltage is used to cause the charged substance (ion) 4 to strike the copper oxide on the surface of the copper metal layer to remove it. As a result of the plasma bombarding the surface of the wafer, in addition to removing the copper oxide on the surface of the copper metal layer, the kinetic energy lost by the charged substance (ions) will be converted into heat to heat the wafer surface. This is also simply silicon nitride. The deposition process of the silicon layer or silicon carbide layer is not sufficient to rearrange the copper metal atomic lattice. However, if a process for removing copper oxide on the surface of the copper metal layer by plasma is added, it is sufficient to rearrange the copper metal atomic lattice. The main cause of the protrusions on the surface of the copper metal layer. In view of this, it is an object of the present invention to provide a method for manufacturing a copper metal layer, which can avoid the protrusions on the surface of the copper metal layer. Another object of the present invention is to provide a method for manufacturing a copper metal layer, by which a method of treating copper oxide on the surface of a copper metal layer by plasma bombardment is discarded, so that no protrusions are generated on the surface of the copper metal layer. A still further object of the present invention is to provide a method for manufacturing a copper metal layer, by which a copper oxide on the surface of the copper metal layer is treated with a reactive plasma, so that no protrusions are generated on the surface of the copper metal layer. According to the above object of the present invention, a method for manufacturing a copper metal layer is proposed, that is, a wafer is transferred to a deposition process reaction chamber after a chemical mechanical polishing and planarization process. The reaction chamber of the deposition process is further connected with a remote plasma generating device. Proton Source gas and inert gas are used together. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm). Printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 559933 5. Description of invention () The far-end electro-polymerization generating device uses an energy source such as a radio frequency wave (Rad 丨 Frequency wave) or a microwave (M 丨 cr0㈧ ...) sentence to generate and collect hydrogen ion (H +), and then transmits the plasma. Within the deposition process reaction ^. The deposition process reaction chamber is maintained at 350 ° C to 400 ° C. The hydrogen ions in the electrodeposition will break the ionic bond between the copper ion (Cu2 +) and the oxygen ion (two) Combined with oxygen ions to form water (H2O), at the same time, substances with reducing ability in electric feeding can reduce divalent copper ions to copper (cu). When some copper oxides are reduced to copper, then, The dielectric material deposition process can be continued in the chamber. However, the method for removing copper oxide disclosed in the present invention does not need to add a bias voltage to the wafer, and uses hydrogen ions and plasma in the plasma. Reducing substance Copper oxide is processed, so electropolymerization will not attack the wafer surface, which can avoid heating the wafer surface due to electrical bombardment. The wafers face only 35 ° C in this process. To degrees Celsius, therefore, the copper metal atomic lattice will not rearrange, and the surface of the copper metal layer will not cause protrusions due to the rearrangement of the copper metal atomic lattice. The detailed description of the invention now uses a copper metal inlaying process as An example is used to illustrate the practical application of the method for manufacturing the copper metal layer of the present invention. 8. Figures 1 to 3 show a method for manufacturing a bimetal mosaic interconnect according to a preferred embodiment of the present invention. Please Referring to FIG. 1, first, a substrate 'Q0' is provided, on which the paper size has been applied to the Chinese National Standard (CNS) A4 specification (210x297) ............. ^ ......... ^ ......... ^ (Please read the precautions on the back before filling out this page; > V. Description of the invention () The wire 102 and components (not (Shown in the figure) and other structures. Next, a dielectric layer 104 is formed on the substrate 100, of which 104 are dielectric layers. For example, an organic dielectric material layer formed by a spin coating method, or a fluorine oxide dream layer, a silicon oxycarbide layer, a porous silicon oxide layer formed by a chemical vapor deposition method, or general use An inorganic material layer. Next, a stop layer is formed on the dielectric layer 104. This etch stop layer 106 has a large etching selection ratio for the dielectric layer 104, which is, for example, a chemical vapor phase. A silicon oxynitride layer, a nitride nitride layer, a carbonized layer or an oxide layer formed by a deposition method. After that, the etch stop layer 106 is defined to stop the layer at the moment corresponding to the wire). An opening (not shown in the figure) is formed in 06, and a part of the dielectric layer 彳 04 above the conductive line 102 is exposed. Continuing, a dielectric layer 108 having a lower dielectric constant is formed on the etch stop layer 106 and the exposed dielectric layer 104, and this dielectric layer 108 has a larger effect on the etch stop layer 106. The selection ratio of etching is based on organic polymer dielectric materials. The preferred organic polymer dielectric materials include FLARE (f 丨 uonirated p0 | y (ary 丨 India㊀ethers)), BCB ( benzocyclobutene), amorphous carbon (am〇rph〇us carbon), or SILK of Dow Chemica 丨, and the formation method is, for example, spin coating method or a fluorosilicon oxide layer formed by chemical vapor deposition method, carbon Oxidized stone oxide layer, porous porosity stone oxide layer, or inorganic material layer generally used. Next, a hard mask layer 10 is formed on the dielectric layer 108. The hard mask layer 110 is, for example, a silicon oxynitride layer, a silicon oxide layer, or a silicon nitride layer formed by a chemical vapor deposition method. After that, 559933 A7 B7 is formed on the hard mask layer 11 Ⅴ. Description of the invention (form a layer of patterned photoresist 120, and expose part of the hard mask layer 彳 10. Then, on the hard mask layer and the dielectric layer Trenches 122 and 124 are formed in 108, and a dielectric stop window opening is formed in etch stop layer 106 and dielectric. Layer 104 is connected to trench 124 and exposes the conductive wire 102 to be conducted in the substrate. 126. Among them, the method for forming the trenches 122 and 124 includes using the etch stop layer 106 as an etching end point, removing a part of the hard mask layer 110 and the dielectric layer 108 ′ until the surface of the etch stop layer 206 is exposed. The method of opening the interlayer window 126 is to remove a part of the dielectric layer 104 from the opening of the etching stop layer 106 (not shown in the figure) until the surface of the part of the wire 100 is exposed. Continued, please refer to In Figure 2, the patterned photoresist 120 is removed. Next, a conformal barrier layer 128 is formed on the substrate 100. The material of the barrier layer 128 includes a nitride button, a button metal, tungsten nitride, or nitrogen. Titanium. This barrier layer 128 protects the dielectric layers 108 and 104. 124 and the dielectric window opening 126 are filled with the conductive material, will not be affected by the diffusion of the conductive material, causing electrical problems of the device, and thereby can improve the adhesion between the conductive material and the dielectric layer 彳 04 and 106 After that, a copper seed layer is formed on the barrier layer 128. The method of forming the copper seed layer 130 is a physical vapor deposition process or a sputtering process. Then, an electroplating process is used to form a copper seed layer. The copper metal fills the trench 124 and the dielectric window opening 126. Next, a chemical mechanical polishing is performed to remove the copper metal and the hard cover layer on the dielectric layer 108 to form a copper bimetal mosaic 132. During the chemical mechanical polishing process After the end, send the substrate 100 to the 4th paper size as applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) ......... (Please read the back first Note for rewriting this page)-Xun _ printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 559933 V. Description of the invention (the deposition process reaction chamber shown in the figure 200), in this example, onn This deposition system is comparable to the deposition of dielectric materials, such as oxynitride, nitride Evening, fossilized stone or oxidized stone, etc. During this process, the surface of the copper double gold inlaid 132 will be exposed to the atmosphere to produce copper oxide 134. The temperature of the deposition process reaction chamber is set at about 150 degrees Celsius To 55 ° C, the preferred temperature is between about 300 ° C and 400 ° C. Printed by the Consumer Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to Figure 4, Figure 4 shows the margin Schematic diagram of copper oxide removal and manufacturing damage disclosed in accordance with the present invention. The manufacturing equipment suitable for copper oxide removal includes a deposition process reaction t 200, a remote polymerization generating device 202, with a channel 2 between the two. 〇4Connection. The remote plasma generating device 202 has at least a gas inlet 206, which is suitable for introducing a reaction gas for generating plasma. The reaction chamber 200 also has a gas outlet 208 connected to a vacuum system 210. The vacuum system 210 is suitable for After the completion of the process in the deposition process reaction chamber 200, the unreacted substances and tail gas in the deposition process reaction chamber 200 are removed through the gas outlet 208. After the substrate is sent to the deposition process to react to 200, the reaction gas is sent from the gas inlet 2Q6 to the remote electric incineration generating device 202. This reaction gas includes at least a hydrogen-containing gas, and the remote plasma generating device A plasma with hydrogen ions is generated in 202. This gas can be, for example, hydrogen or ammonia. The far-end plasma generating device 202 has an energy source (not shown in the figure) for converting the reactive gas into a plasma. The energy source may be radio waves, microwaves, etc. In this embodiment, the energy source is used to generate the plasma. Low Field Torroidal Plasma to crack the reaction gas. In addition, the reaction gas can be mixed with an inert gas, such as argon. The inert gas can reduce the plasma generation required. The paper size is in accordance with China National Standard (CNS) A4 (210X297 mm) 559933 A7
請 先 閲 讀 背 面 之 注 意 事 項 再 填 寫 本 頁 裝 訂 線 559933 A7 ______B7 ___ 五、發明説明（） 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 圖式之簡單說明 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： — I.............裝-' (請先閲讀背面之注意事項再填寫本頁> 圖至第3圖所示 馮很據本發明 平父佳貫施例之 一種雙金屬鑲嵌内連線的製造方法；以及 第4圖係緣示依照本發明所揭露之一種去除氧化銅的 製造設備之示意圖。 訂 經濟部智慧財產局員工消費合作社印製 圖式之標記說明 100 :基底 102 :導線 104、108 :介電層 106 :蝕刻終止層 110 :硬罩幕層 120 :光阻層 122、124 :溝渠 11 線 本紙張尺度適巾國g家標準(CNS)A4規格(2ΐ〇χ 297公f) 1 559933 A7 _B7^ 五、發明説明（） 126 :開口 128 :阻障層 130 :銅晶種層 132 :銅雙金屬鑲嵌 1 34 :氧化銅 136 :氮化矽層 200 :沉積製程反應室 202 :遠端電漿產生裝置 204 :通道 206 :氣體入口 208 :氣體出口 210 :真空系統 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐)Please read the precautions on the back before filling in the gutter on this page. 559933 A7 ______B7 ___ V. Description of the invention () To limit the invention, anyone skilled in the art can make all kinds of changes without departing from the spirit and scope of the invention. Changes and retouching, so the protection scope of the present invention shall be determined by the scope of the appended patent application. Brief description of the drawings In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows:-I .. ........... pack- '(Please read the precautions on the back before filling out this page> Figures to 3 show Feng Bi ’s bimetal according to the present invention, the example of a flat father The manufacturing method of inlaid interconnects; and FIG. 4 is a schematic diagram showing a manufacturing equipment for removing copper oxide disclosed in accordance with the present invention. Order the printed mark description 100 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs and the following: 102: Conductor 104, 108: Dielectric layer 106: Etching stop layer 110: Hard cover curtain layer 120: Photoresist layer 122, 124: Ditch 11 The paper size of this paper is suitable for national standards (CNS) A4 specifications (2ΐ〇). χ 297 male f) 1 559933 A7 _B7 ^ V. Description of the invention () 126: opening 128: barrier layer 130: copper seed layer 132: copper bimetal mosaic 1 34: copper oxide 136: silicon nitride layer 200: deposition Process reaction chamber 202: remote plasma generating device 204: channel 206: gas inlet 208: gas outlet 210: Vacuum system (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm)