TW575806B - A method for enhancing flash memory error correction capability and providing data encryption in the same time - Google Patents

Description

575806 V. Description of the invention (i) Field of invention = The invention is about the technology of flash memory _ material :! It can enhance the error correction in flash memory, and it also has the function of encrypting the content of the stored data. BACKGROUND OF THE INVENTION In order to avoid & ^. I already think of the body early (c e 1 1) because of the use of a, the mind will use the order of the algorithm to improve the accuracy of the data. The ECC used by One Man manages about 128 or 2 56 bytes at a time. The correction capability is a bit error, and it can be detected when it exceeds 2 bits. In order to improve memory capacity and reduce costs, the industry has developed multi-level flash memory, and uses lower-level flash memory to make lower-cost memory cards. This method will increase the demand for ECC correction capability, but increasing the £ (:(: correction capability will inevitably cause an increase in hardware circuits and increase the space for storing Error Correction Codes. This is a know-how One of the problems we face is: In addition, "the flash memory algorithm that does not encrypt data is easy to be cracked." A simple method is to add authentication procedures between the peripheral device and the host (Hosite), but This method still has a chance to be cracked, because as long as the connection between the logical block and the physical block in the memory is known, the location of the file can be found from the original data of the flash memory, so as long as it is written with specific data And by tracking the original data in the flash memory, you can easily find out the algorithm used by the peripheral device. This is a common practice.

Page 4 575806 V. Description of the Invention (2) Another challenge facing technology. SUMMARY OF THE INVENTION The purpose of the present invention is mainly to solve the above-mentioned shortcomings in the prior art, and propose a method that can simultaneously enhance the error correction capability of flash memory and encrypt data.

In order to achieve the above object, the present invention provides a method for enhancing the error correction capability of the flash memory and encrypting data at the same time, which is suitable for writing a data to be written into the flash memory, wherein the data to be written is Each page of data has a first data block, a second data block, a first error correction code to which the first data block belongs, a second error correction code to which the second data block belongs, and a Spare block, the method includes: A data writing procedure including the following steps: (a) planning each page of a buffer memory to have a first access block and a second access block A spare area access block; (b) setting a mapping mode of each page of the data to be written, wherein the mapping mode is about generating each bit of each page during mapping Address; (c) causing a bit mapper to perform the following steps in accordance with the mapping mode to which each page belongs: (c 1) causing the bit mapper to sequentially and interleave the bits in the first data block Element's logical address is mapped to this The access block and the actual address in the second access block; (c2) causing the bit mapper to sequentially and staggerly map the logical addresses of the bits in the second data block to the first An access block and the actual address in the second access block; (c 3) causing the bit mapper to sequentially and stagger the first

Page 5 575806 V. Description of the invention (3) ~ --- The logical address of each element in an error correction code is mapped to the actual address in the first access block and the second access block; (C4 ) Causing the bitmap two to sequentially and staggerly project the logical addresses of the bits in the second error correction code to the actual addresses in the first access block and the second access block; Make the bit mapper sequentially map each element of the spare block to the actual address in the spare block access block; (d) Have a flash memory writer make the buffer memory Data is written into the flash memory. °° In order to make those skilled in the art understand the purpose, characteristics and power amplifier of the present invention, the present invention will be described in detail with the following specific embodiments and the accompanying drawings as follows: Detailed description of the invention The technical thought considers that in the case of multi-level (Mu 11 i-1 e ve 1) flash memory, each memory may store more than 2 bits of information. If a memory unit When an error occurs, the chance of multiple bits being affected at the same time is great, that is, the chance of errors of more than 2 bits in the same area increases. Therefore, by implementing the method of the present invention, the information of multiple bits or more in each memory unit can be scattered to different areas as much as possible, and then written into the actual flash memory order. As a result, It can reduce the probability of all information in a single memory unit being erroneous, and there is no dilemma that traditional techniques are limited by the error correction capability of ECC hardware circuits.

Page 6 575806 V. Description of the invention (4) Another specific benefit brought by the present invention is in the aspect of data confidentiality-because the information of multiple bits in each 5 memory unit has been scattered to Different regions, so the original data on the flash memory has also been changed to have the role of encryption. However, the present invention further considers that the bit mapping (b ^ ^ PPing) method cannot be fixed because the fixed mapping method疋 This can be used to find the rules using special test data, so the method of dispersing the data must be randomly changed. According to the method of the present invention, each page of data is set with its own mapping rule, and then stored. In the spare area of each page (spare), it is finally read by firmware and mapped. Figure 1-shows a schematic diagram of the mapping procedure for each user before the data is written into the actual flash memory. The logical score of the data to be written = the content, such as each page of flash memory in the conventional art, has a second block 100, a second lean block 丨 02, a first data block 1⑽ The error correction code 104 belonging to the owner, the second error belonging to the second data block ι〇2 = the positive code 1G6, and the spare block, the spare block 108 is used to store and enter the tributary material. Each-page 10 maps to which it belongs. As for buffering: each of the nineteenth of the tenth of the tenth of the tenth of the tenth of the tenth style, the six swords have 12 access blocks 120, the end of the second access area, and the access block 124 of the spare area. Regarding the mapping of each bit, it needs to be further explained in conjunction with the flowchart in Figure 2. Figure 2 is a flowchart of the data writing procedure of the present invention. Step 2 0 is to plan each page 12 of the memory to have a first access block 丨 2 〇: First access block 122, spare area access block 124 (as shown in Figure 1) Show); step

Page 7 575806

Step 21 is to set the mapping mode of each page 10 of the data to be written, where the mapping mode is about generating the address of each bit in each page 10 at the time of mapping; step 22 is Make the one-bit mapper perform the following steps according to the mapping mode of each page 10. The step 23 is to make the bit mapper sequentially and staggered the data in the first data block 100. The logical address is mapped to the actual address in the first access block 120 and the second access block 122. Step 24 is to make the bit mapper sequentially and interleaved, and the logical address of each element in the block. Map to the first memory and fetch the actual address in f-an access block 122. Step 25 is to make the bit mapping state sequentially and staggered the logical bits of each bit in the first error correction code 104. The addresses are mapped to the actual bits in the first access block 120 and the second access block 122. Step '26 causes the bit mapper to sequentially and interleave the bits in the second error correction code 106. The logical address of the element is mapped to the first address in the first access block and the first address in the second access block 1 2 2; Step 2 7 The bit mapper sequentially maps each element of the spare block 108 to the spare area access block 124 = the actual address; step 28 is to cause a flash memory writer to buffer the data in the memory 12 Write to this flash memory. "Compared with the data writing method used in the present invention, the present invention can further include a data reading program. As shown in Fig. 3, it is a flowchart of the data reading program of the present invention. Step 30 is to make / The flash memory reader reads the data in the flash memory; step 32 is to make a bit reflect ^ according to the mapping method that each page 1 〇 belongs to, and sequentially store the flash memory The actual address of each element is mapped back to its original logical address.

Page 8 575806 V. Description of the invention (6) It is stored in the buffer memory and read in the memory 12 above. Example 1 A memory unit can store the above, then the block to be written and the two blocks. For the buffer block and a spare area management, the actual address in each data block in the following steps is included; B. Correct each bit address in the code; C. Make the bit area access the buffer memory in the block. Body 12; Step 34 is information. It takes multiple bits (Mul ti stores 2 bits as an example). If each page of the data contains more than one page of data, each page of the memory block accesses the block. Every-minute ... A The logical address of each bit of the element maps the logical address of the bit mapper to the actual address of the spare block by the mapper; D · Makes data written to the flash by a microprocessor from the buffer — One level of flash memory. A memory unit can store 2 bits, and it has more than two error correction codes, and it has more than two access pages. The mapping method is in order. And the maps to each access block are sequentially and sequentially, each bit of each actual bit in each error block is sequentially mapped to a spare flash memory writer to store the memory. The features of the present invention are summarized as follows ... The present invention can simultaneously achieve the functions of improving error correction ability and data confidentiality with minimum hardware requirements. The rules of remapping the original shell material are only known to the designer, so it is difficult to test the algorithm with specific data. The present invention is applicable to multi-level (Mul ti_levei) flash memory, especially when no hardware is added, the error is positive so as to obtain maximum data resilience. Page 9 575806 V. Description of the invention (7) The present invention is quite easy to implement by writing firmware. In addition to controlling the hardware cost to a minimum, it is a novel method in the related field, and it also has progress. And industrial applicability. Although the present invention has been disclosed as above with a specific embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

Page 10 575806 Brief description of the diagram Brief description of the diagram Figure 1 shows a schematic diagram of the mapping process performed by each element before the data is written into the actual flash memory of the present invention. FIG. 2 is a flowchart of a data writing procedure of the present invention. FIG. 2 is a flowchart of a lean purchase process of the present invention. Description of drawing number 1 0. Logical pagination of data to be written 1 0 0. First data block 1 0 2. Second data block 1 0 4. First error correction code 1 to which the first data block belongs 0 6. The second error correction code to which the second data block belongs 1 0 8. Spare block 1 2. Each page of the buffer memory 1 2 0. First access block 122. Second access block 124. Spare Area Access Block

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Claims (1)

$ 75806 575806 VI. The logical address of each element in the patent application code is mapped to the actual address in the first access block and the second access block; (c 5) The bit mapper makes the spare Each element of the block is sequentially mapped to the actual address in the access block of the second spare area; (d) A flash memory writer is caused to write data in the buffer memory to the flash memory. Body. 2. The method according to item 1 of the scope of patent application, wherein the method further comprises a data reading program, and the data reading program comprises the following steps: a flash memory reader is used to store the flash memory into the flash memory; Read the data of the memory; make a one-bit anti-mapper reverse-map the actual address of each element in the flash memory to its original logical address according to the mapping mode of each page; Stored in the buffer memory; a microprocessor reads data from the buffer memory. 3. The method according to item 1 of the scope of patent application, wherein the spare block is used to store a mapping method of a parent page of the tributary material to be written. 4. A method for enhancing the error correction capability of the flash memory and encrypting the data at the same time, which is suitable for writing data to be written into the flash memory, where each page of the data to be written ( p age) has more than two data blocks, the error correction code to which the two or more data blocks belong, and a backup Page 13 575806 VI. Block for patent application, the method includes: a data writing program, including the following steps: s The following steps: There are two or more (a) Each of the buffer memory ' Plan into an access block and a spare area access block. (B) Set the resource to be written from the two '# * ^ Λ,.,;, The parent's first page of the map to which it belongs, Wherein, the mapping method is related to the fact that one% of each page in each page generates the address at the time of mapping; Γ C) makes a one-bit mapping cry. For each mapping method to which each page belongs, perform the following steps: (cl) Make the bit mapper sequentially and staggerly map the logical address of each element in each data block to the actual address in each access block. Address; (c 2) enable the remote bitmaper to sequentially and staggerly map the logical addresses of the bits in each error correction stone to the actual addresses of the access blocks; (c 3) enable 3 bit mapper sequentially maps each element of the spare block to the actual address in the spare block access block (D) having a flash memory writer write the data in the buffer memory to the flash memory. 5. The method according to item 4 of the scope of patent application, wherein the method further comprises a data reading program, and the data reading program comprises the following steps: Page 14 575806 6. The scope of the patent application enables a flash memory reader to read the data in the flash memory; enables a one-bit anti-mapper to sequentially according to the mapping mode to which each page belongs. The actual address of each element in the flash memory is mapped back to its original logical address, and then stored in the buffer memory; a microprocessor reads data from the buffer memory. 6. The method according to item 4 of the scope of patent application, wherein the spare block is used to store a mapping mode of each page of the data to be written. Page 15