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TW589722B - Electronic element - Google Patents

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Publication number
TW589722B
TW589722B TW092100963A TW92100963A TW589722B TW 589722 B TW589722 B TW 589722B TW 092100963 A TW092100963 A TW 092100963A TW 92100963 A TW92100963 A TW 92100963A TW 589722 B TW589722 B TW 589722B
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TW
Taiwan
Prior art keywords
wiring substrate
electronic component
wiring
aforementioned
electronic
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Application number
TW092100963A
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Chinese (zh)
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TW200404355A (en
Inventor
Koji Bando
Original Assignee
Mitsubishi Electric Corp
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Publication of TW200404355A publication Critical patent/TW200404355A/en
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Publication of TW589722B publication Critical patent/TW589722B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H—ELECTRICITY
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    • H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
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    • H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
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    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
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    • H01L2924/19041—Component type being a capacitor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

An electronic element is provided, wherein a wiring board 2 is provided in such a way to wrap a semiconductor chip 1, and on the outside surface of the wiring board 2, a plurality of external terminals 8, which are disposed in a three dimensional way, that is, on the upper surface, side surfaces, and bottom surface of the wiring board and connected to electrode regions of a wiring pattern provided on the wiring board 2 so as to electrically connect to the outside, are mounted. Thus, the arrangement of an electronic device using the electronic element can be carried out freely even various design of final product of the electronic device is going to be dealt with.

Description

589722 五、發明說明（2) 電子裝置。 為解決上述之問題本發明之電子元件係具備：電子零 件；由柔軟性材料所構成，以包圍上述電子零件的方式配 置，且其外面側設有預定的配線圖案，並與上述電子零件 的電極領域電性連接之配線基板，以及在上述配線基板的 外側面以三次元之方式配置，為了與外部進行電性連接而 連接於上述配線圖案的電極領域之複數外部端子。此外， 上述電子零件係包含：諸如半導體晶片之主動元件，或電 容器、電阻等之被動元件。 根據該構成，在配線基板的外面側以三次元之方式設 置外部端子，藉此半導體元件的佈設（layout)，將不再侷 限於傳統之二次元之配置方式，而得以實現三次元的配 置。藉此，在設計由複數之電子元件所構成之電子裝置 時，相較於傳統之形狀，因可自由地決定電子裝置之形 狀，而得以大幅提昇電子裝置設計上的自由度。 此外，根據本發明之電子裝置係藉由：連接上述電子 元件之分別選出的外部端子而構成。根據該構成，由於能 以三次元之方式配置電子元件，因此在設計由複數之電子 元件所構成之電子裝置時，相較於傳統之形狀，因可自由 地決定電子裝置的形狀，而得以大幅提昇電子裝置設計的 自由度。此外，亦可大幅地增加訊號數。 [實施方式] 以下，參照圖式，說明本發明之電子元件以及使用該 電子元件之電子裝置之構造。589722 V. Description of the invention (2) Electronic device. In order to solve the above-mentioned problems, the electronic component of the present invention includes: an electronic component; a flexible material, which is arranged so as to surround the electronic component, and has a predetermined wiring pattern on an outer side thereof, and an electrode of the electronic component; A wiring substrate electrically connected in the field, and a plurality of external terminals arranged in the three-dimensional manner on the outer side surface of the wiring substrate, and connected to the electrode field of the wiring pattern for electrical connection with the outside. In addition, the above-mentioned electronic components include active components such as semiconductor wafers, or passive components such as capacitors and resistors. According to this configuration, the external terminals are arranged in a three-dimensional manner on the outer side of the wiring substrate, whereby the layout of the semiconductor elements is no longer limited to the traditional two-dimensional arrangement, and a three-dimensional arrangement can be realized. As a result, when designing an electronic device composed of a plurality of electronic components, compared with the conventional shape, the shape of the electronic device can be freely determined, thereby greatly improving the degree of freedom in the design of the electronic device. In addition, the electronic device according to the present invention is constituted by connecting individually selected external terminals of the above-mentioned electronic components. According to this configuration, since electronic components can be arranged in a three-dimensional manner, when designing an electronic device composed of a plurality of electronic components, compared with the conventional shape, the shape of the electronic device can be freely determined, which greatly increases the shape of the electronic device. Increase the freedom of electronic device design. In addition, the number of signals can be greatly increased. [Embodiment] Hereinafter, the structure of an electronic component of the present invention and an electronic device using the electronic component will be described with reference to the drawings.

314335.ptd 第6頁 589722 五、發明說明（3) (第1實施形態） 參照第1圖至第4圖，說明本實施形態之電子元件之一 例之半導體元件1 1 1的構造。 (半導體元件111的構造） 參照第1圖至第4圖，該半導體元件1 1 1其内部係具 備：作為電子零件之半導體晶片1。該半導體晶片1的上面 部的長邊方向的兩側部，設有複數電極領域3。 以包圍半導體晶片1的方式配置由柔軟性材料所形成 之配線基板2。配線基板2的材質，可例舉聚醯亞胺、玻璃 壞氧樹脂等材料。 配線基板2’以包辰半導體晶片1之方式配置’同時在 半導體晶片1之設有電極領域3之側的同一面側，配置有配 線基板2之端部的對接部2 A。 配線基板2的外面側，設有預定的配線圖案（省略圖 示），而設於配線基板2的外面側之電極領域2 B，與設於半 導體晶片1之電極領域3 ’係措由引線（w i r e ) 4進行電性連 接。配線基板2係透過接著層5、6而接著固定於半導體晶 片卜 以覆蓋電極領域2 B、3、以及引線4，同時充填半導體 晶片1與配線基板2之間的空隙之方式形成密封用密封樹脂 7。利用該密封樹脂7，即可避免電極領域2 B、3以及引線4 與外部的其他電氣端子間的短路、電極領域2 B、3與引線4 間的連接領域之破損等問題的產生，進而達成半導體元件 1 1 1的可靠性的提昇。314335.ptd Page 6 589722 V. Description of the Invention (3) (First Embodiment) The structure of a semiconductor element 1 1 1 which is an example of an electronic component in this embodiment will be described with reference to FIGS. 1 to 4. (Structure of Semiconductor Element 111) Referring to Figs. 1 to 4, the semiconductor element 1 1 1 has internal components: a semiconductor wafer 1 as an electronic component. A plurality of electrode regions 3 are provided on both sides of the upper side of the semiconductor wafer 1 in the longitudinal direction. A wiring substrate 2 made of a flexible material is disposed so as to surround the semiconductor wafer 1. Examples of the material of the wiring board 2 include polyimide and glass oxyresin. The wiring substrate 2 'is arranged as a Baochen semiconductor wafer 1. At the same time, on the same surface side of the semiconductor wafer 1 on which the electrode region 3 is provided, an abutting portion 2 A at an end portion of the wiring substrate 2 is arranged. A predetermined wiring pattern (not shown) is provided on the outer side of the wiring substrate 2, and an electrode region 2 B provided on the outer side of the wiring substrate 2 and an electrode region 3 ′ provided on the semiconductor wafer 1 are routed by leads ( wire) 4 for electrical connection. The wiring substrate 2 is fixed to the semiconductor wafer through the adhesive layers 5 and 6 so as to cover the electrode areas 2 B and 3 and the leads 4 while filling the gap between the semiconductor wafer 1 and the wiring substrate 2 to form a sealing resin for sealing. 7. With this sealing resin 7, problems such as short circuit between the electrode area 2 B, 3 and the lead 4 and other external electrical terminals, breakage of the connection area between the electrode area 2 B, 3, and the lead 4 can be avoided, and further achieved. The reliability of the semiconductor element 1 1 1 is improved.

314335.ptd 第7頁 589722 五、發明說明（4) 在配線基板2的外面側，設有在配線基板的上面、側 面、以及底面以三次元的配置方式，為了與外部進行電性 連接而連接於配線圖案之電極領域之複數外部端子8。該 外部端子8係由金屬材料等所形成，並大致呈球形形狀。 (其他之形態） 以與上述半導體元件1 1 1相同之構成方式形成，具有 其他外徑形狀之半導體元件，可例舉如第5圖與第6圖所示 之半導體元件112，第7圖與第8圖所示之半導體元件113， 以及第9圖與第1 0圖所示之半導體元件1 1 4。 第5圖、第7圖以及第9圖，為顯示半導體元件1 1 2、 1 1 3、1 1 4之構造之全體斜視圖。而第6圖、第8圖以及第1 0 圖，為顯示半導體元件1 1 2、1 1 3、1 1 4之内部構造之斜視 圖。此外，在與上述之半導體元件1 1 1相同或相當之部 分，標示相同的參考符號，並省略重覆之說明。 第5圖與第6圖所示之半導體元件11 2係具備以下之構 成。電極領域3以橫斷半導體晶片1的中央部之方式設置。 配線基板2上，與第3圖對應之上面、側面以及底面設有外 部端子8 (與第4圖對應之側面並未設置外部端子8 )。 此外，第7圖與第8圖所示之半導體元件1 1 3係具備以 下之構成。在半導體晶片1的對角線上5設置電極領域3。 配線基板2，以沿著半導體晶片1的四邊反折上來之方式配 置。同時在配線基板2的上面、側面、底面的所有面均設 有外部端子8。 此外，第9圖與第1 0圖所示之半導體元件1 1 4係具備以314335.ptd Page 7 589722 V. Description of the invention (4) The outer side of the wiring board 2 is provided with a three-dimensional arrangement on the upper, side and bottom sides of the wiring board for electrical connection with the outside A plurality of external terminals 8 in the electrode area of the wiring pattern. The external terminal 8 is formed of a metal material or the like and has a substantially spherical shape. (Other Forms) The semiconductor element having the same configuration as the above-mentioned semiconductor element 1 1 1 and having other outer diameter shapes can be exemplified by the semiconductor element 112 shown in FIG. 5 and FIG. 6, and FIG. 7 and FIG. The semiconductor element 113 shown in FIG. 8 and the semiconductor elements 1 1 4 shown in FIGS. 9 and 10. 5, 7 and 9 are overall perspective views showing the structure of the semiconductor device 1 1 2, 1 1 3, 1 1 4. 6, 8 and 10 are perspective views showing the internal structure of the semiconductor device 1 1 2, 1 1 3, 1 1 4. In addition, the same or equivalent parts as those of the above-mentioned semiconductor element 1 1 1 are denoted by the same reference symbols, and repeated explanations are omitted. The semiconductor element 112 shown in Figs. 5 and 6 has the following structure. The electrode region 3 is provided so as to cross the central portion of the semiconductor wafer 1. The wiring board 2 is provided with external terminals 8 on the upper, side, and bottom surfaces corresponding to FIG. 3 (the external terminals 8 are not provided on the side corresponding to FIG. 4). The semiconductor elements 1 1 3 shown in FIGS. 7 and 8 have the following configurations. An electrode region 3 is provided on a diagonal line 5 of the semiconductor wafer 1. The wiring substrate 2 is arranged so as to be folded back along the four sides of the semiconductor wafer 1. At the same time, external terminals 8 are provided on all surfaces of the upper surface, side surface, and bottom surface of the wiring substrate 2. In addition, the semiconductor elements 1 1 4 shown in FIGS. 9 and 10 are provided with

314335.ptd 第8頁 589722 五、發明說明（5) 下之構成。沿著半導體晶片1的四邊設置電極領域3。此外 配線基板2上，在沿著半導體晶片1的四邊的四個位置上設 有用以供引線4通過之開口部2 C。 以上，以上述構造形成之半導體元件1 1 1、1 1 2、 1 1 3、1 1 4，配線基板2的外面側係以三次元之方式設置外 部端子8，如此半導體元件的佈設（1 ayout)，不再侷限於 傳統之二次元之配置方式，而得以實現三次元之配置。藉 此，在設計由複數半導體元件所構成之電子裝置時，相較 於傳統之形狀，因可自由地決定電子裝置的形狀，而得以 大幅提昇電子裝置設計的自由度。 此外，有關外部端子8的設置位置，只要將外部端子 配置在上面、底面以及任一個側面中選出之3個面上，即 可形成外部端子8的三次元配置，並獲得上述之作用效 果。故不需在所有的面上，均配置外部端子8。此理在以 下所示之實施形態中亦同。 (第2實施形態） 以下，參照第1 1圖至第1 4圖，說明本實施形態之電子 元件的一例之半導體元件1 2 1之構造。此外，與上述半導 體元件1 1 1相同或相當之部分，標示相同之參考符號，並 省略重覆之說明。 (半導體元件121之構造） 參照第1 1圖至第1 4圖，將半導體元件1 2 1與第1實施形 態之半導體元件1 1 1進行比較時，其相異點僅在於：半導 體元件1 2 1，其配線基板2之端部的對接部2 A，係配置在半314335.ptd Page 8 589722 V. Composition of the invention (5). Electrode areas 3 are provided along the four sides of the semiconductor wafer 1. In addition, the wiring board 2 is provided with openings 2C at four positions along the four sides of the semiconductor wafer 1 for the leads 4 to pass through. Above, the semiconductor elements 1 1 1, 1 1 2, 1 1 3, 1 1 4 formed with the above structure, and the external terminals 8 of the wiring substrate 2 are provided in a three-dimensional manner. Thus, the layout of the semiconductor elements (1 ayout ), Is no longer limited to the traditional two-dimensional configuration, but can achieve three-dimensional configuration. As a result, when designing an electronic device composed of a plurality of semiconductor elements, the shape of the electronic device can be freely determined as compared with the conventional shape, thereby greatly improving the degree of freedom in the design of the electronic device. In addition, regarding the installation position of the external terminal 8, as long as the external terminal is arranged on the three surfaces selected from the upper, bottom, and any one side surface, the three-dimensional arrangement of the external terminal 8 can be formed, and the above-mentioned effect can be obtained. Therefore, it is not necessary to arrange external terminals 8 on all surfaces. The same applies to the embodiments shown below. (Second Embodiment) Hereinafter, the structure of a semiconductor element 1 2 1 which is an example of an electronic element in this embodiment will be described with reference to Figs. 11 to 14. In addition, parts that are the same as or equivalent to those of the semiconductor element 1 1 1 described above are denoted by the same reference symbols, and repeated explanations are omitted. (Structure of Semiconductor Element 121) Referring to FIGS. 11 to 14, when comparing the semiconductor element 1 2 1 with the semiconductor element 1 1 1 of the first embodiment, the only difference is that the semiconductor element 1 2 1. The butt joint 2 A at the end of the wiring board 2 is arranged in a half

314335_ptd 第9頁 589722 五、發明說明（6) 導體晶片1之設有電極領域3之側的相反面側。而其他構 成，係與第1實施形態之半導體元件111相同。 (其他之實施形態） 以與上述半導體元件121相同之構成方式形成，具有 其他外徑形狀之半導體元件，可例舉如第1 5圖與第1 6圖所 示之半導體元件122，第17圖與第18圖所示之半導體元件 123，以及第19圖與第2 0圖所示之半導體元件124。 第1 5圖、第1 7圖以及第1 9圖，為顯示半導體元件 122、123、124之構造之全體斜視圖。而第16圖、第18圖 以及第2 0圖，為顯示半導體元件1 2 2、1 2 3、1 2 4之内部構 造之斜視圖。此外，在與上述之半導體元件1 2 1相同或相 當之部分，標示相同的參考符號，並省略重覆之說明。 第15圖與第16圖所示之半導體元件122，其電極領域3 係以橫斷半導體晶片1的中央部之方式配置。此外，配線 基板2上在與半導體晶片1的中央部相對之位置上設有用以 供引線4通過之開口部2 D。而其他之構成，除配線基板2之 端部的對接部2 A配置在半導體晶片1之設有電極領域3之側 的相反面側外，與第5圖所示之半導體元件1 1 2相同。 此外，第1 7圖與第1 8圖所示之半導體元件1 2 3、以及 第1 9圖與第2 0圖所示之半導體元件1 2 4，除配線基板2之端 部的對接部2 A配置在半導體晶片1之設有電極領域3之側的 相反面側外，與第7圖所示之半導體元件1 1 3、第9圖所示 之半導體元件1 1 4具有相同之構成。 以上，以上述構造形成之半導體元件121、122、314335_ptd Page 9 589722 V. Description of the invention (6) The side of the conductor wafer 1 on which the electrode region 3 is provided is opposite to the side. The other configurations are the same as those of the semiconductor device 111 of the first embodiment. (Other Embodiments) The semiconductor element having the same structure as the semiconductor element 121 described above and having other outer diameter shapes can be exemplified by the semiconductor element 122 shown in FIG. 15 and FIG. 16, and FIG. 17 And the semiconductor element 123 shown in FIG. 18 and the semiconductor element 124 shown in FIG. 19 and FIG. 20. FIG. 15, FIG. 17, and FIG. 19 are overall perspective views showing the structures of the semiconductor elements 122, 123, and 124. 16, 18, and 20 are perspective views showing the internal structure of the semiconductor device 1 2 2, 1 2 3, 1 2 4. In addition, the same reference numerals are given to portions that are the same as or equivalent to those of the semiconductor element 1 2 1 described above, and repeated explanations are omitted. In the semiconductor element 122 shown in FIGS. 15 and 16, the electrode region 3 is arranged so as to cross the central portion of the semiconductor wafer 1. In addition, the wiring board 2 is provided with an opening portion 2D through which the lead 4 passes, at a position opposed to the central portion of the semiconductor wafer 1. The other configuration is the same as that of the semiconductor element 1 12 shown in FIG. 5 except that the butt portion 2 A at the end portion of the wiring substrate 2 is disposed on the side opposite to the side on which the electrode region 3 of the semiconductor wafer 1 is provided. In addition, the semiconductor elements 1 2 3 shown in FIG. 17 and FIG. 18 and the semiconductor elements 1 2 4 shown in FIG. 19 and FIG. 20, except for the butt portion 2 at the end portion of the wiring substrate 2 A is disposed outside the opposite surface side of the semiconductor wafer 1 on which the electrode region 3 is provided, and has the same configuration as the semiconductor elements 1 1 3 shown in FIG. 7 and the semiconductor elements 1 1 4 shown in FIG. 9. Above, the semiconductor elements 121, 122,

314335.ptd 第10頁 589722 五、發明說明（7) 1 2 3、1 2 4，係在配線基板2的外面側以三次元之方式設置 外部端子8，故半導體元件的佈設，將不再侷限於傳統之 二次元的配置，而得以實現三次元的配置。藉此，在設計 由複數半導體元件所構成之電子裝置時，相較於傳統之形 狀，因可自由地決定電子裝置的形狀，而得以大幅提昇電 子裝置設計的自由度。 (第3至第7實施形態） 在此，參照第2 1圖至第2 5圖，說明上述第2實施形態 之第1 9圖所示構造之半導體元件1 2 4的其他形態。分別顯 示之剖面構造，不僅適用於第9圖與第1 9圖所示之構造， 其亦可適用於上述之第1實施形態之半導體元件1 1 1、 1 1 2、1 1 3、1 1 4，以及第2實施形態之半導體元件1 2 1、 122、 123> 124° (第3實施形態） 首先，參照第2 1圖，說明本實施形態之半導體元件 1 3 1之構造。該半導體元件1 3 1之構造上的特徵在於其係採 用：取代上述各實施形態中所使用之引線4，而使用直接 設在配線基板2的外側面之配線突起部9，並將該配線突起 部9連接至設於半導體晶片1之電極領域3上之構成。利用 該構成，亦可獲得與上述各實施形態相同之作用效果。 (第4實施形態） 以下，參照第2 2圖，說明本實施形態之半導體元件 1 4 1之構造。該半導體元件1 4 1之構造上的特徵係在：與上 述之半導體元件1 3 1進行比較時，其相異點僅在於：半導314335.ptd Page 10 589722 V. Description of the invention (7) 1 2 3, 1 2 4 are external terminals 8 provided in a three-dimensional manner on the outer side of the wiring substrate 2, so the layout of semiconductor components will no longer be limited Due to the traditional two-dimensional configuration, the three-dimensional configuration can be realized. As a result, when designing an electronic device composed of a plurality of semiconductor elements, compared with the conventional shape, the shape of the electronic device can be freely determined, thereby greatly improving the degree of freedom in the design of the electronic device. (Third to Seventh Embodiments) Here, with reference to Figs. 21 to 25, other modes of the semiconductor element 1 24 of the structure shown in Fig. 19 of the second embodiment will be described. The cross-sectional structures shown separately are applicable not only to the structures shown in Figs. 9 and 19, but also to the semiconductor element of the first embodiment described above. 1 1 1, 1 1 2, 1 1 3, 1 1 4, and the semiconductor element 1 2 1, 122, 123 > 124 ° of the second embodiment (third embodiment) First, the structure of the semiconductor element 1 31 of this embodiment will be described with reference to FIG. 21. This semiconductor device 1 3 1 is structurally characterized in that it uses: instead of the leads 4 used in the above embodiments, a wiring protrusion 9 provided directly on the outer surface of the wiring substrate 2 is used, and the wiring is protruded. The portion 9 is connected to a structure provided on the electrode region 3 of the semiconductor wafer 1. With this configuration, the same functions and effects as those of the above embodiments can be obtained. (Fourth Embodiment) Hereinafter, the structure of the semiconductor element 141 of this embodiment will be described with reference to Figs. The semiconductor device 1 4 1 is structurally characterized in that, when compared with the above-mentioned semiconductor device 1 3 1, the difference is only that:

314335.ptd 第11頁 589722 五、發明說明（8) 體元件1 4 1，其配線基板2之端部的 導體晶片1之設有電極領域3之側的、妾部2A ’係配置在半 成，則與第3實施形態之半導體元目反面側。而其他構 成，即可獲得與上述各實施形態 31相同。藉由該構 (第5實施形態） 5之作用效果。 以下，參照第2 3圖，說明本實 y a 1 5 1之構造。該半導體元件！ 5〗之構:形態之半導體元件 述之半導體元件1 3丨進行比較時，其&上的特徵係在··與上 基板2的電極領域2β係設在配線基f相異點僅在於··配線 域2B與設於半導體晶片1之電極^ ^ 2的内面側，該電極領 (bump) 10來連接。藉由該構成，即3嫌，藉由導電體凸塊 態相同之作用效果。 X传與上述各實施形 (第6實施形態） 以下 麥知第24圖，說明本實施形態之半導體元件 1 6 1之構成。該半導體元件1 6丨之構造上的特徵係在：與上 述之半導體元件1 5 1進行比較時，其相異點僅在於：半導 體元件1 6 1，其配線基板2之端部的對接部2A，係配置在半 導體晶片1之設有電極領域3之側的相反面側。而其他構 成，則與第5實施形態之半導體元件151㈣。藉由該構 成，即可獲得與上述各實施形態相同之作用效果。 (第7實施形態） 首先，苓照第2 5圖，說明本實施形態之半導體元件 1 7 1之構造該半導體元件1 7丨之構造上的特徵係在於：在 上述之各只施形態之構造外，在配線基板2的外面側設置314335.ptd Page 11 589722 V. Description of the invention (8) For the body element 1 41, the conductor wafer 1 at the end of the wiring substrate 2 is provided with the electrode area 3 on the side, and the crotch 2A 'is arranged in half. , It is opposite to the semiconductor element of the third embodiment. In other configurations, it is possible to obtain the same structure as in each of the thirty-first embodiment. With this configuration (the fifth embodiment), the effect of 5 is obtained. Hereinafter, the structure of the present embodiment y a 1 5 1 will be described with reference to FIGS. The semiconductor element! 5 Structure: When comparing the semiconductor element 1 3 in the form of the semiconductor element, the characteristics of the & are compared with the electrode area 2β of the upper substrate 2 on the wiring base f. The only difference is that ... The wiring domain 2B is connected to the inner surface side of the electrode ^ 2 provided on the semiconductor wafer 1, and this electrode bump 10 is connected. With this configuration, i.e. 3, the same effect is obtained by the bump state of the conductor. X-transmission with each of the above-mentioned embodiments (sixth embodiment) The structure of the semiconductor element 161 of this embodiment will be described below with reference to Fig. 24. The structural feature of this semiconductor element 16 is that when compared with the above-mentioned semiconductor element 1 51, the only difference is that the semiconductor element 1 6 1 is the butt joint 2A at the end of the wiring substrate 2. It is arranged on the side of the semiconductor wafer 1 opposite to the side on which the electrode region 3 is provided. The other structure is the same as that of the semiconductor device 151A of the fifth embodiment. With this configuration, it is possible to obtain the same operational effects as those of the above embodiments. (Seventh Embodiment) First, the structure of the semiconductor element 1 71 according to this embodiment will be described with reference to FIGS. 25 and 5. The structure of the semiconductor element 17 is characterized by the structure of each of the above-mentioned embodiments. Also provided on the outer side of the wiring board 2

第12頁 314335.ptd 589722 五、發明說明（9) 用以增加配線總數之配線層2 E。藉由該構成，即可獲得與 上述各實施形態相同之作用效果。此外，即使配線基板2 之端部的對接部2 A為配置在半導體晶片1之設有電極領域3 之側的相反面側之構成，亦可獲得與上述各實施形態相同 之作用效果。 (第8實施形態） 上述之第1至第7實施形態皆為關於：使用做為主動元 件之半導體晶片1之半導體元件者，但如第2 6圖之剖面圖 所示，本實施形態係關於，以配線基板2覆蓋電容器、電 阻等被動元件1 1、1 2之電子元件1 8 1。其他之構造係與以 被動元件1 1、1 2取代第1至第7實施形態之半導體晶片1後 之形態相同。 根據該構成，同樣因為在配線基板2的外面側以三次 元之方式設置外部端子8，所以被動元件的佈設，不再侷 限於傳統之二次元的配置，而得以實現三次元的配置。如 此，在設計由複數被動元件所構成之電子裝置時，相較於 傳統之形狀，因可自由地決定電子裝置的形狀，而得以大 幅提昇電子裝置設計的自由度。 (第9至第1 1實施形態） 上述之第1至第8實施形態係關於電子元件之構造，而 以下所示之第9至第1 1實施形態乃關於使用第1至第8實施 形態所示之電子元件之電子裝置之構造。此外，例子中雖 以第7實施形態之半導體元件1 7 1進行說明，但對此並未加 以限定，第1至第6實施形態之半導體元件111、1 1 2、Page 12 314335.ptd 589722 V. Description of the invention (9) The wiring layer 2 E used to increase the total number of wirings. With this configuration, it is possible to obtain the same functions and effects as those of the above embodiments. In addition, even if the abutting portion 2A at the end portion of the wiring substrate 2 is arranged on the side opposite to the side on which the electrode region 3 of the semiconductor wafer 1 is provided, the same functions and effects as those of the above embodiments can be obtained. (Eighth Embodiment) The above-mentioned first to seventh embodiments are all related to: those who use the semiconductor element of the semiconductor wafer 1 as an active element, but as shown in the sectional view of FIG. 26, this embodiment is about The electronic components 1 8 1 of the passive components 1 1 and 12 such as capacitors and resistors are covered with the wiring substrate 2. The other structures are the same as those in which the semiconductor wafers 1 of the first to seventh embodiments are replaced with the passive elements 11 and 12. According to this configuration, also because the external terminals 8 are provided in a three-dimensional manner on the outer side of the wiring substrate 2, the arrangement of the passive components is no longer limited to the conventional two-dimensional configuration, and a three-dimensional configuration can be realized. In this way, when designing an electronic device composed of a plurality of passive components, compared with the conventional shape, the shape of the electronic device can be freely determined, thereby greatly improving the freedom of designing the electronic device. (9th to 11th Embodiments) The aforementioned 1st to 8th Embodiments are related to the structure of electronic components, and the 9th to 11th Embodiments shown below are related to the use of the 1st to 8th Embodiments. The structure of the electronic device of the electronic components shown. In addition, although the semiconductor element 1 71 of the seventh embodiment is described in the example, it is not limited thereto. The semiconductor elements 111, 1 1 2 of the first to sixth embodiments are not limited.

314335.ptd 第13頁 589722 五、發明說明（10) 113、114、m、122、123 及電子元件181亦可適用。 (第9實施形態） 124 31、141、1 51 芩照第2 7圖，說明本實施形態之電壯 造。該電子裝置201係使從設於半導體-衣置201之構 8中選出的外部端子8間直接連接，而H件1 7 1之外部端子 電子裝置。 梁成三次元構造之 故 相314335.ptd Page 13 589722 V. Description of the invention (10) 113, 114, m, 122, 123 and electronic component 181 are also applicable. (Ninth embodiment) 124 31, 141, 1 51 The electric construction of this embodiment will be described with reference to Figs. This electronic device 201 is an electronic device that directly connects the external terminals 8 selected from the structure 8 provided in the semiconductor-clothing device 201, and the H-piece 171 external terminals. The reason for Liang Cheng's three-dimensional structure

根據該構成，以三次元方式配置 在設計由複數半導體元件171所構成七體凡件171， 較於傳統之形狀，因可自由地決定電子包壯裝置20 1時 而得以大幅提昇電子裝置2 〇丨的設計的衣置2 0 1的形狀 由該構成亦可大幅地增加訊號數。 由度。此外， (第10實施形態） 參照第2 8圖，說明本實施形態之電 造。該電子裝置2 0 2之特徵為：不同於上^置^壯2之構 構造，其外部端子8間係透過導體構件來連】 f置2 0 it 件可使用導體片2卜或被動元件22。以上，—° "亥導體構 亦可獲得與上述第9實施形態相同之作用效猎本構成， (第1 1實施形態） > ^According to this configuration, the seven-body element 171 composed of a plurality of semiconductor elements 171 is arranged in a three-dimensional manner. Compared with the traditional shape, the electronic device 20 1 can be freely determined, thereby greatly improving the electronic device 2 〇 The shape of the designed clothes set 211 by this structure can also greatly increase the number of signals. By degrees. (Tenth embodiment) Referring to Fig. 28, the electrical structure of this embodiment will be described. The electronic device 2 0 2 is characterized in that it is different from the upper structure 2 and the strong 2 structure, and the external terminals 8 are connected through a conductive member.] F 2 2 it can use a conductor piece 2 or a passive component 22 . Above, the-° conductor structure can also have the same effect as the ninth embodiment described above (first embodiment) > ^

參照第2 9圖與第3 0圖，說明本實施形態之電子 2 0 3之構造。該電子裝置2 0 3係在預定位置具備^數^ f + 極3 1與複數内部電極3 2之筒狀基板3 0的内部，配置複4電 導體元件1 71，並選擇性地使設於半導體元件丨7丨之f 子8之間相連接而構成。本實施形態中，雖將複數個#、曾端The structure of the electron 203 in this embodiment will be described with reference to FIGS. 29 and 30. The electronic device 2 0 3 is provided with a plurality of ^ f + poles 3 1 and a plurality of internal electrodes 3 2 at a predetermined position inside a cylindrical substrate 30. A plurality of electric conductor elements 1 71 are arranged, and are selectively provided in The f-elements 8 of the semiconductor element 丨 7 丨 are connected to each other. In this embodiment, although a plurality of #, Zeng Duan

314335.ptd 第14頁 589722 五、發明說明（11) 體元件1 7 1配置為螺旋狀，但未必需將其配置為螺旋狀， 由任意之積層構造所構成之三次元構造均可適用。如第3 0 圖所示，筒狀基板3 0的内部，係藉由填充樹脂3 3，進行樹 脂密封。以上，藉由本構成，亦可獲得與上述第9實施形 態相同之作用效果。 (第12實施形態） 以下，參照第31圖至第37圖，以第7圖所示之第1實施 形態之半導體元件1 1 3為例，說明上述半導體元件之製造 方法。首先，如第3 1圖所示，準備帶狀配線基板2 F，在該 帶狀配線基板2 F上，藉由在4個位置衝孔而形成預定形狀 之開口部2 Η，同時形成大致呈四邊形的底面領域2 a、以及 由底面領域2 a的四邊以放射狀方式延伸之大致呈三角形的 彎折領域2 b、2 c、2 d、2 e。考慮到作業性，底面領域2 a係 藉由框架2 K而與帶狀配線基板2 F呈連接狀態。之後，再將 外部端子8安裝於底面領域2 a與彎折領域2 b、2 c、2 d、2 e 之連接部分之外面側的預定位置上。 接著，參照第3 2圖，利用接著膠帶（接著層）5將半導 體晶片1固定於底面領域2a。此外，彎折領域2b、2c、 2d、2e上亦分別黏貼接著膠帶（接著層）6。接著，參照第 33圖，彎折彎折領域2b、2c、2d、2e使其包裹半導體晶片 1，之後再將彎折領域2b、2c、2d、2e固定於半導體晶片1 的表面側。 接著，參照第3 4圖，利用引線4連接（引線接合（w i r e b ο n d i n g ))設於配線基板2的外面側之電極領域2 B與設於半314335.ptd Page 14 589722 V. Description of the Invention (11) The body element 1 7 1 is arranged in a spiral shape, but it is not necessary to arrange it in a spiral shape. A three-dimensional structure composed of any laminated structure can be applied. As shown in Fig. 30, the inside of the cylindrical substrate 30 is sealed with a resin by filling the resin 33. As described above, with this configuration, the same effects as those of the ninth embodiment can be obtained. (Twelfth Embodiment) Hereinafter, a method for manufacturing the above-mentioned semiconductor element will be described with reference to FIGS. 31 to 37 and the semiconductor element 1 1 of the first embodiment shown in FIG. 7 as an example. First, as shown in FIG. 31, a strip-shaped wiring substrate 2 F is prepared, and the strip-shaped wiring substrate 2 F is punched at four positions to form openings 2 预定 of a predetermined shape, and at the same time, approximately A quadrangular bottom region 2 a and a substantially triangular bent region 2 b, 2 c, 2 d, 2 e extending radially from the four sides of the bottom region 2 a. In consideration of workability, the bottom surface area 2a is connected to the strip-shaped wiring substrate 2F by the frame 2K. After that, the external terminal 8 is mounted at a predetermined position on the outer surface side of the connection portion between the bottom area 2 a and the bending area 2 b, 2 c, 2 d, 2 e. Next, referring to Fig. 32, the semiconductor wafer 1 is fixed to the bottom surface area 2a with an adhesive tape (adhesive layer) 5. In addition, adhesive tapes (adhesive layers) 6 are also attached to the bending areas 2b, 2c, 2d, and 2e, respectively. Next, referring to FIG. 33, the bending region 2b, 2c, 2d, and 2e are folded to wrap the semiconductor wafer 1, and then the bending regions 2b, 2c, 2d, and 2e are fixed to the surface side of the semiconductor wafer 1. Next, referring to FIGS. 3 to 4, an electrode area 2 B provided on the outer side of the wiring substrate 2 and a half electrode provided on the outer side of the wiring substrate 2 are connected by wire 4 (wire bonding (w i r e b ο n d i n g)).

314335.ptd 第15頁 589722 五、發明說明（12) 導體晶片1之電極領域9 知 覆蓋由引線4所連接2不。/妾者，參照第35圖與第36圖，在 . , 安之电極領域2 B與電極領娀3之丄車捲領域 的同時，利用樹脂注人員^ 3之連接^ 糾、丨、2古掊屯、M a 衣置7 0進灯树脂7的注入（樹脂密 g ’、 ¥ te晶片1與配線基板2之間所產生之間隙 領域。 接著，參日8筮9 7m ,9 s m . 回’將複數外部端子8安裝於底面領 、I b、2c、1 2 3 4d、2e的外面側之預定位置上。 之後’猎由切斷帶狀配線基板2F之框架2κ，而完成半導體 元件1 1 3。 如^上所述’利用帶狀配線基板2F形成半導體元件 1 1 3 ’藉此即此夠以包圍半導體晶片1的方式配置配線基板 2，及將外部端子8安裝在配線基板2的外面側。此外，因 可適用於量產線，故可達成生產性的提昇。 (第1 3實施形態） 以下，參照第38圖至第44圖，並以第9圖所示之半導 體元件1 1 4為例’說明上述半導體元件之製造方法。首 先’如第3 8圖所不’準備帶狀配線基板2 F，在該帶狀配線 基板2F上，藉由在4個位置衝孔而形成預定形狀之開口部 2H，並形成大致呈四邊形的底面領域2a、以及由底面領域 2 a的四邊以放射狀方式延伸之大致呈三角形的彎折領域314335.ptd Page 15 589722 V. Description of the invention (12) The electrode field of the conductor wafer 1 is covered by the lead 4 and not connected. With reference to Figure 35 and Figure 36, while using the electrode area 2B and electrode collar 3 in the car roll area, use the resin injection personnel ^ 3 connection ^ correction, 丨, 2 ancient掊 tun, Ma clothes 7 into the lamp 7 resin injection (resin dense g ', ¥ te chip 1 and the gap between the wiring board 2 area. Then, on the day 8 筮 9 7m, 9 sm. Back 'A plurality of external terminals 8 are mounted at predetermined positions on the outer side of the bottom collar, I b, 2c, 1 2 3 4d, 2e. After that, the semiconductor element 1 is completed by cutting the frame 2κ of the strip-shaped wiring substrate 2F. 1 3. As described above, 'form the semiconductor element 1 by using the strip-shaped wiring substrate 2F' 1 3 'This is enough to arrange the wiring substrate 2 so as to surround the semiconductor wafer 1 and to mount the external terminal 8 on the wiring substrate 2 Outer side. In addition, it can be applied to mass production lines, so that productivity can be improved. (Thirteenth embodiment) Hereinafter, referring to FIGS. 38 to 44 and the semiconductor element 1 shown in FIG. 9 14 is taken as an example to explain the manufacturing method of the above-mentioned semiconductor element. First, prepare a strip-shaped assembly as shown in FIG. 38. A wire substrate 2F is formed on the strip-shaped wiring substrate 2F by punching holes at four positions to form openings 2H of a predetermined shape, and a substantially quadrangular bottom surface area 2a is formed. A generally triangular bending area extending radially

314335.ptd 第16頁 1 b、2 c、2 d、2 e。在彎折領域2 b、2 c、2 d、2 e上，分別形 2 成開口部2 C。此外’考慮到作業性，底面領域2 a係藉由框 3 架2K而與帶狀配線基板2F呈連接狀態。之後，再將外部端 4 子8安裝於底面領域2a與彎折領域2b、2c、2d、2e之連接 589722 五、發明說明（13) 部分之外面側的預定位置上。 接著，參照第3 9圖，利用接著膠帶（接著層）5將半導 體晶片1固定於底面領域2a。此外，彎折領域2b、2c、 2d、2e上亦分別黏貼接著膠帶（接著層）6。此外，需留意 不要使接著膠帶（接著層）6覆蓋開口部2C。接著，參照第 4 0圖，彎折彎折領2b、2c、2d、2e使其包裹半導體晶片 1，並將彎折領域2 b、2 c、2 d、2 e固定於半導體晶片1的表 面側。 接著，參照第4 1圖，配設引線4使其貫通開口部2C， 並利用引線4連接（引線接合）設於配線基板2的外面側之電 極領域2 B與設於半導體晶片1之電極領域3。接著，參照第 42圖與第43圖，覆蓋由引線4連接之電極領域2B與電極領 域3之連接領域露出之開口部2 C的同時，利用樹脂注入裝 置7 0進行樹脂7的注入（樹脂密封），以充填半導體晶片1與 配線基板2之間所產生之間隙領域。 接著，參照第4 4圖，將複數外部端子8安裝於底面領 域2 a與彎折領域2 b、2 c、2 d、2 e之外面側的預定位置上。 之後，藉由切斷帶狀配線基板2 F之框架2 K，而完成半導體 元件1 1 4。 如上所述，利用帶狀配線基板2 F形成半導體元件 1 1 4，藉此即能夠以包圍半導體晶片1的方式配置配線基板 2，及將外部端子8配置在配線基板2的外面側。此外，因 可適用於量產線，故可達成生產性的提昇。 此外，上述第1 2及第1 3實施形態係顯示第1實施形態314335.ptd Page 16 1 b, 2 c, 2 d, 2 e. In the bending areas 2 b, 2 c, 2 d, and 2 e, openings 2 C are formed respectively. In addition, in consideration of workability, the bottom surface area 2a is connected to the strip-shaped wiring substrate 2F through the frame 3 rack 2K. After that, the outer ends 4 and 8 are installed at the connection between the bottom area 2a and the bending areas 2b, 2c, 2d, and 2e. Next, referring to FIGS. 39 and 9, the semiconductor wafer 1 is fixed to the bottom surface area 2a with an adhesive tape (adhesive layer) 5. In addition, adhesive tapes (adhesive layers) 6 are also attached to the bending areas 2b, 2c, 2d, and 2e, respectively. Also, be careful not to cover the opening 2C with the adhesive tape (adhesive layer) 6. Next, referring to FIG. 40, the bending collars 2b, 2c, 2d, and 2e are folded to wrap the semiconductor wafer 1, and the bending areas 2b, 2c, 2d, and 2e are fixed on the surface of the semiconductor wafer 1. side. Next, referring to FIG. 41, a lead wire 4 is disposed so as to penetrate through the opening 2C, and an electrode area 2B provided on the outer side of the wiring substrate 2 and a electrode area provided on the semiconductor wafer 1 are connected (wire-bonded) with the lead wire 4 3. Next, referring to FIGS. 42 and 43, while covering the opening 2 C exposed in the connection area between the electrode area 2B and the electrode area 3 connected by the lead 4, the resin 7 is injected using the resin injection device 70 (resin sealing). ) To fill the gap area generated between the semiconductor wafer 1 and the wiring substrate 2. Next, referring to Figs. 4 and 4, a plurality of external terminals 8 are mounted at predetermined positions on the outer surface side of the bottom area 2a and the bending area 2b, 2c, 2d, and 2e. Thereafter, the frame 2 K of the strip-shaped wiring substrate 2 F is cut to complete the semiconductor element 1 1 4. As described above, by forming the semiconductor elements 1 1 4 by the strip-shaped wiring substrate 2 F, the wiring substrate 2 can be arranged so as to surround the semiconductor wafer 1, and the external terminals 8 can be arranged on the outer side of the wiring substrate 2. In addition, since it can be applied to mass production lines, productivity can be improved. In addition, the above-mentioned 12th and 13th embodiments show the first embodiment

m 314335.ptd 第17頁 五、 所示 形態 可 發明說明 之半 所示 利用 此外 而採用以 例如 述電子 域之連接 之接著層 加以密封 以密封， 電極領域 件的可靠 此外 極領域最 此外 之方式， 面側配置 此外 之方式， 面側配置 此外 述外部端 此外 以 (14) 導體元件1 1 3、 之半導體元件 相同之製造方 ’在上述之電 下所示之形態 :在上述電子 零件之電極領 機構；及設於 ，且至少上述 。如上所述， 藉此即可防止 與連接機構之 性的提昇。 ，在上述電子 好配置在上述 ，在上述電子 在上述電子零 上述基板之端 ，在上述電子 在上述電子零 上述基板之端 ，在上述電子 子之間之方式 ，在上述電子 及第造方法，但第2至第7實施 法來製"造施形態所示之電子元件均 。件中，為了以更佳的狀態實現 元件Φ η 域邀I，隶好具備：用以連接設於 上述兩ί配線基板之預定的電極領 電極；：零件與上述配線基板之間 項域與上述連接機構# 1 項域與連接機構係 t月曰 與外却4 u j W樹脂4 卜。P之其他電氣端子間之S力口 連接領域夕；^ ig笙 $ %、 只碌之破相寺，可達成 70件中，上述配線基板之預 配線基板的外面側或内面側。的電 兀件中，最好以包裹上述電子 件之設有上述電極領域之側％件 部的對接部。 同〜 元件中，最好以包裹上述電予〜 件之設有上述電極領域之側零件 部的對接部。 4目反 元件中，最好以介於上述基 配置配線層。 Η上 凡件中，最好在上述配線基m 314335.ptd Page 17 V. The form shown can be used in half of the invention. In addition, it is sealed with a bonding layer such as the connection in the electronic domain to seal. The electrode field is the most reliable way in the electrode field. In addition, the surface side is arranged in the other way, and the external side is arranged in the side. In addition, (14) the conductor element 1 1 3, the same semiconductor element manufacturing method as the form shown in the above electricity: the electrode of the above electronic parts Consular institutions; and at least the above. As described above, this can prevent the improvement of the connection with the mechanism. The above-mentioned electrons are arranged at the above-mentioned, the above-mentioned electrons are at the end of the electron-zero substrate, the above-mentioned electrons are at the end of the electron-zero substrate, between the electrons, the above-mentioned electrons and the first manufacturing method, However, the second to seventh implementation methods are all used to manufacture the electronic components shown in the manufacturing mode. In order to realize the component Φ η domain invitation I in a better state, it is better to have: a predetermined electrode collar electrode for connecting the two wiring substrates mentioned above; the item domain between the component and the wiring substrate and the above Connection mechanism # 1 The domain and the connection mechanism are month and month but 4 uj W resin 4 Bu. S power connection between other electrical terminals of P is connected to the field; ^ ig sheng $%, only the ruined temple of Lu can reach 70 out of the above-mentioned wiring substrates on the outer side or the inner side of the pre-wiring substrate. Among the electric parts, it is preferable to cover the abutting part of the electronic parts provided with the side parts of the electrode areas. Of the same components, it is preferable to cover the abutting portion of the above-mentioned electrode and the side component portion provided with the electrode field. In the 4-mesh reverse element, it is preferable to arrange the wiring layer with the above-mentioned base. Above all, it is best to use

314335.ptd 第18頁 589722 五、發明說明（15) 面側，設置預定的電極領域，並直接連接設於上述電子零 件之電極領域與上述配線基板之預定的電極領域，且在上 述配線基板的内部，以樹脂密封上述電子零件。 此外，在上述電子裝置中，最好使分別選出之各上述 外部端子間直接連接。 此外，在上述電子裝置中，最好使導體構件介於分別 選出之各上述外部端子間。 此外，在上述電子裝置中，最好具備：將上述電子裝 置安裝在，具備分別對應外表面與内表面之外部端子與内 部電極之筒狀基板的内部，並在使上述外部端子連接於預 定的上述内部電極的狀態下，以樹脂將上述電子裝置密封 於筒狀基板的内部之構造。 根據本發明之電子元件以及電子裝置，因在配線基板 的外面側配置三次元的外部端子，如此電子元件的佈設， 將不再侷限於傳統之二次元的配置，而得以實現三次元的 配置。藉此，在設計由複數之電子元件所構成之電子裝置 時，相較於傳統之形狀因其可自由地決定電子裝置的形 狀，故得以大幅提昇電子裝置設計的自由度。314335.ptd Page 18 589722 V. Description of the invention (15) On the side, a predetermined electrode field is provided, and it is directly connected between the electrode field of the electronic component and the predetermined electrode field of the wiring substrate. Inside, the electronic components are sealed with resin. Further, in the above electronic device, it is preferable that the external terminals selected separately are directly connected. Further, in the above electronic device, it is preferable that a conductive member is interposed between each of the external terminals selected separately. In addition, in the electronic device, it is preferable that the electronic device is mounted on a cylindrical substrate having external terminals and internal electrodes corresponding to the outer surface and the inner surface, and the external terminal is connected to a predetermined one. A structure in which the electronic device is sealed inside the cylindrical substrate with a resin in a state of the internal electrode. According to the electronic component and the electronic device of the present invention, since the three-dimensional external terminals are arranged on the outer side of the wiring substrate, the arrangement of the electronic components will no longer be limited to the traditional two-dimensional configuration, and the three-dimensional configuration can be realized. Therefore, when designing an electronic device composed of a plurality of electronic components, compared with the conventional shape, the shape of the electronic device can be freely determined, so that the degree of freedom in designing the electronic device can be greatly improved.

314335.ptd 第19頁 589722 圖式簡單說明 [圖式簡單說明] 第1圖為顯示第1實施形態之半導體元件之構造之全體 斜視圖。 第2圖為僅顯示第1實施形態之半導體元件的内部構造 之斜視圖。 第3圖為第1圖中之I I I - I I I線的箭號方向的剖面圖。 第4圖為第1圖中之IV-IV線的箭號方向的剖面圖。 第5圖為顯示第1實施形態之具有其他外徑形狀之半導 體元件之構造之全體斜視圖。 第6圖為僅顯示第5圖所示之半導體元件的内部構造之 斜視圖。 第7圖為顯示第1實施形態之具有其他外徑形狀之半導 體元件之構造之全體斜視圖。 第8圖為僅顯示第7圖所示之半導體元件的内部構造之 斜視圖。 第9圖為顯示第1實施形態之具有其他外徑形狀之半導 體元件之構造之全體斜視圖。 第1 0圖為僅顯示第9圖所示之半導體元件的内部構造 之斜視圖。 第1 1圖為顯示第2實施形態之半導體元件的構造之全 體斜視圖。 第1 2圖為僅顯示第2實施形態之半導體元件的内部構 造之斜視圖。 第1 3圖為第1 1圖中之X III -X I I I線的箭號方向的剖面314335.ptd Page 19 589722 Brief description of drawings [Simplified description of drawings] Fig. 1 is an overall perspective view showing the structure of the semiconductor device of the first embodiment. Fig. 2 is a perspective view showing only the internal structure of the semiconductor device of the first embodiment. Fig. 3 is a cross-sectional view taken along the line I I I-I I I in the direction of the arrow in Fig. 1. FIG. 4 is a cross-sectional view taken along the line IV-IV in the arrow direction in FIG. 1. Fig. 5 is an overall perspective view showing the structure of a semiconductor element having another outer diameter shape according to the first embodiment. Fig. 6 is a perspective view showing only the internal structure of the semiconductor element shown in Fig. 5; Fig. 7 is an overall perspective view showing the structure of a semiconductor element having another outer diameter shape according to the first embodiment. Fig. 8 is a perspective view showing only the internal structure of the semiconductor element shown in Fig. 7. Fig. 9 is an overall perspective view showing a structure of a semiconductor element having another outer diameter shape according to the first embodiment. Fig. 10 is a perspective view showing only the internal structure of the semiconductor element shown in Fig. 9. Fig. 11 is a perspective view showing the entire structure of a semiconductor device according to a second embodiment. Fig. 12 is a perspective view showing only the internal structure of the semiconductor device according to the second embodiment. Figure 13 is a section in the arrow direction of the X III -X I I I line in Figure 11

314335.ptd 第20頁 589722 圖式簡單說明 圖。 第1 4圖為第1 1圖中之X I V-X I V線的箭號方向的剖面 圖。 第1 5圖為顯示第2實施形態之具有其他外徑形狀之半 導體元件之構造之全體斜視圖。 第1 6圖為僅顯示第1 5圖所示之半導體元件的内部構造 之斜視圖。 第1 7圖為顯示第2實施形態之具有其他外徑形狀之半 導體元件之構造之全體斜視圖。 第1 8圖為僅顯示第1 7圖所示之半導體元件的内部構造 之斜視圖。 第1 9圖為顯示第2實施形態之具有其他外徑形狀之半 導體元件之構造之全體斜視圖。 第2 0圖為僅顯示第1 9圖所示之半導體元件的内部構造 之斜視圖。 第2 1圖至第2 5圖為顯示第3實施形態至第7實施形態之 半導體元件之構造之剖面圖。 第2 6圖為顯示第8實施形態之電子元件之構造之剖面 圖。 第2 7圖為顯示第9實施形態之半導體裝置的全體構造 之剖面構造圖。 第2 8圖為顯示第1 0實施形態之半導體裝置的全體構造 之剖面構造圖。 第2 9圖為顯示第1 1實施形態之半導體裝置的全體構造314335.ptd Page 20 589722 Schematic description Fig. 14 is a cross-sectional view of the X I V-X I V line in the arrow direction of Fig. 11. Fig. 15 is an overall perspective view showing the structure of a semiconductor element having another outer diameter shape according to the second embodiment. Fig. 16 is a perspective view showing only the internal structure of the semiconductor element shown in Fig. 15; Fig. 17 is an overall perspective view showing the structure of a semiconductor element having another outer diameter shape according to the second embodiment. Fig. 18 is a perspective view showing only the internal structure of the semiconductor element shown in Fig. 17. Fig. 19 is an overall perspective view showing the structure of a semiconductor element having another outer diameter shape according to the second embodiment. Fig. 20 is a perspective view showing only the internal structure of the semiconductor element shown in Fig. 19; 21 to 25 are cross-sectional views showing the structure of a semiconductor device according to the third embodiment to the seventh embodiment. Fig. 26 is a sectional view showing the structure of an electronic component according to an eighth embodiment. Fig. 27 is a cross-sectional structure diagram showing the entire structure of a semiconductor device according to a ninth embodiment. Fig. 28 is a cross-sectional structure diagram showing the entire structure of the semiconductor device of the tenth embodiment. Fig. 29 is a diagram showing the overall structure of the semiconductor device of the first embodiment

314335.ptd 第21頁 589722 圖式簡單說明 之剖面構造圖。 第3 0圖為顯示第1 1實施形態之半導體裝置的全體構造 之斜視圖。 第3 1圖至第3 7圖為顯示第1 2實施形態之半導體元件的 製造方法之第1至第7步驟圖。 第3 8圖至第4 4圖為顯示第1 3實施形態之半導體元件的 製造方法之第1至第7步驟圖。 第4 5圖為顯示傳統之電子元件（半導體裝置等）的構造 之全體斜視圖。314335.ptd Page 21 589722 A schematic drawing of a sectional structure. Fig. 30 is a perspective view showing the overall structure of the semiconductor device according to the eleventh embodiment. Figures 31 to 37 are diagrams showing the first to seventh steps of the method for manufacturing a semiconductor device according to the twelfth embodiment. Figures 38 to 44 are the first to seventh steps of the method for manufacturing a semiconductor device according to the thirteenth embodiment. Fig. 45 is an overall perspective view showing the structure of a conventional electronic component (semiconductor device, etc.).

1 半導體晶片 2 配線基板 2 a 底面領域 2b 、2 c、2 d、2 e 彎 2A 對接部 2B 、3電極領域 2C、 2D、 2H 開口 部 2E 配線層 2F 帶狀配線基板 2K 框架 4 引線 5 ^ 6接著層 7 密封樹脂 8 外部端子 9 配線突起部 10 導電體凸塊 1卜 1 2被動元件 21 導電片 22 被動元件 30 筒狀基板 31 外部電極 32 内部電極 33 樹脂 70 樹脂注入裝置 111 、112、 113、 114、 12卜 122、 123、 124 、m、 14 卜 15卜 161 > 1 7 1半導體元件 314335.ptd 第22頁 5897221 Semiconductor wafer 2 Wiring substrate 2 a Bottom area 2b, 2 c, 2 d, 2 e Bend 2A Butt 2B, 3 Electrode area 2C, 2D, 2H Opening 2E Wiring layer 2F Strip-shaped wiring substrate 2K Frame 4 Lead 5 ^ 6 Adhesive layer 7 Sealing resin 8 External terminal 9 Wiring protrusion 10 Conductor bump 1 2 Passive element 21 Conductive sheet 22 Passive element 30 Tube substrate 31 External electrode 32 Internal electrode 33 Resin 70 Resin injection device 111, 112, 113, 114, 12b 122, 123, 124, m, 14 b 15b 161 > 1 7 1 semiconductor element 314335.ptd page 22 589722

314335.ptd 第23頁314335.ptd Page 23

Claims (1)

589722 _案號92100963 年1月上[日 修正_ 六、申請專利範圍 1. 一種電子元件，具備： 電子零件； 由柔軟性材料所構成之配線基板，以包圍前述電 子零件之方式配置，且其外側面設有預定的配線圖 案，並與前述電子零件之電極領域電性連接；以及 以三次元之方式配置於前述配線基板的上面、側 面以及底面，為了與外部進行電性連接而連接於前述 配線圖案之電極領域之複數外部端子。 2. 如專利申請範圍第1項之電子元件，其中，具備：用以 連接設於前述電子零件之電極領域與前述配線基板之 預定的電極領域之連接機構；及設於前述電子零件與 前述配線基板之間之接著層，且至少前述電極領域與 前述連接機構係以樹脂加以密封。 3. 如申請專利範圍第2項之電子元件，其中，前述配線基 板之預定的電極領域係設在前述配線基板的外面側。 4. 如申請專利範圍第2項之電子元件，其中，前述配線基 板之預定的電極領域係設在前述配線基板的内面側。 5. 如申請專利範圍第1項之電子元件，其中，以包裹前述 電子零件之方式，在前述電子零件之設有前述電極領 域之側的同一面側配置前述配線基板之端部的對接 部° 6. 如申請專利範圍第1項之電子元件，其中，以包裹前述 電子零件之方式，在前述電子零件之設有前述電極領 域之側的相反面側配置前述配線基板之端部的對接589722 _Case No. 92100963 [Amended on June 6] Application scope 1. An electronic component comprising: an electronic component; a wiring substrate made of a flexible material, configured to surround the aforementioned electronic component, and its The outside surface is provided with a predetermined wiring pattern and is electrically connected to the electrode field of the electronic component; and is arranged on the upper surface, side surface, and bottom surface of the wiring substrate in a three-dimensional manner, and is connected to the foregoing for electrical connection with the outside. A plurality of external terminals in the electrode field of the wiring pattern. 2. The electronic component according to item 1 of the patent application scope, comprising: a connection mechanism for connecting the electrode field provided in the aforementioned electronic part and a predetermined electrode field provided in the aforementioned wiring substrate; and the electronic part and the wiring provided in the aforementioned A bonding layer between the substrates, and at least the electrode area and the connection mechanism are sealed with resin. 3. The electronic component according to item 2 of the patent application, wherein the predetermined electrode area of the wiring substrate is provided on the outer side of the wiring substrate. 4. The electronic component according to item 2 of the patent application scope, wherein the predetermined electrode area of the aforementioned wiring substrate is provided on the inner surface side of the aforementioned wiring substrate. 5. For the electronic component according to the first item of the patent application scope, in which the abutting portion of the end portion of the wiring substrate is arranged on the same side of the side of the electronic component where the electrode field is provided by wrapping the electronic component. 6. As for the electronic component in the first item of the patent application scope, the butt joints of the ends of the wiring board are arranged on the opposite side of the side of the electronic part where the electrode area is provided by wrapping the aforementioned electronic parts. 314335(修正版）.ptc 第24頁 589722 案號 92100963 %年：x月>ς曰 修正 六、申請專利範圍 部。 7. 如申請專利範圍第1項之電子元件，其中，以介於前述 配線基板與前述外部端子之間之方式設置配線層。 8. 如申請專利範圍第1項之電子元件，其中，在前述配線 基板的内面側設置預定的電極領域，並使設於前述電 子零件之電極領域與前述配線基板之預定的電極領域 直接連接，且在前述配線基板的内部，以樹脂密封前 述電子零件。314335 (revised version) .ptc page 24 589722 case number 92100963% year: x month > 7. The electronic component according to item 1 of the patent application scope, wherein a wiring layer is provided between the aforementioned wiring substrate and the aforementioned external terminal. 8. For the electronic component according to item 1 of the patent application scope, wherein a predetermined electrode area is provided on the inner side of the wiring substrate, and the electrode area provided on the electronic component is directly connected to the predetermined electrode area of the wiring substrate, The electronic components are sealed with a resin in the wiring substrate. 314335(修正版）.ptc 第25頁314335 (Revised) .ptc Page 25
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Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7115986B2 (en) * 2001-05-02 2006-10-03 Micron Technology, Inc. Flexible ball grid array chip scale packages
SG122743A1 (en) * 2001-08-21 2006-06-29 Micron Technology Inc Microelectronic devices and methods of manufacture
SG104293A1 (en) 2002-01-09 2004-06-21 Micron Technology Inc Elimination of rdl using tape base flip chip on flex for die stacking
SG115456A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
SG111935A1 (en) 2002-03-04 2005-06-29 Micron Technology Inc Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods
SG115455A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Methods for assembly and packaging of flip chip configured dice with interposer
SG121707A1 (en) * 2002-03-04 2006-05-26 Micron Technology Inc Method and apparatus for flip-chip packaging providing testing capability
SG115459A1 (en) 2002-03-04 2005-10-28 Micron Technology Inc Flip chip packaging using recessed interposer terminals
US6975035B2 (en) * 2002-03-04 2005-12-13 Micron Technology, Inc. Method and apparatus for dielectric filling of flip chip on interposer assembly
US20040036170A1 (en) * 2002-08-20 2004-02-26 Lee Teck Kheng Double bumping of flexible substrate for first and second level interconnects
US7112877B2 (en) * 2004-06-28 2006-09-26 General Electric Company High density package with wrap around interconnect
TWI244177B (en) * 2004-10-21 2005-11-21 Chipmos Technologies Inc Method for assembling image sensor and structure of the same
CN101371353B (en) 2006-01-25 2011-06-22 日本电气株式会社 Electronic device package, module and electronic device
JP2007266240A (en) * 2006-03-28 2007-10-11 Fujitsu Ltd Electronic device and electronic apparatus having the same
US7888185B2 (en) * 2006-08-17 2011-02-15 Micron Technology, Inc. Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device
JP2008078205A (en) * 2006-09-19 2008-04-03 Fujitsu Ltd Substrate assembly and manufacturing method thereof, electronic component assembly and manufacturing method thereof, and electronic apparatus
US9023511B1 (en) * 2012-12-18 2015-05-05 Amazon Technologies, Inc. Systems and methods for removably attaching a battery to a user device
CN103997848B (en) * 2014-05-30 2017-01-11 昆山一邦泰汽车零部件制造有限公司 Cylinder rotary printed circuit cylinder

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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US6225688B1 (en) * 1997-12-11 2001-05-01 Tessera, Inc. Stacked microelectronic assembly and method therefor
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