TW583583B - Apparatus and method for selective control of condition code write back - Google Patents

Abstract

A microprocessor apparatus and method are provided, for selectively controlling write back of condition codes. The microprocessor apparatus has translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction includes an extended prefix and an extended prefix tag. The extended prefix disables write back of the condition codes, where the condition codes correspond to a result of a prescribed operation. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within an instruction set for a microprocessor. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions, and generates the result, and disables write back of the condition codes.

Description

583583

-J · A7 B7_ V. Description of the invention (/) ~ ^ Contrast with related applications [0001] This application claims the superior number 10 / 144,593 based on the following US applications, and the application is May 2002 On the 9th, the patent was entitled "Apparatus and Method for Selectively Controlling Condition Code Writeback". [00〇2] This hat case is related to the U.S. patent application filed below: 'The application is the same as this case, and has the same applicant and ^ Mingren 0 TW SERIAL NUMBER DOCKET NUMBER Patent name 91116957 CNTR : 2176 Dad's microprocessor instruction set & setup and method 91116958 CNTR: 2186 Device and method for executing conditional instructions 91116959 91116672 CNTR: 2189 CNTR: 2198 The mechanism of the temporary check of the unvoiced processor selectively controls the result back Device and method for writing (1) Technical field of the invention: [0003] The present invention relates to the field of microelectronics, in particular to a device capable of incorporating selective condition code write-back control features into an existing microprocessor instruction set architecture. technology. (II) Technical background of the invention: [0004] Since its development in the early 1970s, the use of microprocessors has been 2 paper sizes applicable to the Chinese National Standard (CNS) A4 specification (210 X 2.97 public copy) IV-- --- ^ --- (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 583583 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 5. Description of the invention (>) Exponential growth. From the earliest applications in science and technology, to today's consumer domains that have introduced commerce from special areas such as desktop and laptop computers, video game controllers, and many other common home and business devices And other products. [0005] With the explosive growth in use over the past thirty years, it has also undergone a corresponding improvement in technology, which is characterized by the following requirements for increased benefits: faster speed, stronger addressing ability , Faster memory access, larger operands, more operations (such as floating-point operations, single instruction multiple data (SIMD), conditional movement, etc.), and additional special operations (such as multimedia operations). This has created amazing technological progress in this field, and has been applied to the design of microprocessors, such as extensive pipelining, ultra-scalar architecture, cache structure, and out-of-order processing. (Of-〇rder prcesscess), burst access, branch predication, and speculative execution. To put it bluntly, today's microprocessors are surprisingly more complex and powerful than they were when the shovel first appeared in 30 years. [0006] But unlike many other products, another very important factor has been limited and continues to limit the evolution of microprocessor architectures. Today's microprocessors can be so complicated, and a large part can be attributed to the compatibility of legacy software. In consideration of the market, most manufacturers choose to incorporate new architectural features into the latest microprocessor designs, but at the same time, in these most recent productions, all of them are retained to ensure compatibility with older, so-called Required for legacy applications. ----- V --- V ----- install --- (Please read the precautions on the back before filling this page) Order:

X 297 mm) 583583 A7

Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs [0007] This old software compatibility burden is nowhere more apparent than in the history of the development of x86-compatible microprocessors. Everyone knows that 'the current 32 / 16-bit virtual_mode x86 microprocessor' can still execute 8-bit real-mode applications written in chronology. And those who are familiar with this field also acknowledge that there are a lot of similar _architectural “coatings” stacked in χ86 _, just to support the old recordable and operational style_. In the past, developers could add newly developed architectural features to some old-fashioned structures, but nowadays, using the guards that these features rely on, they can be programmed instructions, but they are scarce. To put it simply, in some important instruction sets, there are no “redundant” instructions, allowing designers to incorporate more features into an existing architecture. ^ [0008] For example, 'In the x86 instruction set architecture, there is no one undefined-byte-sized opcode state, and it has not been used yet. In the main -byte size M6 opcode diagram, all said that the status of the opcode has been occupied by the existing instructions. As a result, designers of x86 microprocessors must now choose between providing new features and giving up legacy software compatibility. To provide new financial characteristics, Chastity must assign shipping codes to these characteristics. If the existing instruction coform does not have any extra code state ', then some existing opcode states must be redefined to provide new features. So, to provide new features, Lin sacrifices compatibility of old software. ^ [〇〇〇〇09 Continued development, but in the field of material instruction has not yet shot 'is the condition code readback (conditioncodes read eback) choice {Please read the precautions on the back before filling this page} Pack 4 5 2. Description of the invention (+) 3 = 2 In the multi-modern instruction set, some instructions will instruct the execution logic in the old-fashioned linguistic theory 11 to add the two operands to the provided operands, or Execute on two operands; what is the type of 辑 = 生 ^ Γ 娜 Na, and the result is “Insult” after the operation is performed. And often, the application can be =: = product; the specific attributes of the result, but different Path 1 p 'Right result is-positive number' The job may proceed to the second fruit point 'and if the result is-negative number, the process will proceed to point B. If the right,, and fruit are zero, the process will proceed to point C Because of the boundary conditions (such as negative, positive, zero, overflow, odd π, ,, and capsule) boundary conditions determined by the _ Cheng handle process of Lepidoptera mosquitoes, and change the program's ^ use 66 two 'The most widely used ... And the -4b conditional branch register to store the state of one or more bits to calculate the domain generation-for ship results, each boundary condition in the microprocessor evaluates the corresponding result, and sets the 3 condition exhaustion The corresponding bit in the register is used for subsequent use of conditional branch instructions. [丨] In many modern microprocessors, the result evaluation and condition are performed automatically. Each time a new result is calculated, the condition The status of "stone", "❻" (also known as the flag register) was updated to reflect the printing of A7 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, 583583. V. Invention Description (f) The boundary attributes of this new result. Although This feature is quite useful in many cases, but there are still times when you don't want to update the bar code register once a result is produced. For example, those skilled in the art know, evaluate, boundary conditions, and Update the corresponding condition code bits of each-newly generated result, which is quite complicated and time-consuming work, so that for most microprocessors, σ, each time a result is different, the execution pipeline must be stopped This cycle is based on the evaluation of boundary conditions and related condition code bits. This phenomenon has been pronounced by microprocessor designers and compiler designers ^. Therefore, when-conditional branch instructions (conditions Code user) immediately before an instruction (condition code maker) that establishes a branch condition. In this case, most compilers and some microprocessors will look for ^ or more in the instruction stream. Does not affect the subsequent instructions of the condition code, and inserts these subsequent instructions between the instruction that makes the condition code and the conditional branch instruction, so that the execution of the program can be arranged more efficiently. Tao 2] But those skilled in the art will know Refers to _ inserting people, so the stop of the pipeline operation is often = no: the problem will be more serious when performing repeated program loops. Moreover, if eight conditions have been established, then inserting unnecessary virtual operation instructions (η〇 · ς instruCtlGn) into the field-type wiper has proved to be very unfavorable to the overall execution speed of the Lang program. The new [= 17 '我 倾 _ 是 ， -watch the conditional code update k selective control technology incorporated into the existing microprocessor instruction set architecture, the microprocessor instruction set is completely completed by the defined operations Occupation, and the inclusion of this technology does not affect-the implementation of the old application should be carried out in micro-county counties that meet the old specifications ___ 6 This paper size is applicable _ home standard (CN_S) A4 size coffee χ four II lew — --- (please first Read the notes on the back and fill in this page) Order-583583 583583 V. Inventive (") The ability to use programs. _4] In another case, the programmer may want this 1 cow: as a judgment of whether the subsequent calculation is performed Based on ... "Therefore, during the implementation of the A7 B7 2 order printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs," a set of conditions can be maintained; it is necessary to ==: the r side continues to command the shirt to have previously been set. (3) invention brief Explanation: _5] The present invention, like the other applications mentioned above, addresses the problems and shortcomings of the above and other conventional techniques. The present invention provides a more advanced technology, which expands the micro-processing instruction set beyond the existing capabilities, and carries out programmable control over the update of the job condition code of the resulting result. The present invention provides a microprocessor device for selectively controlling the write-back of condition codes. The microprocessor device has a translation logic and an extended execution translation. The translation logic translates an extended instruction into a corresponding micro instruction. The extended instruction has an extended prefix and an extended prefix code (extended ρΓ ^ χ

tag). This preamble removal can correspond to the write-back of the condition code of the specified operation result. The extended preamble flag indicates the extended preamble. Among them, the extended preamble flag is another operation code specified in the microprocessor instruction set according to the architecture. The extended execution logic is coupled to the translation logic for receiving the corresponding microinstruction, generating the result, and disabling the write-back of the condition code. X

[0016] An object of the present invention is to provide an existing microprocessing

This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) 583583

The write-back control mechanism for adding conditional flags to the device instruction set has an -extend instruction and a translator (10 = delay = order finger not-microprocessing n leftover-writeback of a subset of the sketches). These conditional flags reflect the boundary conditions of the silk, where the result is calculated. The extension instruction includes the code of the existing micro-processing stealth ^ set shot-selection code, which is controlled by the 1-bit extension control-set code. The selection The operation code indicates the extended instruction, and the n-bit control code is difficult to generate the subset. The translator receives the = and generates a " " microinstruction sequence to instruct the microprocessor to execute the operation difference. It also instructs the write-back control logic to exclude the write-back of the sub-set after the result is generated. [0017] Another object of the present invention is to propose a condition code return for adding selectivity to an existing microprocessor instruction set. Instruction set extension module for writing ability. The instruction set extension module has-escape mark (bundling tons), a condition code write-back designated element (eGdeswritebaekspedfier), and-condition code write-back controller (conditioncodes read ebackc〇Ca Uer). The Ministry of Economy It is not printed by the Consumer Cooperatives of the Property Bureau. It has been received by Zhunze Logic and pointed out that the accompanying part of a corresponding instruction specifies-the microprocessor to perform-extended operations, where the escape mark is the existing micro The first-opcode item in the processor's instruction set. The condition code is written back & the element handle is connected to the escape tag 'and is one of the accompanying parts', the number of the specified plural side-associated Weiyan materials is calculated. Condition code. The condition code writeback ㈣ϋ to the translation logic uses the writeback of the condition codes to enable the writeback of the remaining condition codes. [0018] The re-objective of the present invention is to provide an extension Microprocessing 8

583583

Description of the Invention (The method of the device instruction set to provide can be provided, the method includes providing-extended instructions, the extension wr package extension = two you Yunqi, write the preamble and the rest of the pro-machine order code Specifying the operation to be performed, the associated association fetch_writeback will be forbidden; execute the operation with i to generate u, and prohibit writeback of the selected condition code. (IV) Illustration of the invention: [0019] The foregoing and other objects, features, and advantages of the present invention can be understood by following the descriptions and descriptions below: [0020] FIG.-Is a block diagram of a butterfly-like microprocessing difficult-to-order format; 0021] Figure 2 is a _ table describing how the instructions in the instruction set architecture correspond to the bit logic states of an 8-bit opcode byte in the instruction format of Figure 1. [0022] Figure 3 is [0023] FIG. 4 is a table showing how the printed features of the consumer cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs correspond to an 8-bit extension front according to the present invention. The logical state of the bits in the code embodiment; [0024 Figure 5 is a block diagram illustrating a pipelined microprocessor used to control condition code updates associated with the results of operations performed by the present invention; [0025] Figure 6 is used to selectively control condition code back according to the present invention A block diagram of a specific embodiment of the extended preamble written; 9 This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) 583583 A7

Description of the Invention (B7 Observation of the details of the series: 1 block diagram Hi figure is the nuance of Figure 5; the internal extension of the execution logic is shown in Figure 8 and Figure 9 is to describe the present invention to provide the condition code write-back control of the heart Operation flow chart of the method for ordering translation and execution. Explanation of drawing number: 100 instruction format 102 operation code 200 8-bit operation code figure 202 operation code ΠΗ 300 extended instruction format 302 operation code 304 extended instruction mark 400 8-bit prefix Code map 500 pipelined microprocessor 502 instruction cache memory / external memory 503 instruction Ning column 505 extended translation logic 507 execution logic 600 extended preamble 602 write back control field 700 translation stage logic 101 103 201 301 303 305 401 501 504 506 508 601 601 Preamble address designation meta opcode value Prema address designation meta extension preamble architecture feature extraction logic translation logic microinstruction queue extension execution logic standby field 701 activation status signal 10 * ·, the Zhang scale is applicable to the Chinese National Standard (CNS) A4 specification (21 × 997 mm 583583

702 machine-specific temporary storage 704 instruction buffer 706 translation controller 708 escape instruction detector 710 instruction decoder 712 micro instruction buffer 714 micro op code field 716 source bit 800 extended execution logic 802 micro instruction register 804 Other bits 806 Condition flag register 808 Result bus 81. Result register 703 Extended feature bit 705 Translation logic 707 Disabling signal extension Preamble calculus horse 711. Control read only Memory 713 operation 礓 extension field 715 purpose 717 displacement 801 operation element register 803 operation code extension 襕 bit 805 operand register condition exhaustion write back controller 809 arithmetic logic unit Γ square ~ 9 The legal code shouts ㈣ 之 LING for translation and execution ------------- install --- (Please read the precautions on the back before filling out this page} Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (5) Detailed description of the invention: [29] The following description is provided in the context of a specific embodiment and its necessary conditions, so that a person skilled in the art can use the invention. However, various The modification of the preferred embodiment is familiar with this technology. This is obvious, and the general principles discussed herein can also be applied to other embodiments. Therefore, the present invention is not limited to the specific embodiments shown and described herein, but has the same features as those disclosed herein. Principle and 11 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 583583 A7

583583 A7 The Intellectual Property Bureau of the Ministry of Economy ’s Employees ’Cooperative publishes a description of the operation (丨 &) operation, and selects (〇Pti〇nal) to specify meta-item 103 after the operation code 102 to specify the specific operation. Additional information, such as how to perform the operation, where the operands are located, and so on. The instruction format just allows the programmer to add a preamble item 101 before-opcode 102. When a specific operation specified by the operation code 102 is performed, the preamble 101 indicates whether to use a specific architectural feature. -In general, these architectural features can be applied to most of the operations specified by any opcode 102 in the instruction set. For example, preamble 101 today exists in some microprocessors that can perform operations using different sized operands (such as 8-bit, 16-bit, 32-bit). And when many of these processors are programmed to a preset operand size (such as 32-bit), 'pre-coded to 101 in their individual instruction set still enables the programmer to follow the instructions To selectively override the preset operand size (for example, to perform a 16-bit operation). The selectable operand size is just one example of architectural features. In many modern microprocessors, these architectural features can be applied to many operations that can be specified by opcode 102 (such as addition, subtraction, multiplication, and Bollinger logic). Wait). [0032] The instruction format 100 shown in FIG. 1 has a well-known example in the industry, this is the x86 instruction format 100, which is used by all modern 6-compatible microprocessors. More specifically, the x86 instruction format 100 (also referred to as the x86 instruction set architecture 100) uses an 8-bit preamble 101, an 8-bit opcode 102, and an 8-bit address designator 103. The χ86 architecture 100 also has several preambles 101, two of which replace the preset address / data size of the x86 microprocessor (that is, opcode states 66H and 67H), and the other instructs the microprocessor to use different Translation rules to interpret the subsequent operation code bytes 13 This paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) {Please read the precautions on the back before filling this page) Binding: 583583 Economy Printed by the Intellectual Property Bureau Employee Consumer Cooperative A7 Invention Description (i)) 102 (that is, the preamble value follows, which makes the translation action based on the so-called two-digit ^ and opcode rules) 'Other preambles 101 Then the special operation is repeated until the repetition condition is satisfied (ie the opcodes: legs, F2H and F3H). [0033] Please refer to FIG. 2, which shows a table 200, which is used to describe how the instruction 201 of an instruction set architecture corresponds to the bit of an 8-bit operation code byte 102 in the instruction format of FIG. 1. Logical state. Table 2000 presents an exemplary 8-bit opcode map 200, which associates up to 256 values of an 8-bit opcode item 102 with the corresponding microprocessor opcode 々201. The table 200 maps a specific value of the different code item IQ), such as 02H, to a corresponding operation code instruction 201 (ie, instruction ι0222). In the example of the x86 opcode diagram, it is well known in the art that the opcode value 14H is mapped to the x86 carry and accumulate (continued evaluation pool Cany, ADC) instruction. This instruction will be an 8-bit direct (丨 from the surface) operation Wu added to the internal value of the structure register AL. Those skilled in this field will also find that the x86 preamble 101 (ie, 66h, 67H, 0FH, F0H, F2H, and F3H) mentioned above is the actual operation code value 201, which is different in different In the context, it is specified that a specific architectural extension is to be applied to the operation specified by the subsequent operation code item 102. For example, adding the preamble 0FH before the opcode 14H (normally, the ADC opcode you describe) will cause the χ86 processor to perform a "decompression and insert low-compression single-precision floating-point value" ( Unpack and Interleave Low Packed Single-Precision Floating-Point Values) operations instead of the original ADC operations. The features described in this X86 example are partially enabled in modern microprocessors. This is due to the small winter ring and also applicable to the Chinese National Standard (CNS) A4 specification (21〇X 297 mm (please read first Note on the back, please fill out this page again) Install 583583 A7 5. Inventory (I 4) The instruction translation / decoding logic in the item processor is to sequentially interpret the items κη-κΒ of an instruction 100. So in the past ' The use of specific math values as a preamble in the instruction set architecture allows the microprocessor designer to incorporate many advanced features into the micro-service design towels of the old software without using those specific The old programs of the state of the operation code bring the negative impact of the execution of the last two. For example, '-the old programs that have not used the χ86 operation code 0FH can still be executed on today's X86 microprocessors. A newer application, By using the full operation code 0FH as the preamble 101, it is possible to use newly incorporated X86 architecture features, such as single instruction multiple data operations, conditional movement operations, etc. [〇〇34] Although it has been available by designation in the past / Excessive opcodes The value plus is used as the preamble 101 (also known as the core feature flag / indicator or escape command = 1) to provide architectural features, but when many instruction fabrics just provide functional enhancements, they will still be very direct The reason for this is to get in the way: all available 7 extra opcode values have been viewed, that is, all opcode values of the opcode graph 200 have been architecturally specified. When all available = values are assigned as the operation outline The code value can be used to incorporate new features when it comes to 10 or preamble items. This serious problem lies in the fact that many microprocessors are now shooting, which forces the design to be compatible with the reserved form. _ / Means that the instruction 201 shown in Figure 2 is general (such as Jin; Li Er ', 124, 186), rather than specifically referring to the actual operation has been reduced Mutually exclusive or). This is because, in some different cases, the fully occupied operation code is around 200 in the structure [____ 15 This paper is applicable to 583583 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Inventory (丨 /) f Includes newer The possibility of progress is ruled out. Although the example in Figure 2 refers to the = bit operation code item 102, those skilled in the art will still notice that the special size of the operation code 102 is a special case to discuss the fully occupied operation code. Beyond the problem caused by the structure, other aspects have nothing to do with the problem itself. Therefore, a fully occupied 6-bit opcode map will have 64 opcodes / preambles that can be architecturally specified and will not provide usable / excessive opcode values for expansion. [0036] Another method is not to discard the original instruction set and replace it with a new grid = 100 and opcode map 200, but only to a part of the existing opcodes. With substitution, the operation code shown in Figure 2 is torn to 4FH. With this hybrid technology, microprocessors that meet the old specifications can be compatible with the old software mode operation, in which the operation code tearing_Ga system still has rules to solve the problem, or to strengthen the mode (touch sister ⑽Karu) Operation, where the operation code 40H_4FH is interpreted in accordance with the enhanced architectural rules. This technology does allow the designer to incorporate new features into the design. However, when the old man's old specifications are enhanced, the shortcomings still exist. ^ It is a fine program for the micro-processing materials to age any side. Therefore, from the standpoint of preserving legacy software compatibility, technology that is compatible with legacy software / enhancement mode is still unacceptable. [0037] However, the instruction code for the operation code space has been completely occupied, and the space covers all applications in accordance with the old specifications of the micro-description; the case of the application 'The inventor of this case has noticed that the operation code The use status of 001 'and they also observed that although some instructions 202 refer to the structured ^', they are not used for application programs that can be processed by microprocessing. Figure 16 Degree · Chinese National Standard (CNS) A4 Regulation ^^^^ (Please read the precautions on the back before filling out this page) 丨 Call 丨 Installation- · Order · 583583 A7 V. Description of the Invention (丨 ί) I — The instruction IF1 202 is an example of this phenomenon. In fact, the same opcode value 202 (ie F1H) is mapped to a valid instruction 202 that is not used in the x86 instruction set architecture. Although the unused χ86 instruction 202 is a valid χ86 instruction 202, which instructs a architecturally specified operation to be performed on a χ86 microprocessor, it is not used in any implementation that can be performed on a modern χ86 microprocessor. application. This special X86 instruction 202 is called InCircuitEmulationBreakpoint (InCircuitEmulationBreakpoint) (that is, ICE BKPT, the operation code value is F1H). It was previously used exclusively in a microprocessor simulation device that no longer exists. ICE BKPT 202 has never been used in applications other than in-circuit simulators, and in-circuit simulation devices that previously used ICEBKpT 202 no longer exist. Therefore, in the circumstances, the present inventor has found a tool within a completely occupied instruction set architecture 200, by using an effective but unused operation code 200 to allow the design of the microprocessor Incorporates advanced architectural features without sacrificing compatibility with legacy software. In a completely occupied instruction set architecture 200, the present invention uses a structurally specified but unused operation code 200 as an index mark to indicate the next n-bit preamble, so Allows the microprocessor to set up a delayer to incorporate up to 2η of the latest developments, including the microprocessor's | ☆ species' while retaining full compatibility with all older software. > [〇〇38] The present invention provides a η-bit condition code write-back control designation | 7L preamble, the concept of replenishment / ㈣ before 钱 when money, so | programmers can-use it Operations performed by the microprocessor (such as addition, subtraction,! Brin operations, operand operations, etc.) are stylized, and within the same instruction, enable / disable the results of performing the custom operation Relevant designated system L_ 17 This paper size is suitable for financial and family care. (Please read the precautions on the back before filling out this page) K-pack ·-583583 Printed by A7, Employees ’Cooperatives, Bureau of Wisdom and Finance, Ministry of Economic Affairs 2. Description of the invention (.) Write-back of condition code (that is, update). In a specific embodiment, the condition code status of the microprocessor is stored in a condition code (or flag) register, which is updated according to the status of the field in the n-bit extended preamble, and the The n-bit extension code disables the update of a conditional code sub-set associated with the result. Another embodiment excludes the write-back of all condition codes associated with the result. The invention will now be discussed with reference to Figs. [0039] Please refer to FIG. 3, which is a block diagram of the extended instruction format 300 of the present invention. It is very similar to the format 100 discussed in Figure 1. The extended instruction format 300 has a variable number of instruction items 301-305, each of which is set to: a specific value 'collected to form a microprocessor-a specific instruction 300 β Hite's heart order 300 instructs the microprocessor to perform a specific operation, such as adding two operands, or moving the -operator from the register to the microprocessor's register. -In general, the operation code item 30 of the 'instruction 300' specifies the specific operation to be performed, and the selected address designation meta-item 3 is located after the operation code 3002 to specify the specific operation. For additional information, such as how to perform the operation, the operand is in the domain section. Instruction format · It also allows the private operator to add a preamble item before -operation code 302. The Shima Project 30m is used to indicate whether to use the existing architectural features when the specific operation specified by the operation is performed. [0040] However, the extended instruction 300 of the present invention is the above-mentioned instruction of Fig. 1 = the superset of Equation 100, which has two additional items and 305, which can be selectively used as instruction extension items and placed in the instruction. All remaining items in the 300 before 3Q3. The two fine-added items 304 and 305 are used to enable / disable the complex 18-degree scale associated with a specified operation result. The Chinese National Standard (CNS) A4 specification (21G χ 297 --------- ---- ^ -------- ^ ---------. < Please read the notes on the back before filling this page) 583583 A7

Equipment ------- (Please read the precautions on the back before filling out this page), and item A-nnnn, 583583 Α7 Β7 V. Description of the invention) ------------- -Install · (Please read the precautions on the back before filling this page) In a specific embodiment, the extended preamble 305 has an octet size, and a maximum of 256 different subsets of the condition codes can be specified. In the embodiment of the meta-preamble, a maximum of 2n different condition code combinations can be specified. [0042] Referring now to FIG. 4, a table 400 shows how a condition code update control extension is mapped to a bit logic state of an 8-bit extended preamble implementation according to the present invention. Similar to the operation code diagram 2qq discussed in FIG. 2, the table 400 in FIG. 4 presents an example of an 8-bit condition code designator before the code diagram 400, which extends an 8-bit preamble item 305 A maximum of 256 values are associated with the corresponding condition code status 401 (such as E34, E4D, etc.) of a microprocessor that meets the old specifications. In a specific embodiment of χ86, the 8-bit extended feature preamble 305 of the present invention is provided for use by designated elements 401 (ie, E00-EFF), and these designated elements 401 are used by the current x86 instruction set architecture. Failed to provide. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs [0043] The extended feature 40m shown in Figure 4 is expressed in a general way, and does not specifically refer to actual features. This is because the technology of the present invention can be applied to various Different architecture extensions 401 and specific instruction set architectures. Those skilled in the art will find that there are many different architectural features 401, some of which have been mentioned above, which can be converted according to the escape mark 3 04 / extended preamble 305 technology described here. Inclusion-Existing instruction set. The 8-bit preamble embodiment of FIG. 4 provides a maximum of 256 different features 4Q1, and the _η-bit preamble embodiment has a stylized selection of up to 2η different features 401. [0044] In the embodiments corresponding to different condition code bridging methods, these types are common to many modern microprocessors, and the combination of condition codes can be designated as prohibiting write-back. Including-This paper size applies the Chinese National Standard (CNS) A4 specification (210 297 meals) 583583 Γ; printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ------2 ________, the boundary of the results of the invention (γ) Attributes, such as equal to zero, not equal to zero, even parity, even parity (0 (jd parity), negative sign (employment), no negative sign, overflow, non-overflow, carry ), No carry, etc. In many such microprocessors, a condition code status item (ie, a register) is configured with a plurality of condition code bits (or flags), where each bit represents Whether a recently produced result has exceeded a certain result boundary condition, such as generating a carry bit, or a sign bit indicating that the result is a negative number. However, the foregoing specific condition code does not limit the scope of the present invention to A specific A condition code set. The foregoing embodiment can be used as an example to explain how a condition code specifies a meta-preamble 305 to be encoded in order to exclude an update of a specific condition code sub-set after a result is generated. Those skilled in the art will perceive that the configuration of a special condition code designation element preamble 305 depends on how a condition code is represented and stored in a corresponding microprocessor. [0045] Please refer to FIG. To illustrate the block diagram of a pipelined microprocessor 500 for controlling condition code updates associated with the results of operations performed by the present invention. The microprocessor 500 has three distinct types of stages: extraction, translation, and execution. Extraction stages With extraction logic 50, instructions can be retrieved from the instruction cache memory 502 or external memory 502. The extracted instructions are sent to the translation stage via the instruction queue 503. The translation stage has translation logic 504, which is coupled to a micro instruction Queue 506. Translation logic 504 includes extended translation logic 505. During the execution phase, there is execution logic 507, which has extended execution logic 508. [0046] According to the present invention, When working, extract logic 501 from instruction 21 This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 public love) --------, ----- install --- (Please read first Note on the back, please fill out this page again) _ 583583 V. Description of the invention $ Take A memory / external memory 5G2 to extract the formatting instructions, and put these instructions: in the order of ^ execution into the instruction symbol 503. Then, the inverse instructions are extracted from the instruction array M3 and sent to the translation logic 504. The translation logic 504 translates each & order & order into a corresponding micro instruction sequence to instruct the micro processor 5 to execute the operations specified by these instructions. According to the present invention, the extended translation logic 505 detects those instructions with extended preamble flags to perform translation / decoding of the specified meta-prefixes in accordance with conditional writing. In the actual example of -x86, the extended translation logic 505 is configured to translate its value to the corresponding extended preamble mark, which is the ICE κκρτ operation code. The microinstruction field is provided in the microinstruction column 5506 to specify the condition code to be excluded from updating. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs [0047] Microinstructions are sent from the microinstruction queue 506 to the execution logic 507, and the extended execution logic 508 detects microinstructions with selective condition code write-back features The write-back feature here refers to the month b according to the instruction of the micro instruction niches. The extended execution logic 508 executes the operation specified by the microinstruction and produces a corresponding result. After the corresponding result is generated, the extended execution logic 508, which is the evaluation of the disabling boundary condition according to the instruction of the micro instruction block, and the update of the condition code. In a specific embodiment, only the condition code specified by the extended instruction to be updated will be written back to the condition code register. In another embodiment, only condition codes that are not specified by the extended instruction as not to be updated are written back to the condition code register. [0048] Those skilled in the art will find that the microprocessor 500 shown in FIG. 5 is a simplified result of the modern pipelined microprocessor 50. In fact, a modern pipelined microprocessor 500 may contain up to 20 to 30 different pipeline stages. However, these stages can be broadly categorized as squares. ^ 22 This paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) " ----- Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 583583 A7 -------B7 Fifth, the three stages shown in the description of the invention (> >), therefore, the block diagram 500 of FIG. 5 can be used to point out the necessary elements required for the embodiment of the present invention. For brevity, unrelated components in the microprocessor 500 are not shown. [0049] Please refer to FIG. 6, which is a block diagram of a specific embodiment of an extended preamble for selectively controlling writeback of a condition code according to the present invention. The extension condition code designation element preamble 600 is an 8-bit extended preamble 600, and has a write-back control (a pool back contrd 'including a plurality of bits (starting at bit 0)). wbc) field 602 and a spare field 601 containing the remaining bits (ending at bit 7). In a specific embodiment, the wbc block 602 includes bit 0, and according to the instruction of the present invention, the extended execution logic disables the write-back of all condition codes. Another specific implementation side uses the lower five bits of the preamble 600 as the WBC bit 602, where each bit corresponds to a negative sign prohibition condition, a carry condition, an overflow condition, and a zero value condition, respectively. And write-back of parity conditions. [0050] Please refer to FIG. 7, which is a detailed block diagram of the translation stage logic 700 in the microprocessor of FIG. 5. The translation stage logic 700 has an instruction buffer 704, which according to the present invention provides extended instructions to the translation logic 705. Then, the logic 705 handle is connected to a machine-specific register 702 with an extended feature booth 703. The translation logic 705 has a translation controller 706, which provides a disabling signal 707 to an escape instruction detector 708 and an extended preamble decoder 709. The escape instruction debt tester 708 is connected to the extended preamble decoding $ 709 and an instruction calculus horse training. Extended preamble decoder 709 and instruction decoding logic 71. Access to a control read-only memory (ROM) 711, which stores a pattern corresponding to some extended instructions --II — I * — III ----- --I ^ — — — — — — — II ^^ 1. (Please read the precautions on the back before filling out this page) 23 583583 A7 、 Instructions of the invention (4) Micro instruction sequence of the board (te_ate). The translation logic 705 φ includes a microinstruction buffer m ′ which has an opcode extension term claw, a microop field 7U, a destination block 715, a source bit 716, and a bit 7. [〇 Gang operation, during the start-up of the microprocessor, the state of the extended field 703 in the specific register of the machine is determined by the signal activation state a (n)) 7 (31 to indicate the specific micro-processing) If no, transfer to n lines of the extended condition execution instruction of the present invention. In a 701m signal 701 from a feature control register (not shown on the picture;) * out 'the feature control register is read-added to the silk array ― (Not shown). The status of the machine-specific temporary extension feature stop 703 is sent to the translation controller 鄕. = 制 ^ == 令: Puncher 7.4 Extraction and selection of raw materials and writing conditions control translation Providing such control features can allow supervised programs (such as BI⑹ extension_signs. If the extension feature is disabled, the operation with the mark selected as the extension feature is only used.) Dirty, the translation is performed. A specific x86 == No: The instruction is abnormal (exeeptlGn). _ ”Come. The escape instruction _7708 therefore specifies the extension condition code after the translation / decoding mark is detected to specify the decoder's operation. / Explanation 22 is applicable to China Please read the selection of the back body Then calculate the F1H translation items

I I I I I Order 583583 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. When the description of the invention (χψ) 'enables the instruction decoder 710. Certain specific instructions will cause access to control ROM 711 to obtain the corresponding microinstruction sequence template. The different code extension item field 713 of the microinstruction buffer 712 is grouped by the preamble decoder 709 to specify a subset of the plurality of condition codes, wherein the update of the condition codes is a corresponding operation. The result is enabled / disabled after the result. The other buffer fields 714-717 specify the corresponding operation, and the instruction decoder 710 performs group operations. The configured micro-instruction 712 is sent to a micro-instruction string (not shown in the figure) for subsequent execution by the processor. [0052] Please refer to FIG. 8, which is a block diagram of the extended execution logic 800 in the microprocessor of FIG. 5. The extended execution logic 800 has an arithmetic logic unit (ALU) 809, which is coupled to a condition code write-back controller 807 via a result bus 808. The condition code write-back controller 807 is coupled to a condition flag storage mechanism 806, or a condition flag temporary register 806. The two operands 0PERAND 丨 and 〇pERAND 2 are extracted by the ALU 809 from the operation 70 registers 801 and 805. A micro-instruction register 802 provides a micro-instruction to the ALU 809 and the condition code write-back control logic 807. The micro-instruction register 802 has an operation code extension entry block 803 and a remaining field 804. ALU809 is also connected to a result register 81Q. [0053] In operation, when an extended instruction using the selective condition code write-back control feature is translated into a micro instruction sequence according to the present invention, the extended micro instruction and the available operands in the registers 801 and 805 are both Via the micro-instruction register 802, it is sent to the extended execution logic_. The operation code extension item slot 803 specifies a subset of a plurality of condition codes, and the update of the condition codes corresponds to that specified by the remaining field 804 using the operand g0i ------ --------— (Please read the notes on the back before filling out this page) Order ·.--II. 25 583583 A7

583583 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Invention Description (Required)

The state is to point out that the ancient process of the condition codes specified by the extended preamble then proceeds to block 912 〇 / 口 H _ί in block 912, the rest of the instruction (such as the preamble item, transport different code, Address designation 疋) is translated / decoded to the properties of the operations and associated operations required by Jing. The flow then proceeds to block rule. = 〇] In block 9, the remaining positions of a sequence of microinstructions are grouped into the operation specified by Cai Yue and its operation S attribute. Flow block 910 〇 Neighbor] In = block training, the micro instruction sequence, which contains the opcode extension field configured in block _ and the remaining fields of the group of sounds set in block 9M, is sent to the -micro instruction The list of items is executed by the microprocessor and then proceeds to block 918. [0062] In block 918, the microinstruction sequence is extracted by the extended conditional execution logic of the present invention. The flow then proceeds to block 92. , _3] Execute the logic in the box 运算 to execute the specified operation and produce the result. The flow then proceeds to the judgment block. In the judgment block, the condition code two innovations exclude the boundary condition evaluation and condition code update of the sub-set. The sub-set in 1 is extended by microinstructions and is located in the block. The excluded subset flows to block 926. For the remaining condition codes that are not evaluated / updated, the flow proceeds to block 924. [0065] In block 924, the result is evaluated, and the corresponding bits of the condition code register are updated according to the remaining condition codes, and proceed to block 926. τ 27 The paper ruler does not take into account the Chinese national standard (cns) A4 specification (2ig χ 297 public love "(Please read the precautions on the back before filling this page)

LSJ 583583 A7 V. Description of the invention (> 7) [0066] At block 926, the method is completed. [_7] The present invention and its objects, features, and advantages have been summarized in detail, and other practical supplements may also be included in the scope of the present invention. For example, the present invention has been described in terms of the following techniques: • The use of the fully-occupied finger a set of framework-single-, unused opcode status as a mark to refer to the following extended feature preamble 6 but this In any aspect, the scope of the invention is not limited to the complete instruction structure, the instruction, or the single-marker. On the contrary, the present invention encompasses incompletely mapped instruction sets, embodiments with used opcodes, and embodiments that flag more than one instruction. For example, 'consider-there is no instruction set architecture that does not render the state of Saki. A specific embodiment of the present invention includes selecting an operation code state as an escape mark ', wherein the selection criterion is determined according to market factors. Another implementation includes the use of arithmetic breaks—special combinations as markers, such as ambiguity in the state of arithmetic codes. The essence of Benjamin lies in the use of the -tag sequence 'followed by an n-bit extended preamble, which allows the programmer to enable / disable the execution result of the operation specified by the rest of the -extended instruction. Evaluation and update of related condition codes. [0068] Furthermore, the present invention has been exemplified by a microprocessor having a set of condition codes or flags, the set of condition codes indicating a boundary condition of a result, including parity, overflow, sign and zero. Although these types of conditions are still widely used today, the invention is not limited to application to these types of conditions. For example, other embodiments of the present invention include other specified conditions, such as the status of a special register content, whether a communication card or other I / O device uses a towel, whether there is a shapeable memory or a cache. Paper scale towels, family standard, standard coffee, χ Norwegian, ^ __- ^ —---------- Aw > Μ — (Please read the notes on the back before filling this page) Order: Intellectual Property Bureau, Ministry of Economic Affairs Printed by employee consumer cooperatives 583583 A7 V. Description of invention (β) Memory space and so on. [0069] Furthermore, although the above uses the microprocessor as an example to explain the present invention and its objects, features, and advantages, those skilled in the art can still perceive that the scope of the present invention is not limited to the microprocessor _, And can cover all forms of expected scales, such as Xunweili H's industrial controller, array processor and other similar devices. Where: The above is only a preferred embodiment of the present invention, and the scope of implementation of the present invention is not limited. All the specialization and materials made by the applicant for the application of the present invention should still fall within the scope of the patent cover of the present invention. I would like to ask your review committee members in May and pray for your approval. f ------- I ---- Order · ---- I --- (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 29

Claims (1)

583583 A8 B8 C8 D8 2. 3. Scope of patent application-A microprocessor device for selectively controlling the writing back of a plurality of condition codes, including: a translation logic for translating an extended instruction into the corresponding A micro instruction, wherein the extended instruction includes: an extension such as a code, which is used to disable write-back of the condition codes, the condition codes corresponding to a result of a specified operation; and an extended preamble mark, which is used to: Point out the extended preamble, where the extended preamble mark is another operation code specified by the architecture in a microprocessor instruction set; and-extended execution logic, connected to the translation logic 'to receive the corresponding The micro-instruction 'generates the result' and disables the write-back of the condition codes. The microprocessor device described in item 1 of the scope of the patent application, the extended instruction further includes a plurality of items specified by the instruction set according to the architecture / . As described in claim 2 of the microprocessing II device of the scope of the patent, the items determined by the 1-na architecture include an opcode item using == the specified operation. μ 4. The microprocessor device as described in the scope of the patent application, wherein the extended f code includes a plurality of bits, and it causes each logical state of the bits to indicate that the microprocessor will The write-back of one of the sub-sets of the result condition is disabled, and the condition code includes a special sub-set of the female result condition. 5. The micro-processing device as described in the fourth item of the patent application of the W patent, wherein the result conditions include overflow, carry, miscellaneous, negative ribs and parity ^ ____ _ JU This paper standard applies to Chinese national standards (" Μ4 specification (21G x 297) £ -------- 1 ----- AWI -------- ^ ---------. (Please read the precautions on the back first (Fill in this page again) A8 B8 C8 D8, patent application scope 6. The microprocessor device described in item 5 of the patent application scope, wherein the result conditions are stored in a flag register of the microprocessor 7. The microprocessor device according to item 1 of the scope of the patent application, wherein the extended preamble contains 8 bits. 8. The micro-service device according to item 1 of the patent claim, wherein the The instruction set contains the x86 instruction set. • The microprocessor device as described in item 8 of the patent application scope, wherein the extension is shown as a code, and contains the operation code F1 (ICEBKpT) of the X86 instruction set. 10 · If applying for a patent The microprocessor device described in item i of the scope, wherein the corresponding microinstruction includes a micro-op field and a micro-op extension field. The microprocessor device described in Item 10, wherein the extension execution logic uses the micro-operation code extension field to determine the silk code to be returned, and wherein the extension execution logic uses the The micro-f exhaustion determines the specified operation performed by Wei Xian to produce the result. = Declaration of the patent | & The micro-processing device described in item 11, wherein the extended execution logic includes: condition code write-back control H, The field is produced as a result of a plurality of operation results ^ 'Update-condition code register, and is configured to exclude the write-back of those condition codes as the result is generated. 13, = ffm described in item 1 The microprocessor device, wherein the transfer # logic includes: — escape instruction detection logic for detecting the extended preamble mark; (please read the precautions on the back before filling this page) to install the wisdom of the Ministry of Economic Affairs Printed by the Property Agency Staff Consumer Cooperative 583583 583583 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 B8 C8 D8 6. Scope of Patent Application • Other extended instruction items are configured to specify the specified operation. 17. The extension mechanism as described in item 16 of the scope of patent application, wherein the other Yanxianling project Wei Zhaoxian has an existing micro-news order structure. 18 · = Please refer to the extension of the patent, where the condition flags include overflow, carry, equal to zero, negative sign, and parity. 19. The extension mechanism according to item 15 of the scope of patent application, wherein the ^ bit extension control preamble includes 8 bits. The processing instruction set is the x86 microprocessor instruction set. The extended operation code described in item 20 of the scope of patent application includes ICEB ^ m (that is, operation code F1) in the microprocessor instruction set. ^ ^ The extension mechanism described in item 15 of the scope of 22tr patent, wherein the translator is a data watch, the selected m-coded decoder '_ to the escape instruction detector, and is used for 隼 ^ ㈣' And generate the persuasion "in-sequence—micro-operation code extension term 23.” that specifies the subset port—a kind of addition to an existing microprocessor instruction set. Capability instruction set extension module, the condition code is back to ^ bar: the code is written back. The escape mark is used to eliminate those conditions that can be dared to write ^ 70 to write back to the exhausted. Contains: Write 'and enable the remaining 33 private paper ruler MUSIC National Standard (CNS) A4 specifications (210 X 297 male f ^ ^ IIAWI --- (Please read the precautions on the back before filling this page) Order: 4 583583 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the escape mark is received by the translation logic, and it is stated that the manufacturing instruction = specified by the system is one of the extended operations to be performed by the micro processor, and the escape mark One of the first opcode items in the existing microprocessor instruction set; Bayi = code write-back designation element, the escape tag, and multiple condition code towel associations for the ribs attached At the end of the extended operation; and a conditional horseback write controller, coupled to the translation logic, to disable the writeback of condition codes associated with the extended result, and enable the remaining condition codes Write back. 4. The instruction set extension module as described in item 23 of the patent scope of claim π, wherein the rest of the attached Ik part includes a second opcode item and a plurality of optional address designation meta items. 25. According to the instruction set extension module described in item 23 of the scope of patent application, the condition code in the basin writes back the specified element including an 8-bit data item. ^ " 26. If you apply for 23 items of Lai Zhiling's Secret Group, the existing microprocessor instruction set is the x86 microprocessor instruction set. 27. The instruction set extension module described in item 26 of the scope of patent application, wherein the first opcode item includes an IC £ BKPT opcode item (ie, opcode π) in the x86 microprocessor instruction set. 2 8 · The instruction set extension module described in item 23 of the scope of patent application, wherein the translation logic translates the escape mark and the accompanying part into corresponding micro instructions, and the corresponding micro instruction indicates an extension Execute logic to perform stretching operations. --- hill · ---- ·· -install --- (Please read the precautions on the back before filling out this page} · 34 88899 ABCD V Application for Patent Scope 29. Instructions as described in Item 23 of Patent Application Scope An extension module, wherein the translation logic includes:-escape tag detection logic, which detects the escape tag and instructs the accompanying part to perform translation operations in accordance with extended translation conventions; and page-one decoding logic , Reduced to the escape tag _ logic to execute the translation action of the microprocessor instruction according to the routine of the non-microprocessor command set, and execute the translation of the corresponding instruction according to the extended translation routine to allow the The conditional write-back of these condition codes. 2 = —the prostitutes with a small amount of age, stylized tons of fruit ... The condition code write-back capability, the method includes ... providing an extended t instruction, the extended instruction includes-extended Tag and conditional code, where the extended tag is one of the first operation codes of the microprocessor instruction set; I m through 3 pounds = code write-back preamble and the rest of the extended instruction refers to the operation, which makes _Selection condition code for base operation result Write back will be prohibited; and, execute 2 different to produce the result, and prohibit the exhaustion of the selection conditions. 31 hit the method described in = calculation = package item r, which causes the specified action to be performed. Using the microprocessor 32. As described in the application of her slaves in item G, I provided an extension of the paper rule Lai Choi (210x 297 J7 " system of patent application order actions including the use of 8-bit size return Write the preamble to configure. Saki this article 33. The method described in item 30 of the scope of patent application, the action of taking the lease = includes selecting the first 3 "^ from the x86 microprocessor instruction set The application refers to the method described in item%, wherein the action of selecting the first operation code includes selecting the _ICE Βκρτ operation code (that is, operation code F0 as the extension mark.) The method further includes: extending the delay to make micro instructions, J 4 shows-extending the execution logic to stop the return of the selection condition code 36. If the action of the 35th order in the scope of the patent application includes the ... The extension of translation is to detect in a translation logic. Extension tag; and decoding the condition-specified meta-prefix and the extension two-knife according to the extension translation rule. The extension translation rule is-the existing microprocessing structure is provided for programmable write-back control that cannot be provided by the translation rule. ability.