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TWI351082B - Method for fabricating chip package - Google Patents

Method for fabricating chip package

Info

Publication number
TWI351082B
TWI351082B TW096117886A TW96117886A TWI351082B TW I351082 B TWI351082 B TW I351082B TW 096117886 A TW096117886 A TW 096117886A TW 96117886 A TW96117886 A TW 96117886A TW I351082 B TWI351082 B TW I351082B
Authority
TW
Taiwan
Prior art keywords
chip package
fabricating chip
fabricating
package
chip
Prior art date
Application number
TW096117886A
Other languages
Chinese (zh)
Other versions
TW200744174A (en
Inventor
Mou Shiung Lin
Jin Yuan Lee
Original Assignee
Megica Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Megica Corp filed Critical Megica Corp
Publication of TW200744174A publication Critical patent/TW200744174A/en
Application granted granted Critical
Publication of TWI351082B publication Critical patent/TWI351082B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)
TW096117886A 2006-05-18 2007-05-18 Method for fabricating chip package TWI351082B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US80106706P 2006-05-18 2006-05-18

Publications (2)

Publication Number Publication Date
TW200744174A TW200744174A (en) 2007-12-01
TWI351082B true TWI351082B (en) 2011-10-21

Family

ID=55855970

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096117886A TWI351082B (en) 2006-05-18 2007-05-18 Method for fabricating chip package

Country Status (1)

Country Link
TW (1) TWI351082B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10366941B2 (en) 2017-02-21 2019-07-30 Winbond Electronics Corp. Package structure

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101255954B1 (en) 2011-12-22 2013-04-23 삼성전기주식회사 Printed circuit board and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10366941B2 (en) 2017-02-21 2019-07-30 Winbond Electronics Corp. Package structure

Also Published As

Publication number Publication date
TW200744174A (en) 2007-12-01

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees