TWI325695B - Phase-frequency detector capable of reducing dead-zone range - Google Patents

Description

1325695 - IX. Description of the invention: • Technical field to which the invention pertains The invention relates to a phase frequency detector, and more particularly to a phase frequency detector capable of reducing the dead zone range. [Prior Art] In the prior art phase lock (loop, PLL) architecture, a phase-frequency detector (PFD) is mainly used to detect an input signal and a feedback signal, respectively. The phase and frequency difference between the two, according to the result of the phase frequency detector detection, by a charge pump, a loop filter and a voltage-controlled oscillator (VCO) To adjust the operation in the phase-locked loop circuit until the frequency and phase of the feedback signal match the input signal as jil. Please refer to FIG. 1 , which is a functional block diagram of a phase locked loop 1 先前 in the prior art. The phase locked loop 100 includes a phase frequency detector U0, an electric prayer pump 120, a loop filter Go, a voltage controlled oscillator 14A, and a frequency divider 150. The phase frequency detector 110 detects the difference in frequency and phase between the clock signals F1N and Fref, and generates a corresponding output clock signal up & output the clock signal D〇WN to determine whether it is necessary to forward or Adjust the phase of the clock signal Fref backwards. Next, the electric Heli 120 according to the output clock signal up and the output clock signal to 1325695:: generate corresponding control current signal to the loop filter 130, the circuit chopping device " then according to the control current signal generation phase Corresponding control voltage signal to - voltage controlled oscillator 14 〇, finally voltage controlled oscillator M0 generates corresponding output clock signal 'τ according to the control signal. At the same time, the output clock signal is also fed back to the phase frequency (four) detector 110 through the frequency divider 150. The frequency divider 150 generates the clock signal FREF according to the output clock signal F〇, so that the output clock signal F0UT and the clock are output. The frequency of the signal Fref has a multiple relationship. Thus, the phase-locked loop 100 can adjust the phase of the clock signal F through the feedback until the frequency and phase of the clock signal F|N and the clock signal Fref match. With the increase in the application of the south frequency, the function of the phase-locked loop needs to be improved. Please refer to Figure 2, which is the output signal diagram of the phase frequency accumulator of the prior art. In Fig. 2, the vertical axis represents the average value of the output signal of the phase frequency detector (that is, the output clock signal U p and the rounded pulse signal d 〇 平均值 average). The axis represents the phase difference Δ〇 between the clock signal 'and the clock signal ^. In the ideal case as shown in Fig. 2, the DC voltage level of the output signal average of the phase frequency detector is proportional to the phase difference ΔΦ. However, when the phase frequency detector actually operates, there are two undesirable output areas: (d) (dead_zQne) and dead zone (10). The dead zone occurs when the phase difference ΔΦ between the pulse signal fin and the clock signal Fref is small, because the rising edge of the signal of the clock signal and the clock signal FREF is too close, so that the output clock 1325695 signal is UP. And the output clock signal D0WN is not enough to the level difference, so the charge signal (4) and the voltage signal generated by the circuit 会 will be smaller, so that the phase frequency _ _ _ _ _ _ _ _ _ _ _ _ _ _ The phase difference Δ Φ between the pulse signals ^. The blind spot occurred at the time of the pulse signal Fin and the clock signal? The difference ΔΦ of _ is 2; when the multiple of τ is used, the reset of the phase resolver and the time of the rising edge of the signal of the next cycle are very close, so that the phase frequency cannot correctly determine the value of the phase difference Δφ. A good phase frequency detector not only reduces the range of dead zones and dead zones, but also uses fewer active components to reduce the noise of the phase-locked loop. Referring to Figure 3, it is a functional block diagram of a phase frequency detector 3 using a flip-flop in the prior art. The phase frequency prescaler 300 includes two RS flip-flops 31〇, 32〇 and an AND gate 33〇cRS flip-flops 31〇 and 320 for edge triggering (edge_trigger), • when its R terminal and s terminal are received When the signal is on the rising edge, its Q end will produce a corresponding output. The S terminals of the RS flip-flops 310 and 320 respectively receive the clock signal F1N and the clock signal Fref, the r-ends of the RS flip-flops 31 and 32, and the reset signals generated by the gate 330, the RS flip-flops 310 and 320, · The Q of the phase frequency detector 300 generates two output clock signals up and DOWN, respectively.凊 Refer to Fig. 4' which is a schematic diagram of the phase frequency detector 3〇〇 1325695 in the prior art: =).相靖=:(1) Turning out the clock signal to turn out the clock signal logic potential m (four) bit (logic g); (2) output clock signal w with low == signal d_ with high logic. series potential (logic) :

DcZl W has a high logic potential, while the output clock signal DO WN has a low logic potential. The number is _N and the low snow 2 (10) and the output pulse F white low logic potential (logic 〇), once _ to the clock signal I edge, 'will jump to another state' When outputting ^ ^ logic potential ' and outputting the clock signal plus Jane = bit, when the object detects the rising edge of the signal of the clock signal F, it will jump back to the original state, that is, output the clock signal - UP and output When the ^ number DOWN has a low logic potential. When the output clock signal is captured, the pulse signal DO has a low logic potential (logic 〇). Once the signal of the _ ^ signal Fref rises, it will jump to another state, and the output pulse signal will be low. Logic potential, and the output clock signal • OWN has a high logic potential (logic 丨). If the rising edge of the = sign is detected, it will jump back to the original state, that is, output the pulse signal UP and output. The clock signal D〇WN has a low logic potential. , α refers to Fig. 5' which is a circuit diagram of the prior art-phase frequency detector 5〇〇. The phase frequency detector includes two pulse generators 512 and a cut 'two-lock circuit 514 and a reset control circuit, and inverters 51, 52. The first and second input terminals 1325695 of the phase frequency detector 5 receive the clock signal f1n and the clock signal fref, respectively, and generate output clock signals at the first and the first " UP and output clock signal DOWN. The flash lock circuits 514 and 524 each include a reverse 53, 54 and a reverse cry 55, 56 'the input and output of the inverter 53 are respectively connected to the output and input of the inverter 54 respectively, the inverter The input and output of 55 are coupled to the output and input of inverter 56, respectively, such that latch circuits 514 # and 524 can provide a high logic potential or a low logic potential (logic 1 or logic 0) at their outputs. ). _ Reset control circuit 510 includes two P-type MOS transistors (P-type)

Metal-oxide semiconductor transistor * PMOS transistor) TRESET, N-type metal-oxide semiconductor transistor ('NMOS transistor) Tlso, NAND gate 50, and reverse 57, 58. When the outputs of latch circuits $14 and 524 have a low logic potential, transistor Tiso is turned off, causing latch circuits 514 and 524 to be electrically separated from pulse generators 512 and 522, respectively. The two input terminals of the anti-gate 50 are coupled to the outputs of the latch circuits 514 and 524 through inverters 57 and 58, respectively, and the gates of the latch circuits 514 and 524' have low logic potentials. 50 will send a reset signal FRESEt at its output to turn on (make short) the transistor TrEset, so that the outputs of the flash lock circuits 514 and 524 are reset to have a high logic potential. 1325695. Pulse generators 512 and 522 each comprise two N-type gold oxide semi-transistors

Tstart and TSTOP' and inverters 59 and 60, respectively. The gates of the transistors Tstart of the pulse generators 512 and 522 are respectively coupled to the first and second inputs of the phase frequency detector 500, and the gates of the transistors TST0P of the pulse generators 512 and 522 are respectively transmitted through the opposite The transmitters 59 and 60 are coupled to the first and second inputs of the phase frequency detector 500 to detect the clock signal Fin and the clock signal Fref. Since the inverters 59 and 60 are connected between the gates of the transistor and the gate of Tstop, a signal delay can be provided to control the clock signals generated by the pulse generators 512 and 522, respectively. The phase frequency detector 5 of the prior art provides a signal delay by an inverter to control the clock signal generated by the pulse generator: to achieve the two-state operation as shown in Fig. 4. However, the internal characteristics of each inverter are not the same', and the characteristics may deviate from the predetermined value due to process factors, so that the phase frequency detector cannot operate effectively. SUMMARY OF THE INVENTION The present invention provides a phase reset control circuit that can reduce the dead zone range of another architecture, and a first pulse generated by the first pulse output H input terminal is generated at the first and second output ends thereof. Corresponding output signal, the phase: the frequency detector comprises a first flash lock circuit, a second flash lock circuit, and a second pulse generator

lJZDO^J; a first reverse circuit, a first - _, and a Hth first-reverse circuit, a -th sense element, to • the first sense 70 pieces 0 the first latch lightning eve第一 The first output of a frequency detector. The second question lock (4) = Γ: the second output end of the detector, the second end of the second flash lock circuit of the first spear of the control circuit and the phase frequency detection should be the first end And correspondingly generating corresponding signals according to the phase frequency detector to the second end of the first and the _* paths respectively. The first pulse generator includes - the first round

The input terminal is connected to the first phase of the phase frequency detector - the second terminal J = '· and the output terminal is consumed by the second end of the first (four) circuit; the second pulse generator includes - - The input terminal, _ in the second round of the phase frequency detector. The first hand is connected to the first and the output of the second circuit, and is turned to the first end of the battery. The first-inverting circuit includes a round-ended end that is connected to the first input end of the phase frequency detector; and a round. the output end is consumed by the first-pulse generator, and the second input end. The second input circuit is connected to the second input end of the phase frequency detector, and the output terminal is coupled to the second output of the second pulse generator. The sensing component includes a first end coupled to the first pulse and a second input end of the benefit; the second end is secretive to the first reverse circuit; and the control end is lightly coupled to the first The second end of the shackle circuit. The second sensing 7L component includes a first end 'being pure to the second input end of the second pulse generator'. The second end is lightly connected to the second reverse circuit; and a control end coupled At a second end of the second latch circuit.

12 1325695 -. [Embodiment] - The present invention provides another architecture for reducing the deadband range of phase frequency detectors. Please refer to FIG. 6, which is a circuit diagram of a phase frequency detection state 600 in the present invention. The phase frequency detector 6A includes two pulse generators 612 and 622, two latch circuits 614 and 624, two reverse circuits 616 and 626, two sensing elements 618 and 628, and a reset control circuit 61. The first and second input terminals of the phase frequency price measurement 1 600 receive the clock signal IN and the clock signal Fref, respectively, and generate the output clock signal UP and the output clock at the first and second outputs respectively. Signal down. First, the detailed structure of each circuit in the phase frequency detector 600 will be described. In the phase frequency detector 600, the reverse circuits 616 and 626 can be a complementary metal oxide semiconductor transistor (CMOS transist〇r) structure, which can be respectively • a p-type The gold oxide semi-transistor and an N-type gold oxide semi-transistor are composed. In the reverse circuit 616, its transistor D? The gate of the transistor Tn is coupled to the input terminal of the reverse circuit 616, and the input end of the reverse circuit 616 is coupled to the first input of the phase frequency detector 6 to detect the pulse. No. Fin, according to the clock signal Fin, the transistor TP and the transistor n of the reverse circuit 616' can be turned on or off. In addition, the transistors of the inverter circuit 61 and the transistors are coupled to a predetermined potential (eg, coupled to a positive potential and a ground potential, respectively), and the drain is transmitted through the sensing element 618. Connected to each other 1325695, connected. Similarly, in the reverse circuit 626, the gates of the transistor ΤΡ' and the transistor ΤΝ' are coupled to each other as an input terminal of the reverse circuit 626, and the input terminal of the reverse circuit 626 is coupled to the phase frequency Detector. The second input terminal of the detector 600 can turn on or off the transistor TP' and the transistor TN' of the inverting circuit 626 according to the clock signal FreF. In addition, the sources of the transistor TP' and the transistor TN' of the inverting circuit 626 are all coupled to a predetermined potential (eg, coupled to a positive potential and a ground potential, respectively), and the drains are mutually consumed by the sensing element 628. Pick up. The outputs of the inverting circuits 616 and 626 are denoted by "A" and "A'" in Fig. 6.

Pulse generators 612 and 622 each comprise two N-type MOS transistors. In the pulse generator 612, the gate of the transistor T START is the first input end of the pulse generator 612, and is coupled to the first input end of the phase frequency detector 600 to receive the clock signal F1N ' and the transistor TstOP The second input of the pulse generator 612 is coupled to the output A of the reverse circuit 616. At the same time, the source of the φ transistor Tstart and the source of the transistor Tstop are mutually connected, and the source of the transistor Tstart is coupled to a predetermined potential (such as a ground potential). The output of the transistor TST0P is the output terminal of the pulse generator 612, which is represented by the ''B'' in Fig. 6. Similarly, in the pulse generator 622, the transistor T START' • the gate is extremely pulsed. The first input end of the generator 622 is coupled to the second input end of the phase frequency detector 660 to receive the clock signal Fref, and the transistor sings the stop pulse to generate the first input of the 622 The terminal 1 is connected to the output terminal A' of the inverting circuit 626. At the same time, the source of the transistor Tstart' and the source and the source of the transistor 1325695 and the body Tstop' are connected to each other, and the source of the transistor Tstart' is connected. To a predetermined potential (such as ground potential), the transistor TST0P' is the output of the pulse generator 622, which is represented by "B'" in Fig. 6. The reset control circuit 610 includes two reset transistors T RESET and RESET, NAND gate 68, and a delay circuit 66. The reset transistors Treset and Treset' may be N-type MOS transistors, the drains of which are respectively coupled to the first of the phase frequency detectors 600. And the second output terminal can separately detect the output time pulse signal UP and output The pulse signal is DOWN, and the source is coupled to a predetermined potential (such as a ground potential). The two inputs of the gate 68 are also coupled to the first and second outputs of the phase frequency detector 600, respectively. The output clock signal UP and the output clock signal DOWN are respectively detected. The delay circuit .66 is coupled between the gates of the two reset transistors and the output of the gate 68, and may include a resistor and capacitor composed of a resistor and a capacitor. The RC delay circuit is connected in series by a plurality of inverters. The first ends of the latch circuits 614 and 624 are respectively coupled to the output terminal B of the pulse generator 612 and the pulse generator 612. The output terminal B' is coupled to the first and second output ends of the phase frequency detector 600, and the latch circuits 614 and 624 can detect the power according to the first end and the second end. The /bit is maintained in a predetermined operational state. In this embodiment, the latch circuits 614 and 624 each include inverters 61, 62 and inverters 63, 64, the input and output of which are respectively surfaced The output of the inverter 62 and the input 1325695 - terminal, the input and output of the inverter 63 are respectively consumed At the output and input of the inverter 64, the latch circuits 614 and 624 can be maintained in a predetermined operational state. For example, when the latch circuits 614 and 624 are maintained in a first operational state, their first The terminal has a high logic potential and the second terminal has a low logic potential; when the latch circuits 614 and 624 are maintained in a second operational state, the first terminal has a low logic potential and the second terminal has a high logic potential The sensing elements 618 and 628 each include a transistor TSENSE and a transistor Lu TseNSE' 'Optical TresET and a transistor TSENSE' may be P-type MOS transistors, the gates of which are coupled to the pulse generator 612, respectively. The output terminal B and the output terminal B' of the pulse generator 622 are respectively coupled to the second outputs of the pulse generators 612 and 622, and the drains are coupled to the reverse circuits 616 and 626, respectively. Next, the operation of the phase frequency detector 600 will be described. In the initial state _, the output clock signal UP and the output clock signal DOWN of the phase frequency detector 600 have a low potential at the same time, and the output terminal B of the pulse generator 612 and the output terminal B' of the pulse generator 622 are both With high potential. When the pulse signal Fin is positively triggered to a high potential, the transistor TP of the reverse circuit 616 is turned off, and the transistor Τν is turned on. At this time, the transistor Tstart and the transistor TsTOP are simultaneously turned on, and the transistor is turned on. The TsENSE is still off, so the potential at the output B of the pulse generator 612 is gradually pulled low through the conducting transistor Tstart and the transistor TST0P. When the output of the reverse circuit 616 is A and

16 1325695 - When the potential difference between the output terminals B of the pulse generator 612 is greater than the threshold voltage of the transistor • TsENSEE, the transistor TsENSE will be turned on. [At this time, the potential of the output terminal A of the circuit 616 is transmitted through the conducting transistor Tsense. And the transistor Tn is gradually pulled low' to turn off the transistor Tstop. At this time, the potential of the output terminal B of the pulse generator 612 is no longer affected by the clock signal FIN. When the first end of the latch circuit 614 detects the low potential of the output terminal B, it will send a high logic at the second end. The output of the potential pulse signal is UP. Similarly, when the pulse signal Fref is positively triggered to a high potential, the electromorphic Tp' of the reverse circuit 626 is turned off and the transistor Tn' is turned on. At this time, the transistor T START' and the transistor tST0P' At the same time, the transistor tsense' is still turned off, so the potential of the output terminal B' of the pulse generator 622 is gradually pulled down through the turned-on transistor Tstart' and the transistor Tstop. When the potential difference between the output terminal A' of the inverting circuit 626 and the output terminal B' of the pulse generator 622 is greater than the threshold voltage of the transistor TsE'NSE', the transistor TsENSE' will be turned on. The potential of the output terminal A' is gradually pulled down by the conducting transistor · Lu Tsense' and the transistor .Tn' to turn off the transistor Tstop'. At this time, the potential of the output terminal B' of the pulse generator 622 is no longer affected by the clock signal Fref. After the first end of the latch circuit 624 detects the low potential of the output terminal B', it will send the device at the second end. High logic potential output clock signal. DOWN. When the output clock signal UP and the output clock signal DOWN have a high logic potential at the same time, the output of the gate 68 will send a reset with a high logic potential 17 1325695 :: signal Freset, reset signal FRESET through the delay circuit 66 Pass to the reset circuit • The gates of the crystal Treset and Treset'. Therefore, the reset transistor D and Treset' will be turned on, and the drain potential will be pulled low. The output clock = ^ UP and the output clock signal D0WN will also be reset to the low logic potential °. When the second end of the latch circuits 614 and 624 respectively detect the output pulse signal up and the output clock signal D0WN with a low logic potential, respectively, the first ends of the latch circuits 6丨4 and 624 are respectively sent out. The signal of the logic potential causes the output terminal b of the pulse generator 612 and the wheel terminals b, _ of the pulse generator 622 to return to a high potential. Please refer to Fig. 7 for a pulse generator 612 of the present invention and a state diagram during operation. State 71 is the initial state of pulse generators 612 and 622. At this time, the output clock signal up and the output clock signal d〇Wn simultaneously have a low potential, and the output of the pulse generator .612 and the pulse generator 之The output terminal B has a high and narrow position. After the positive trigger, the clock signal “• and the clock signal have a high potential, as shown in state 72. Then, the transistor tstart, the transistor TsT〇p, the transistor D·, and the transistor _ , will be turned on, and the output B of the pulse generator 612 and the output B' of the pulse generator 622 will be pulled low to low, as shown in states 73 and 74. The output of the pulse generator 612 b and the output of the pulse generator 622 'B' has a low potential, the transistors tsense and Tsense will be turned on, and the output clock signal UP and the output clock signal D〇WN will be pulled high, the knife Not shown in states 75 and 76. In addition, when the transistor Dense sense and Tsense, 1325695 - turn on, the transistors τ STOP and Tstop ' will be turned off, as shown in state 77. Please refer to Figure 8, Figure 8. The state diagram of the reset control circuit 610 is in operation. The state 81 is the initial state of the reset control circuit 610, and the output clock signal UP and the output clock signal DOWN have a high potential at the same time. High-potential output clock signal UP and output clock signal DOWN, and gate 68 The output has a high potential, as shown in state 82. Then, the reset transistors T RESET and D RESET ' will be turned on, and the output clock _ signal UP and the output clock signal DOWN will be pulled low to low. As shown in states 83 and 84. Finally, when the output B of the pulse generator 612 and the output B' of the pulse generator 622 are pulled high, as shown in state 85. The phase frequency detector at this time 600 will return to the initial state as shown in state 71 of Figure 7. In the phase frequency detector 600 of the present invention, the potentials of the output terminals B and B' are detected by sensing elements 618 _ and 628 The time for turning off the transistors Tstop and Tstop' can be accurately controlled, so that the pulse generators 612 and 622 can operate effectively. Meanwhile, in the present invention, when the output clock signal UP and the output clock signal DOWN are simultaneously at a high potential And the gate 68 reset signal Preset is sent through the delay circuit 66 to enable the output clock signal UP and the output clock signal DOWN to be maintained at a high potential for a certain period of time, so that when the phase frequency detector 600 receives the next One cycle clock signal Fref and time pulse No. Fref, each component can have enough time to react and reduce the phase frequency detector

19 < S 1325695 - 600 dead zone range. ^Feeding is only a preferred embodiment of the present invention, and all changes and modifications made in accordance with the scope of the present patent should be covered by the scope of the present invention. [Simplified description of the drawing] FIG. 1 is a prior art - Functional block diagram of the phase-locked loop. Figure 2 is an output signal diagram of the phase frequency 4M detector in the prior art. Lu 3 is a functional block diagram of a phase frequency controller using an RS flip-flop in the prior art. Figure 4 is a three-state diagram of the operation of the phase frequency inversion sensor in the prior art. Figure 5 is a circuit diagram of a phase frequency detector in the prior art. The $6 diagram is a circuit diagram of another phase-frequency detector that reduces deadband in the architecture of the present invention. Figure 7 is a diagram showing the state of the pulse generator of the present invention in operation. • Figure 8 is a diagram showing the state of the reset control circuit of the present invention in operation. [Main component symbol description] 100 phase-locked loop 120 charge pump 130 loop filter 140 voltage-controlled oscillator 150 frequency divider 310 ' 320 RS flip-flop 50 reverse gate 68 ' 330 and gate 66 delay circuit 510 , 610 reset control Circuit 20

Tiso ' Tstart ' Tstop Tstop5 ' Treset* ' Tsense5 ' Tp ', TN' transistor 1325695 * 616, 626 reverse circuit · 51-60, 61-64 110 , 300 , 500 , 600 512 , 522 , 612 , 622 514, 524, 614, 624 618, 628 sensing element inverter phase frequency detector pulse generator latch circuit

Treset, Tsense, Tp, Tn, Tstart’

twenty one

Claims (1)

1325695, the scope of patent application: a phase frequency detector capable of reducing the dead zone range, according to the input signals received by the first and second input terminals, corresponding output signals are generated at the first and second output ends thereof The phase frequency detector comprises: . The first-to-flash lock circuit has its first end connected to the first output of the phase frequency detector; ° - the second flash lock circuit 'the first end is lightly connected to the phase frequency detector second An output terminal; a reset control circuit coupled to the first end of the first and second latch circuits and the first and second output ends of the phase frequency detector, wherein: according to the phase frequency The potentials of the first and second rounds of the detector respectively generate corresponding signals to the second ends of the first and second pin circuits; ^ a first pulse generator comprising: a first input The first input terminal is coupled to the first input terminal, and the first input terminal is coupled to the second end of the first latch circuit. A second pulse generator is The method includes: 'a first input end coupled to the phase frequency detector input end; a second input terminal; and a second output terminal coupled to the second end of the second phase, the first reverse circuit includes an input terminal coupled to the first end of the phase frequency detector And the output terminal 'coupled to the second input end of the first pulse generator; the second reverse circuit includes an input coupled to the second end of the phase frequency detector; a 刖=output 'coupled to the second input of the second pulse generator; a sensing component, comprising: a second end, a second input of the first pulse generator a first end coupled to the first pong circuit; and a control terminal coupled to the second latch of the first latch circuit, and a second end; a sensing component, comprising: a second input terminal connected to the second pulse generator; first, coupled to the second reverse circuit; and - a control terminal at the second end of the second circuit . The phase frequency 4M detector according to the term 1 of the month, wherein: the first latch circuit comprises: a first 'the input end is connected to the first-flash lock circuit _ ^ and the output end is coupled Connected to the first end of the first latch circuit, and 1325695 * a second inverter, the input end of which is coupled to the output end of the first inverter, and the output end is coupled to the first reverse And the second latching circuit includes: a third inverter having an input end coupled to the first end of the second latch circuit, and an output end coupled to the second latch a second end of the lock circuit; and a fourth inverter, the input end of which is coupled to the output end of the third inverter, and the output end is coupled to the input end of the third inverter. 3. The phase frequency detector of claim 1, wherein: the first pulse generator comprises: a first N-type MOS transistor, comprising: a gate coupled to the a first input end of the first pulse generator; and a second N-type MOS transistor, comprising: a gate coupled to the second input end of the first pulse generator; a source, a coupling Connected to the drain of the first N-type MOS transistor; and -r • a drain coupled to the output of the first pulse generator; and the second pulse generator includes: 24 ί 5 > a third N-type MOS transistor, comprising: a wheel-gate coupled to the first end of the second pulse generator; and a fourth N-type MOS transistor comprising: The second input gate is coupled to the second pulse generator input end; one source is coupled to the third N-type gold-oxygen semi-electrode germanium; and a drain is coupled to the The output of the second pulse generator. 4. The phase frequency (four) device described in Item 3, the first and second type of gold oxide semi-electric crystals in #: the body each contains a source, and the phase is grounded as described in claim 1. a frequency detector, wherein: the Hedi: the sensing component comprises a -th-type MOS transistor, comprising: a gate coupled to the control terminal of the first sensing element; a source 'Pure the first - the first end of the sensing element; and - the dipole, the second end of the first sensing element; and "the second sensing element comprises a second type of gold oxide half a crystal comprising: - an interpole, the domain being at a control end of the second sensing element; The first pole is coupled to the first end of the second sensing component; and the second pole is coupled to the second end of the second sensing component. The phase fresh detector of claim 1, wherein the first reverse circuit and the second reverse circuit each comprise an inverter of a complementary metal oxide semiconductor structure. Wherein the reset control, such as the phase frequency detector circuit described in claim 1, includes: and a gate. The first and second input terminals are respectively coupled to the first and second output ends of the phase detector; the first reset N-type MOS transistor, comprising: a gate coupled to the opposite And a drain terminal coupled to the first end of the first interrogation circuit; and a source coupled to a bias voltage; and a second reset N-type MOS transistor, The gate includes a gate coupled to the output of the gate and a gate; a drain coupled to the second latch circuit a, E k , and a % of the suspension; and a source coupled to the A bias voltage. W<phase frequency detection, wherein the source of the Ν-type MOS transistor (4) to grounding = 9. As requested in item 7, r Xue X, Ying phase frequency detector' The reset control '^^S delay 7° piece' is coupled between the pole between the first and second reset N MOS transistors and the output of the NAND gate. 10. The phase frequency debt detector of claim 9, wherein the delay element comprises a resistor-capacitor delay circuit composed of a resistor and a capacitor. 11. The phase frequency detector of claim 9, wherein the delay element comprises a plurality of serially connected inverters. ^, 囷 27