TWI496191B - Method of forming semiconductor package - Google Patents
Method of forming semiconductor package Download PDFInfo
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- TWI496191B TWI496191B TW102100085A TW102100085A TWI496191B TW I496191 B TWI496191 B TW I496191B TW 102100085 A TW102100085 A TW 102100085A TW 102100085 A TW102100085 A TW 102100085A TW I496191 B TWI496191 B TW I496191B
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- Prior art keywords
- transparent carrier
- semiconductor
- semiconductor package
- semiconductor component
- layer
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- 239000004065 semiconductor Substances 0.000 title claims description 61
- 238000000034 method Methods 0.000 title claims description 8
- 239000010410 layer Substances 0.000 claims description 29
- 239000008393 encapsulating agent Substances 0.000 claims description 17
- 239000003292 glue Substances 0.000 claims description 17
- 239000012790 adhesive layer Substances 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 238000005286 illumination Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 239000000084 colloidal system Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 238000003825 pressing Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
- G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
- G03F7/2026—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure for the removal of unwanted material, e.g. image or background correction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Light Receiving Elements (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
本發明係有關於一種半導體封裝件及其製法，尤指一種能提升曝光精確度之半導體封裝件製法及據此所得之半導體封裝件。The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a method of fabricating a semiconductor package capable of improving exposure accuracy and a semiconductor package obtained thereby.
隨著電子產業的蓬勃發展，現今電子產品均朝向微型化、多功能、高電性及高速運作的方向發展。例如，隨著前端半導體晶片製程的集積化，半導體晶片之主動面上形成有密集的電極墊，以提供訊號的輸入/輸出(I/O)。為了配合此一發展趨勢，後端半導體業者積極研發能利用互連結構將該等電極墊傳輸之訊號扇出的半導體封裝件，例如扇出式封裝件。With the rapid development of the electronics industry, today's electronic products are moving toward miniaturization, multi-function, high-power and high-speed operation. For example, with the accumulation of front-end semiconductor wafer processes, dense electrode pads are formed on the active side of the semiconductor wafer to provide signal input/output (I/O). In order to cope with this trend, back-end semiconductor manufacturers are actively developing semiconductor packages, such as fan-out packages, that can fan out the signals transmitted by the electrode pads using interconnect structures.
在是種封裝件中，如晶片之半導體元件通常係藉由一封裝膠體鑲嵌至一承載件。之後，該承載件會被移除，並在該半導體元件上形成互連結構。如第1A至1G圖所示，係顯示一種扇出式封裝件之製法。In a package, a semiconductor component such as a wafer is typically mounted to a carrier by an encapsulant. Thereafter, the carrier is removed and an interconnect structure is formed on the semiconductor component. As shown in Figs. 1A to 1G, a method of manufacturing a fan-out package is shown.
如第1A圖所示，提供一表面上依序形成有離型層11和膠層12之透明承載件10，該膠層12上設置有半導體元件13。。As shown in FIG. 1A, a transparent carrier 10 having a release layer 11 and a subbing layer 12 formed on the surface is provided, and the subbing layer 12 is provided with a semiconductor element 13. .
如第1B圖所示，於該透明承載件10之底面10b上接置一光罩14，並進行曝光製程。As shown in FIG. 1B, a photomask 14 is attached to the bottom surface 10b of the transparent carrier 10, and an exposure process is performed.
如第1C圖所示，移除未曝光之膠層12部分。As shown in FIG. 1C, the unexposed glue layer 12 portion is removed.
接著，如第1D及1E圖之順序，藉由一支撐件16使封裝膠體15包覆該半導體元件13，並移除該透明承載件10。最後如第1F圖所示，移除剩餘之該膠層12。Next, as in the order of FIGS. 1D and 1E, the encapsulant 15 is coated with the semiconductor component 13 by a support member 16, and the transparent carrier 10 is removed. Finally, as shown in FIG. 1F, the remaining glue layer 12 is removed.
然而，該光罩14係設於透明承載件10之底面10b，且透明承載件10之厚度約有700μm，是以，曝光光線通過光罩14產生繞射，再通過一厚度較大的介質，將使得曝光圖形變形。尤其因設置半導體元件時，該半導體元件13之部分通常會陷入該膠層12(如第1A圖所示)，故必須於曝光時定義出半導體元件投影區域外之膠層部分，以於後續步驟移除之，但因曝光圖形變形導致於第1C圖所示之步驟無法移除半導體元件13周圍之膠層12，使得形成封裝膠體15時，無法完整包覆半導體元件13之側面，進行令該半導體元件13側面與封裝膠體15形成間隙g。如果接著於該半導體元件上形成互連結構，例如第1G圖所示之形成於該半導體元件13上之包括導電跡線171和絕緣層172之線路重佈結構17和導電元件18，勢必容易因該間隙g影響產品信賴性。However, the reticle 14 is disposed on the bottom surface 10b of the transparent carrier 10, and the thickness of the transparent carrier 10 is about 700 μm, so that the exposure light is diffracted by the reticle 14, and then passed through a medium having a relatively large thickness. The exposure pattern will be deformed. In particular, when a semiconductor device is provided, a portion of the semiconductor device 13 is usually trapped in the adhesive layer 12 (as shown in FIG. 1A), so that the portion of the adhesive layer outside the projected region of the semiconductor device must be defined during exposure for subsequent steps. It is removed, but the step shown in FIG. 1C cannot remove the adhesive layer 12 around the semiconductor component 13 due to the deformation of the exposure pattern, so that when the encapsulant 15 is formed, the side of the semiconductor component 13 cannot be completely covered. A side surface of the semiconductor element 13 forms a gap g with the encapsulant 15 . If an interconnect structure is subsequently formed on the semiconductor element, such as the line redistribution structure 17 and the conductive element 18 including the conductive traces 171 and the insulating layer 172 formed on the semiconductor element 13 as shown in FIG. 1G, it is easy to cause This gap g affects product reliability.
因此，如何克服習知技術中之種種問題，實已成目前亟欲解決的課題。Therefore, how to overcome various problems in the prior art has become a problem that is currently being solved.
鑑於上述習知技術之缺失，本發明提供一種半導體封 裝件之製法，係包括：設置至少一半導體元件於一透明承載件上，其中，該透明承載件表面上形成有膠層，該膠層與透明承載件之間形成有光罩，且該至少一半導體元件藉由該膠層黏附於該透明承載件上；進行曝光顯影步驟，以移除未為該至少一半導體元件所覆蓋之膠層部分；形成包覆該至少一半導體元件之封裝膠體；以及移除該透明承載件及剩餘之膠層。In view of the above-mentioned shortcomings of the prior art, the present invention provides a semiconductor package The method of manufacturing the method includes: disposing at least one semiconductor component on a transparent carrier, wherein a surface of the transparent carrier is formed with a glue layer, and a mask is formed between the glue layer and the transparent carrier, and the a semiconductor component is adhered to the transparent carrier by the adhesive layer; an exposure and development step is performed to remove a portion of the adhesive layer not covered by the at least one semiconductor component; and an encapsulant covering the at least one semiconductor component is formed; And removing the transparent carrier and the remaining glue layer.
本發明將圖案化的薄膜形成於膠層與透明承載件之間，以作為光罩，此薄膜的厚度很薄，尤其是相較於傳統曝光顯影的光罩厚度，故於大幅減少光罩與膠層之間的距離後，得以避免曝光光線通過光罩和透明承載件因產生繞射所放大之誤差，提升曝光精確度及產品信賴性。The invention forms a patterned film between the glue layer and the transparent carrier to serve as a photomask. The thickness of the film is very thin, especially compared with the thickness of the conventional exposure and development mask, so that the mask is greatly reduced. After the distance between the adhesive layers, the exposure light can be prevented from passing through the reticle and the transparent carrier due to the error of the diffraction, thereby improving the exposure precision and product reliability.
10,20‧‧‧透明承載件10,20‧‧‧Transparent carrier
10b‧‧‧底面10b‧‧‧ bottom
11,21‧‧‧離型層11,21‧‧‧ release layer
12,22‧‧‧膠層12,22‧‧‧ glue layer
13,23‧‧‧半導體元件13,23‧‧‧Semiconductor components
14‧‧‧光罩14‧‧‧Photomask
15,25‧‧‧封裝膠體15,25‧‧‧Package colloid
16,26‧‧‧支撐件16,26‧‧‧Support
17,27‧‧‧線路重佈結構17,27‧‧‧Line redistribution structure
171,271‧‧‧導電跡線171,271‧‧‧ conductive traces
172,272‧‧‧絕緣層172,272‧‧‧Insulation
18,28‧‧‧導電元件18,28‧‧‧Conductive components
2‧‧‧半導體封裝件2‧‧‧Semiconductor package
20a‧‧‧第一表面20a‧‧‧ first surface
20b‧‧‧第二表面20b‧‧‧second surface
24‧‧‧光罩膜24‧‧‧Photomask
23a‧‧‧作用面23a‧‧‧Action surface
23b‧‧‧非作用面23b‧‧‧Non-active surface
231‧‧‧電極墊231‧‧‧electrode pads
25a‧‧‧頂面25a‧‧‧ top
25b‧‧‧底面25b‧‧‧ bottom
g‧‧‧間隙G‧‧‧ gap
L‧‧‧照光L‧‧‧ illumination
第1A至1G圖係為習知扇出式封裝件之製法剖面示意圖；以及第2A至2H圖係為本發明之半導體封裝件之製法的剖面示意圖，其中，第2A’圖係第2A圖之俯視圖。1A to 1G are schematic cross-sectional views showing a conventional fan-out package; and FIGS. 2A to 2H are schematic cross-sectional views showing a method of fabricating the semiconductor package of the present invention, wherein FIG. 2A is a second FIG. Top view.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定 條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“頂”、“底”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. Limited The conditions are not technically meaningful, and any modification of the structure, change of the proportional relationship or adjustment of the size should remain in the present invention without affecting the effects and the achievable objectives of the present invention. The technical content revealed can be covered. In the meantime, the terms "upper", "top", "bottom", "first", "second" and "one" as used in this specification are also for convenience of description, not for The scope of the invention can be implemented, and the relative changes or adjustments of the invention are considered to be within the scope of the invention.
第2A至2H圖係為本發明之半導體封裝件之製法的剖面示意圖。2A to 2H are schematic cross-sectional views showing a method of fabricating the semiconductor package of the present invention.
首先，於進行曝光顯影步驟之前，係設置至少一半導體元件23於一透明承載件20上，其中，該透明承載件20表面上形成有膠層22，該膠層22與透明承載件20之間形成有光罩，且該至少一半導體元件23藉由該膠層22黏附於該透明承載件20上。First, before the exposure and development step, at least one semiconductor component 23 is disposed on a transparent carrier 20, wherein a surface of the transparent carrier 20 is formed with a glue layer 22 between the glue layer 22 and the transparent carrier 20. A photomask is formed, and the at least one semiconductor component 23 is adhered to the transparent carrier 20 by the adhesive layer 22.
具體而言，如第2A及2A’圖所示，提供一具有相對之第一表面20a和第二表面20b的透明承載件20，於該第一表面20a上形成一光罩膜24，例如，利用化學氣相沉積法於該第一表面20a上形成圖案化之金屬膜，其材質可為鋁。藉此，所得之薄膜厚度可薄至0.1μm。Specifically, as shown in FIGS. 2A and 2A', a transparent carrier 20 having an opposite first surface 20a and a second surface 20b is provided, and a photomask film 24 is formed on the first surface 20a, for example, A patterned metal film is formed on the first surface 20a by chemical vapor deposition, and the material thereof may be aluminum. Thereby, the obtained film thickness can be as thin as 0.1 μm.
如第2B圖所示，亦可利用化學氣相沉積法，於該透明承載件20之第一表面20a及光罩膜24上形成離型層21，接著於該離型層21上形成膠層22，其材質可為光固性膠，例如紫外光可固化膠。該膠層22與透明承載件20 之間形成有覆蓋該光罩膜24之離型層21，則該透明承載件20和光罩膜24即可重複使用，達到節省成本和簡化製程之效果。As shown in FIG. 2B, a release layer 21 may be formed on the first surface 20a of the transparent carrier 20 and the photomask film 24 by chemical vapor deposition, and then a glue layer may be formed on the release layer 21. 22, the material can be a photo-curable adhesive, such as an ultraviolet curable adhesive. The glue layer 22 and the transparent carrier 20 The release layer 21 covering the photomask film 24 is formed, and the transparent carrier 20 and the photomask film 24 can be reused, thereby achieving cost saving and simplifying the process.
如第2C圖所示，將至少一半導體元件23(本圖係以二個半導體元件說明)設於該透明承載件20之膠層22上。該半導體元件23係具有相對之作用面23a和非作用面23b，該作用面23a上具有複數電極墊231，且將該作用面23a接置於該膠層22上。As shown in FIG. 2C, at least one semiconductor element 23 (described in the figure as two semiconductor elements) is provided on the adhesive layer 22 of the transparent carrier 20. The semiconductor element 23 has an opposite active surface 23a and a non-active surface 23b. The active surface 23a has a plurality of electrode pads 231, and the active surface 23a is placed on the adhesive layer 22.
接著，如第2D及2E圖所示，進行曝光顯影步驟，亦即包括自該透明承載件20之第二表面20b照光L，再移除未為該至少一半導體元件23所覆蓋之膠層22部分。Next, as shown in FIGS. 2D and 2E, an exposure and development step is performed, that is, light is emitted from the second surface 20b of the transparent carrier 20, and the adhesive layer 22 not covered by the at least one semiconductor component 23 is removed. section.
如第2F圖所示，形成封裝膠體25時，可包括藉由支撐件26將該封裝膠體25壓制於該半導體元件23上，以包覆該半導體元件23。As shown in FIG. 2F, when the encapsulant 25 is formed, the encapsulant 25 may be pressed onto the semiconductor element 23 by the support member 26 to encapsulate the semiconductor element 23.
如第2G圖所示，移除該透明承載件20及剩餘之膠層22。As shown in FIG. 2G, the transparent carrier 20 and the remaining glue layer 22 are removed.
此外，可如第2H圖所示，於該半導體元件23上形成線路重佈結構27和如銲球之導電元件28，該線路重佈結構27包括形成於該半導體元件23及封裝膠體25之頂面25a上的導電跡線271以及覆蓋於該半導體元件23、封裝膠體25之頂面25a及導電跡線271上的絕緣層272，該絕緣層272外露部分導電跡線271，以供形成導電元件28。由於精準之曝光可減少間隙之產生，故可提升產品信賴性。In addition, as shown in FIG. 2H, a line redistribution structure 27 and a conductive member 28 such as a solder ball 28 may be formed on the semiconductor element 23, and the line redistribution structure 27 is formed on top of the semiconductor element 23 and the encapsulant 25. a conductive trace 271 on the face 25a and an insulating layer 272 overlying the semiconductor component 23, the top surface 25a of the encapsulant 25, and the conductive trace 271, the insulating layer 272 exposing a portion of the conductive trace 271 for forming a conductive component 28. Since accurate exposure reduces the occurrence of gaps, product reliability can be improved.
根據前述之製法，本發明提供一種半導體封裝件2， 係包括：封裝膠體25，係具有相對之頂面25a和底面25b；以及至少一半導體元件23，係嵌埋於該封裝膠體25中，該封裝膠體25之頂面25a外露出該至少一半導體元件23。According to the foregoing method, the present invention provides a semiconductor package 2, The method includes: an encapsulant 25 having an opposite top surface 25a and a bottom surface 25b; and at least one semiconductor component 23 embedded in the encapsulant 25, the top surface 25a of the encapsulant 25 exposing the at least one semiconductor component twenty three.
於一具體實施例中，該半導體封裝件2復包括支撐件26，如玻璃，係設於該封裝膠體25之底面25b上，且該至少一半導體元件23係具有相對之作用面23a和非作用面23b，且該封裝膠體25之頂面25a係外露出該至少一半導體元件23之作用面23a。In a specific embodiment, the semiconductor package 2 further includes a support member 26, such as glass, disposed on the bottom surface 25b of the encapsulant 25, and the at least one semiconductor component 23 has an opposite active surface 23a and a non-functional effect. The surface 23b and the top surface 25a of the encapsulant 25 expose the active surface 23a of the at least one semiconductor component 23.
於另一具體實施例中，該作用面23a與該封裝膠體25之頂面25a具有一段差，例如約10μm的段差。In another embodiment, the active surface 23a has a difference from the top surface 25a of the encapsulant 25, such as a step of about 10 [mu]m.
綜上所述，本發明將圖案化的薄膜形成於膠層與透明承載件之間，以作為光罩，因此光線通過光罩後不再穿越厚度很厚的透明承載件，故於大幅減少光罩與膠層之間的距離後，得以避免曝光光線通過光罩和透明承載件因產生繞射所放大之誤差，提升曝光精確度及產品信賴性。In summary, the present invention forms a patterned film between the adhesive layer and the transparent carrier to serve as a mask, so that the light passes through the mask and does not pass through the thick transparent carrier, thereby greatly reducing the light. After the distance between the cover and the glue layer, the exposure light can be prevented from passing through the reticle and the transparent carrier due to the error of the diffraction, thereby improving the exposure precision and product reliability.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
20‧‧‧透明承載件20‧‧‧Transparent carrier
20b‧‧‧第二表面20b‧‧‧second surface
21‧‧‧離型層21‧‧‧ release layer
22‧‧‧膠層22‧‧‧ glue layer
23‧‧‧半導體元件23‧‧‧Semiconductor components
24‧‧‧光罩膜24‧‧‧Photomask
L‧‧‧照光L‧‧‧ illumination
Claims (8)
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| TW102100085A TWI496191B (en) | 2013-01-03 | 2013-01-03 | Method of forming semiconductor package |
| CN201310015586.4A CN103915351B (en) | 2013-01-03 | 2013-01-16 | Method for manufacturing semiconductor package |
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| TW102100085A TWI496191B (en) | 2013-01-03 | 2013-01-03 | Method of forming semiconductor package |
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| TWI496191B true TWI496191B (en) | 2015-08-11 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TW201114009A (en) * | 2009-10-07 | 2011-04-16 | Xintec Inc | Chip package and fabrication method thereof |
| US20110193217A1 (en) * | 2010-02-08 | 2011-08-11 | Georg Meyer-Berg | Manufacturing of a Device Including a Semiconductor Chip |
| WO2011103211A1 (en) * | 2010-02-16 | 2011-08-25 | Cypress Semiconductor Corporation | Panelized packaging with transferred dielectric |
| US20110281405A1 (en) * | 2008-08-04 | 2011-11-17 | Infineon Technologies Ag | Method of fabricating a semiconductor device and semiconductor device |
| TW201236123A (en) * | 2011-02-24 | 2012-09-01 | Unimicron Technology Corp | Package structure and method of forming same |
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| CN102163603B (en) * | 2011-01-30 | 2013-11-06 | 南通富士通微电子股份有限公司 | Packaging structure for system level fan-out wafer |
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| US20110281405A1 (en) * | 2008-08-04 | 2011-11-17 | Infineon Technologies Ag | Method of fabricating a semiconductor device and semiconductor device |
| TW201114009A (en) * | 2009-10-07 | 2011-04-16 | Xintec Inc | Chip package and fabrication method thereof |
| US20110193217A1 (en) * | 2010-02-08 | 2011-08-11 | Georg Meyer-Berg | Manufacturing of a Device Including a Semiconductor Chip |
| WO2011103211A1 (en) * | 2010-02-16 | 2011-08-25 | Cypress Semiconductor Corporation | Panelized packaging with transferred dielectric |
| TW201236123A (en) * | 2011-02-24 | 2012-09-01 | Unimicron Technology Corp | Package structure and method of forming same |
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| CN103915351B (en) | 2016-09-28 |
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