TWI400789B - Semiconductor device - Google Patents

Description

Semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor device, and more particularly to a semiconductor device having an electrode pad and a capacitor element such as a flip chip pad.

[Cross-reference related application]

The present application is based on Japanese Patent Application No. 2006-71,089, the disclosure of which is incorporated herein by reference.

In recent years, the scale of semiconductor devices has increased and the degree of accumulation has increased, and the number of signal pads and the number of power pads have increased. Moreover, in the case where the operating rate of the device is increased, an improvement in the electrical characteristics of the device such as impedance matching between the semiconductor device and the mounting substrate or the package substrate is more important. A flip chip mounting has become the mainstream of measures to solve this problem. The flip chip mounting is a package mechanism that achieves a pad that is disposed across the entire surface of the semiconductor device, and more specifically, multiple pads. Moreover, the flip chip mounting provides improved electrical characteristics of the device throughout the packaged substrate or package substrate.

Figure 11 is a cross-sectional view showing the construction of a conventional flip chip bond pad (also indicated by FCPAD). The flip chip pads shown in Fig. 11 were formed in accordance with the following procedure.

First, an interlayer film 203 and an uppermost layer wiring 205 are formed on a semiconductor substrate 201 having a plurality of semiconductor elements and a plurality of wirings formed therein for protecting a cover film 207 of one of the semiconductor devices. On it. Next, only a portion of the uppermost layer wiring 205 of the cover film 207 connected to the flip chip bond pad 211 is selectively removed to provide a pad hole 217 extending through one of the cover films 207.

Then, the flip chip pad 211 is selectively formed in a region for forming the pad hole 217 and its vicinity. A solder ball 213 is sequentially selectively formed on the flip chip pad 211. Finally, although not shown in FIG. 11, the terminals on the side of the package substrate or the package substrate are connected to the solder balls 213 for completing the flip chip package.

At the same time, the scale of semiconductor devices has increased, the degree of accumulation has increased, and the increase in operating rate has progressed, and the circuit operation has become a more serious problem due to the defect of power/signal noise such as crosstalk. The countermeasure against these problems is to form a capacitor element on the semiconductor device and add a capacitor to other necessary parts such as a power supply to suppress noise. In addition, the process for forming a capacitor element includes a process of using a semiconductor substrate and a process using a wiring process, and in recent years, a metal-insulator-metal (MIM) capacitor is often manufactured by using the wiring process. Provides a high degree of design flexibility and a high degree of capacitance.

A typical example of such a capacitive element is described in Japanese Laid-Open Patent Publication No. 10-313,095 (1998), JP-A-2002-353,328, JP-A-2004-266,005, and JP-A-2001-313,372. No. 2002-57,291, and Japanese Patent Laid-Open No. 8-186235 (1996).

A technique for forming a capacitance under a solder pad is described in Japanese Laid-Open Patent Publication No. 10-313,095. 12A and 12B are structural views showing a device disclosed in Japanese Laid-Open Patent Publication No. 10-313,095.

In the configuration of Figs. 12A and 12B, a ceria film 3 as a capacitor film is formed on a well 14, which is formed in a single crystal germanium substrate 1, and will be used as a normal one. One of the gate electrodes, the first polysilicon wiring 4, is formed thereon to form a capacitor element. Further, a contact hole 7, a first (aluminum) metal wiring 8 and a second (aluminum) metal wiring 9 are formed on the first polysilicon wiring 4, and an aluminum soldering portion 16 is disposed thereon. A capacitive element is formed under a pad.

However, in the configuration shown in Fig. 12, no transistor or no wiring can be formed on the portion having the capacitance formed thereon. Therefore, MIM capacitors formed through a wiring process have recently been used.

Fig. 13 is a structural view showing the MIM capacitor explained in Japanese Laid-Open Patent Publication No. 2002-353,328. The structure shown in FIG. 13 relates to a process in which a lower layer metal layer 2B is simultaneously patterned in a multilayer film in a process for forming a lower wiring layer 2A, and a dielectric material layer 3A is formed thereon. on. Further, an upper cladding metal layer 4 is formed thereon and selectively patterned to form a capacitive element between the lower metal layer 2B and the upper wiring layer 4. Then, via holes 7a to 7d and 11a, wirings 7A to 7D and 11, and upper wiring layers 9A to 9C which are provided between the respective wirings and between the electrodes are formed.

Fig. 14 is a structural view showing the MIM capacitor explained in Japanese Patent Laid-Open No. 2004-266,005. In the configuration shown in Fig. 14, a first aluminum wiring 3 and an anti-reflection film 4 are formed, and then a second insulating via 5 is formed. Next, a normal contact plug 82 is opened to expose one surface of the first aluminum wiring 3, and one of the upper electrodes 81 of a capacitor is opened to expose one surface of the anti-reflection film 4.

Then, each of the openings is filled with the barrier metal 7 and the metal electrode, and a second aluminum wiring 10 is further formed thereon. This provides a connection between the first aluminum wiring 3 and the second aluminum wiring 10 via the contact plug 82, and a titanium nitride (TiN) layer 41 and a bismuth oxynitride (SiON) layer from the antireflection film 4. A capacitor element having a capacitance film formed of 42 is formed between the first aluminum wiring 3 and the upper electrode 81.

Further, a technique for forming a MIM capacitor between metal layers by using a copper wiring process in accordance with a damascene process is described in Japanese Laid-Open Patent Publication No. 2001-313,372. We may consider that this technology is an advanced version of the technology described in Japanese Patent Laid-Open No. 2004-266,005. The technique described in Japanese Laid-Open Patent Publication No. 2004-266,005 has a separate damascene process for forming a contact plug for connecting the upper and lower plates and a separate process for forming the upper cover plate, but the Japanese Patent Laid-Open No. The technique described in No. 2001-313, No. 372 has a single process for simultaneously forming a contact plug and an upper cover plate via a double inlay process. Further, although the technique described in Japanese Laid-Open Patent Publication No. 2004-266,005 includes a board connected to one of the upper cover layers, the technique described in Japanese Laid-Open Patent Publication No. 2001-313,372 includes a board connected to the lower layer wiring.

Japanese Laid-Open Patent Publication No. 2002-57,291 describes a technique for forming a rewiring on a connection pad and then forming a capacitor element therebetween.

Japanese Laid-Open Patent Publication No. 8-186235 describes a technique for forming a memory cell transistor and a memory capacitor on different substrates and then bonding the substrates to form a dynamic random access memory (DRAM). In the circuit configuration of such a DRAM, one of the terminals of a memory capacitor is connected to one memory cell transistor and the other is grounded.

However, in the various techniques described in the related art documents listed above, there is still room for improvement as described below.

First, in the technique described in Japanese Laid-Open Patent Publication No. 10-313,095, since the capacitor is formed under the pad, no transistor or no wiring can be formed on the portion where the capacitor is to be formed. Further, the capacitance is formed on the germanium substrate, and therefore, an increase in capacitance results in an increase in the area of the wafer. Moreover, in recent years, as the number of layers of such wiring increases, the direct connection of the capacitive element formed by the basic process to the pad directly disposed thereon can reduce the degree of flexibility for designing such wiring, thereby not realistic.

Further, in the technique described in Japanese Laid-Open Patent Publication No. 2002-353,328, another electrode layer is formed between the wiring layers as the upper electrode, which requires complicated structure and manufacturing conditions, and requires an increase in operation. number.

Further, in the technique described in Japanese Laid-Open Patent Publication No. 2002-353,328, the lower wiring is used for the lower electrode of the capacitor. Further, in the technique described in Japanese Laid-Open Patent Publication No. 2004-266,005, the upper cover wiring and the contact plug are used for the upper electrode of the capacitor, and the lower wiring is used for the lower electrode. In these configurations, no wiring can be extended through this portion, thereby reducing the degree of flexibility of the design. Further, an increase in the capacitance causes an increase in the area ratio of the capacitors occupying the area of the wiring, and further deteriorates the wiring capability and the adjustment capability of one of the wirings, and the wafer area and the number of wirings can be increased.

In the technique described in Japanese Laid-Open Patent Publication No. 2004-266,005, since the MIM capacitor is formed without forming another layer between the wiring layers, by forming an upper electrode to be coplanar with the contact plug, as above Referring to Fig. 14, the configuration can be further simplified as compared with the configuration of Fig. 2002-353, 328 (Fig. 13). However, since the upper and lower wiring layers are used for such electrodes of the capacitance of the configuration shown in FIG. 14, the limitation on the wiring design is increased, and the increase in capacitance causes an increase in the size of the wafer and/or an increase in the number of wirings.

Further, the technique described in Japanese Laid-Open Patent Publication No. 2001-313, No. 372 has a problem similar to the technique described in Japanese Patent Laid-Open No. 2004-266,005, because the upper and lower plates are added in the wiring. A board layer is formed using a wiring itself. Also, when the lower plate is used as a bond pad, an additional upper cover layer is formed on the bond pads, requiring additional operation to form a conductive layer.

In the technique described in Japanese Laid-Open Patent Publication No. 2002-57,291, the capacitor element is formed on the electrode pad, and the electrode pad is disposed on a protective film deposited on the insulating layer, and constitutes a dielectric of the capacitor element. The material is disposed on the electrode pad, and another conductive film is disposed thereon. Therefore, the addition of this layer of the electroconductive thin film containing this capacitive element results in a complicated process in the technique described in Japanese Laid-Open Patent Publication No. 2002-57,291.

Further, in the technique described in Japanese Laid-Open Patent Publication No. 8-186235, a memory capacitor segment and a transistor segment are separately manufactured, and the two segments are joined by a ridge therebetween, thereby aligning The two segments that are joined are complicated. Moreover, there may be a concern that causes misalignment between the substrates, which results in a decrease in manufacturing yield.

According to an embodiment of the present invention, a semiconductor device includes: a semiconductor substrate; an insulating via disposed on the semiconductor substrate; a multilayer wiring buried in the insulating via; and an electrode bonding a pad which is disposed to face an upper surface of one of the uppermost wirings of the multilayer wiring and has a bump electrode for external connection mounted thereon; and a capacitor insulating film disposed on the uppermost wiring And the electrode pad, wherein the semiconductor device comprises a capacitor element, which is composed of the uppermost layer wiring, the capacitor insulating film and the electrode pad.

In the description of the related art, the flip chip pads 211 of the prior art described above with reference to FIG. 11 are used to mount a solder ball for flip chip bonding. Therefore, it is inevitable that the flip chip pads 211 are electrically connected to the uppermost wiring 205. Inevitably The die pad 211 does not function as a capacitor element.

On the contrary, in the semiconductor device of the present invention, a capacitor is formed between the uppermost layer wiring and the electrode pad. With this configuration, a capacitor can be formed between the basic elements in the semiconductor device without the need to have a new conductive layer for forming a capacitor. Therefore, the complexity of the process by providing a capacitor element can be avoided. Moreover, since a capacitor can be formed in a space region above the uppermost layer wiring, this space region can be effectively utilized to provide a capacitor element while ensuring a certain degree of flexibility in the design of the device, and can be easily Promote a further increase in its capacitance. Further, since the uppermost layer wiring functioning as the lower electrode of the capacitor element can be utilized as one of the power supply lines of the present invention, stable operation of the power source of the components of the apparatus can be achieved.

Here, the electrode pad constituting the capacitor element may have a configuration in which a bump electrode for external connection is provided thereon, and a bump electrode may or may not be mounted thereon.

Since the device according to the present invention includes the capacitor element composed of the uppermost layer wiring, the capacitor insulating film and the electrode pad as described above, the region above the uppermost layer wiring can be effectively utilized to provide the capacitor element while suppressing The process of manufacturing such semiconductor devices is complicated.

The invention will now be described with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be made by using the teachings of the present invention, and the invention is not limited to the embodiments shown.

Preferred embodiments in accordance with the present invention will be described in more detail below with reference to additional figures. In all the figures, the same numbers are assigned to the elements that are normally present in this figure, and the detailed description will not be repeated.

(First Embodiment)

Fig. 1 is a cross-sectional view showing the structure of a semiconductor device of the present embodiment.

A semiconductor device 100 shown in FIG. 1 includes: a semiconductor substrate (germanium substrate 101); an insulating interlayer (interlayer film 103) disposed on the germanium substrate 101; and a multilayer wiring buried in the interlayer film 103; An electrode pad (flip-chip pad 111) disposed to face an upper surface of one of the uppermost layers 105 of the multilayer wiring and having a bump electrode (solder ball 113) for mounting thereon One of the outer coupling portions; and a capacitor insulating film (capacitor film 109) are disposed between the uppermost layer wiring 105 and the flip chip pad 111. In the semiconductor device 100, the solder balls 113 are bonded to the flip chip pads 111.

The semiconductor device 100 includes a capacitor element 110 composed of an uppermost layer wiring 105, a capacitor film 109, and a flip chip pad 111, and a capacitor is formed between the uppermost layer wiring 105 and the flip chip pad 111.

The semiconductor device 100 includes a first insulating film (cover film 107) covering one of the upper portions of the interlayer film 103, and a recess portion (a window region) is provided in the cover film 107 in a region facing the upper surface of the uppermost layer wiring 105. 115).

The thickness of the cover film 107 is locally reduced in this region to form the aperture region 115, and the cover film 107 in this region having a reduced thickness constitutes the capacitance film 109. The capacitor film 109 formed between the uppermost layer wiring 105 and the flip chip pad 111 is formed by etching the cover film 107, and the capacitor film 109 is selectively formed in this region for being formed on the uppermost layer wiring 105. The capacitance between the flip chip pad 111 and the flip chip.

The cover film 107 is formed, for example, with a material different from that used for the interlayer film 103. In the present embodiment, the interlayer film 103 is an insulating film containing ruthenium, and the cover film 107 and the capacitor film 109 are an organic resin film such as a polyimide film or the like. The cover film 107 serves as a protective film, and a region having a reduced thickness also serves as the capacitance film 109. In the semiconductor device 100, the protective film and the capacitor film 109 are formed integrally and continuously.

The flip chip pad 111 has an electrode pad configuration that provides a flip chip connection of the germanium substrate 101 on other substrates. The flip chip pad 111 is disposed over the cover film 107 and constitutes an upper electrode of the capacitor element 110. The flip chip pad 111 is disposed so as to cover one of the inner walls of the window region 115 and extend to the outside of the window region 115. Further, the rewiring layer is not included in the upper portion of the flip chip pad 111.

The flip chip pad 111 is composed of, for example, nickel (Ni), copper (Cu), molybdenum (Mo), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), nitrogen. A conductive film of one of the metals such as TaN or the like, or a multilayer film of these films. The material of the flip chip pad 111 may be different from the material of the uppermost layer wiring 105. This provides increased selectivity for one of the materials that exhibits better adhesion to the solder balls 113 of the flip chip pads 111.

The material of the solder ball 113 may be, for example, an alloy of lead (Pb) and tin (Sn), an alloy of silver (Ag) and Sn, or the like. Although the structure for using the solder balls 113 for the bump electrodes mounted on the flip chip pads 111 is shown in the present embodiment and the following embodiments, the material of the bump electrodes is not limited to the solder.

The uppermost wiring 105 constituting the capacitive element 110 may be, for example, a power supply wiring (VDD) or a ground wiring (GND). Further, the uppermost wiring 105 constituting the capacitor element 110 may be a signal wiring.

The semiconductor device shown in FIG. 1 may be formed, for example, by the following process.

First, an interlayer film 103 is formed on a germanium substrate 101 having a plurality of predetermined semiconductor elements, wirings, and circuits formed thereon, and then an uppermost wiring 105 is formed in such an interlayer film. The uppermost wiring 105 may be, for example, a layer composed of aluminum (Al), Cu and an alloy thereof, and a multilayer film composed of one of Ti, TiN, TiW, Ta, TaN, or the like.

A cover film 107 for protecting the semiconductor element is formed on the uppermost layer wiring 105. Next, a photomask (not shown) having a region for forming a capacitance on the uppermost wiring 105 as an opening portion is formed on the upper surface of the cover film 107. The cover film 107 includes a reduced thickness from one of the regions exposed from the opening portion, and a thinner region which functions as the capacitance film 109 can be formed, and an opening region 115 having a lower surface of the upper surface of the thinner region is formed.

Next, the flip chip pad 111 is formed on the opening region 115. In this case, the flip chip pad 111 is formed to extend from the inner wall surface of one of the opening regions 115 to the outside of one of the opening regions 115.

Then, a solder ball 113 for providing a coupling to the packaged substrate or the package substrate is formed on the flip chip pad 111.

The semiconductor device shown in Fig. 1 is obtained in accordance with the above procedure. In this procedure, a capacitor film 109 is formed between the flip chip pad 111 and the uppermost layer wiring 105 to form the capacitor element 110.

Moreover, since the thickness of the cover film 107 is locally reduced as the capacitance film 109 in the present embodiment, the device of the present embodiment can be adjusted by merely adjusting the cover film of the conventional semiconductor device described above with reference to FIG. It is easy to obtain with a proper opening condition.

In the present embodiment, the flip chip pads 111 disposed on the germanium substrate 101 are used to enable the capacitor element 110 to form a minimum number of operations. In this case, the capacitance can be formed by changing only one of the conditions for etching the cover film 107 without adding a new conductive layer for providing a capacitance element. Therefore, the simplification of this process can be achieved.

Figure 15 is a cross-sectional view showing an exemplary embodiment of a configuration of a semiconductor device having dedicated capacitor electrodes between the wiring layers. The structure shown in Fig. 15 is formed in accordance with the following procedure. A plurality of lower wirings 311 are formed on one semiconductor substrate 310. Next, an interlayer film 312 is formed thereon. Further, a capacitor lower layer electrode 313 and a capacitor film 314 are formed thereon and patterned. A capacitor upper electrode 315 is selectively formed thereon, and an interlayer film 316 is formed on the entire surface thereof. Next, a desired portion is opened to form a contact plug 317 for providing a coupling to an upper electrode, an upper cover wiring 318 is formed thereon, the formed wiring is patterned, and an interlayer film is formed. The 319 series is formed on the entire surface thereof.

In contrast to the techniques disclosed in Japanese Laid-Open Patent Publication No. 2002-353, No. 328 and No. 2004-266,005, the use of such dedicated capacitor electrodes does not require the use of a wiring for the exemplary embodiment shown in FIG. One of the electrodes is formed for use, so the limitation on the design of such wiring is reduced, and the increase in the size of the wafer and the increase in the number of wiring layers can be considerably reduced due to the increase in capacitance. However, since the upper and lower capacitor electrodes and the dedicated layer are formed between the wiring layers, the configuration and manufacturing conditions are complicated and the number of operations required is also increased.

On the contrary, according to the configuration of the dedicated capacitor electrodes for forming between the wiring layers, the simplification of the device configuration and the process can be achieved according to the present embodiment.

Moreover, since a space region in the uppermost layer wiring can be effectively utilized as a capacitor in the present embodiment, the design of the capacitor arrangement region may be provided after the design of all components including the uppermost layer wiring is completed, and therefore, Consideration should be given to the design limitations of the location of such capacitors, etc., which do not provide any indication of the degree of flexibility in designing such wiring and/or such components.

Figure 16 is a diagram showing an exemplary embodiment of a flip chip bond including a flip chip bond for providing the semiconductor device 100 of Figure 1. In the configuration shown in FIG. 16, the flip chip pads 111 are disposed in a certain area on the uppermost wiring 105, and the flip chip pads 131 are disposed in other regions. The flip chip pad 131 is electrically connected to the uppermost wiring 105. The flip chip pad 131 is an electrode pad capable of electrically coupling one of the electrodes provided in the other substrate to the uppermost wiring 105 when the 矽 substrate 101 is flip-chip bonded to the other substrate.

In this case, since the flip chip pads 111 constituting the capacitor element 110 and the flip chip pad 131 can be simultaneously formed by the same operation, the complication of the process caused by the provision of the capacitor element 110 can be reduced.

Moreover, the flip chip pads 111 are typically disposed over the germanium substrate 101 to form a pattern of dot patterns or a type of array pattern having equal spacing or conform to a predetermined configuration rule. Without the need to change the rules for configuring such flip chip pads 131, the flip chip pads 111 are disposed in one of flip chip pads 131 that are not required to provide a common coupling. In the space area. Thus, the presence of such flip chip pads 111 does not adversely affect the configuration of the flip chip pads 131 used to provide a common coupling at one of its perimeters. In the present embodiment, the space region is effectively utilized to provide the high-capacity capacitive element 110, and a simplified process can be achieved, ensuring design flexibility and promoting an increase in capacitance.

In addition to the above, although a structure having exactly one flip chip pad 131 and exactly one flip chip pad 111 is shown in Fig. 16, a predetermined number of pads may be provided over the ruthenium substrate 101. Since the number of flip chip pads 111 mounted thereon can be freely determined within an allowable range, the rise and fall of the capacitance value can be promoted. Also, since the flip chip pad 111 is fabricated in the final operation of the diffusion process, the change and/or correction of the capacitance value can be easily achieved when the change and/or correction is required after the design is completed.

Moreover, although the two-dimensional geometry of one of the flip chip pads 111 constituting the capacitor element 110 is the same as the two-dimensional geometry of the flip chip pad 131 connected to the pad of the package substrate, the structure is shown in FIG. 16. Medium, but these two-dimensional geometries may be different, as discussed later in the description of the tenth embodiment.

Further, by providing the flip chip pad 111 having its own capacitance, it is possible to form a capacitor element which is easy to provide an increased capacitance by a simple process which does not disturb the design flexibility of one of the embodiments. In addition, it can also promote the rise and fall of the capacitance value or change. Moreover, the flip chip pads 111 constituting the capacitor element 110 are also specifically formed to function as a signal input pad or a power pad.

Further, since in the present embodiment, the uppermost wiring 105 can be utilized as a power supply line, an immediate power supply can be achieved and a stable potential can be secured. Therefore, the use of the capacitive element 110 can suppress the defects of the circuit operation due to noise.

Further, in the semiconductor device 100, the flip chip pad 111 is specifically formed to cover the inner wall surface of one of the window regions 115 and extend to the cover film 107 outside the window region 115. Therefore, when the solder balls 113 are bonded to the flip chip pads 111, the solder balls 113 can be more reliably mounted to form flip chip pads than those described in the above listed documents. Within one of the 111 areas. Therefore, contamination or the like due to diffusion of the metal in the solder ball 113 can be more effectively suppressed by the solder ball 113 in contact with the cover film 107.

Further, since the present embodiment uses the flip chip pad 111 as an upper electrode, the technique described in Japanese Patent Laid-Open No. 8-186235 (which includes one of the terminals of the memory capacitor necessarily connected to the ground) is used. Below, the flip chip pad 111 can be connected to a desired potential other than the ground terminal.

Although an exemplary embodiment in which the cover film 107 and the capacitor film 109 are made of an organic resin film such as a polyimide film or the like is described in the present embodiment, the film obtainable in this configuration may include a plurality of insulating films ( Including ruthenium or the like, such as a ruthenium dioxide film, a tantalum nitride film, a ruthenium oxynitride film, a tantalum carbide film, a tantalum carbonitride film, or the like, or a single film or two or two of such a film may be used. One of the above films is a multilayer film.

In the following embodiments, focusing on the features different from those of the first embodiment will be explained.

(Second embodiment)

Figure 2 is a cross-sectional view showing the structure of one of the semiconductor devices of the present embodiment. The basic structure of a semiconductor device 120 shown in FIG. 2 is similar to that described in the first embodiment (FIG. 1) except that different insulating films are used for the cover film 107 and the capacitor film 119 of the capacitor element 130, respectively. The construction of the semiconductor device 100.

Further, the recess formed in the cover film 107 corresponds to a through hole (pad hole 117) extending through one of the cover films 107 in the semiconductor device 120. The semiconductor device 120 includes a second insulating film (capacitor film 119) covering one of the inner walls of such a through hole, and the flip chip pad 111 is provided on the capacitor film 119.

The pad hole 117 is a channel hole provided in the cover film 107 in a region where the capacitor element 130 is to be formed.

In the present embodiment, the cover film 107 may be composed of a protective film which is composed of an organic resin film such as a polyimide film or the like. Further, the capacitor film 119 is made of, for example, a material different from the material of the cover film 107. In the present embodiment, the capacitor film 119 may be composed of, for example, a high dielectric constant film.

Here, the high dielectric constant film is a film which exhibits a higher specific dielectric constant than yttrium oxide, and a so-called "high-k film" may be employed. The high dielectric constant film may be composed of a material exhibiting a specific dielectric constant of 6 or higher. More specifically, the high dielectric constant film may be composed of a material selected from the group consisting of hafnium (Hf), tantalum (Ta), zirconium (Zr), titanium (Ti), tungsten (W), and tantalum. One or more metal components of a group consisting of (Re), tantalum (Tb) and aluminum (Al), and may also comprise a film comprising one of the above metal components, an alloy film, an oxide film, a tannic acid Salt film with a carbon film and so on. It is possible to use one of these films alone or a combination of two or more of these films to form a multilayer film.

The semiconductor device shown in Fig. 2 is formed in accordance with the following procedure. The cover film 107 on the uppermost wiring 105 is formed by using the process described in the first embodiment. Then, in a region for forming a capacitive element 130, a portion of the cover film 107 disposed on the uppermost wiring 105 is selectively removed to establish an opening. In the present embodiment, the pad hole 117 extending through the cover film 107 is formed during the process of establishing such an opening by a process for forming a pad hole 217 (see FIG. 11) of the semiconductor device as described above. It is used to expose the upper surface of one of the uppermost wirings 105.

Next, an insulating film for forming the capacitor film 119 is formed on the entire upper surface of the cover film 107, and then the insulating film is patterned, so that a plurality of portions of the insulating film are selectively retained in addition to The capacitor is formed in a region other than the vicinity thereof. This provides a capacitive film 119 that forms a lower surface that covers one of the pad holes 117.

Then, the process after the formation of the flip chip pad 111 is carried out by using the process in the first embodiment described above.

As described above, the present embodiment relates to the formation of the capacitor film 119 by a process different from that of the cover film 107 after the opening portion of the cover film 107 is formed, and the capacitor film 119 is selectively formed to be formed at The portion of the capacitance between the uppermost layer wiring 105 and the flip chip pad 111 and its vicinity.

Since in the present embodiment, this capacitance is formed between the flip chip pad 111 and the uppermost layer wiring 105, the advantageous effects obtainable in the first embodiment can also be obtained.

Moreover, in the present embodiment, the material of the capacitor film 119 can be arbitrarily selected independently of the material for the cover film 107, so that the capacitance value of the capacitor element can be established to have a desired value of a higher degree of flexibility. . Further, a high-k capacitor film or the like is used for the capacitor film 119, so that the capacitance of the higher capacitance element 130 can be easily achieved.

Further, in the present embodiment, the flip chip pad 111 is specifically formed to cover one inner wall surface of the pad hole 117 and extend the pad hole 117 on the cover film 107. Further, in the present embodiment, the capacitor film 119 is specifically formed to cover the inner wall surface of one of the pad holes 117 and to extend the pad holes 117 on the cover film 107. Therefore, it is further ensured that the solder ball 113 is prevented from coming into contact with the cover film 107. Therefore, contamination or the like caused by diffusion of one of the metals in the solder ball 113 can be further effectively suppressed.

Although an exemplary embodiment including the capacitor film 119 composed of a high dielectric constant film is described in the present embodiment, specific examples of the film which can be obtained by the capacitor film 119 include a hafnium oxide film, a hafnium nitride film, and nitrogen. A ruthenium oxide film, a tantalum carbide film, a ruthenium carbonitride film, a polyimide film, or the like, and a single film of one of the films or a stacked film of one or two or more of the above films may also be used. Further, these films may be used in combination with the above high dielectric constant film.

Further, it is also possible to use the films of the above-described first embodiment for the cover film 107.

Between the following embodiments, the third to eighth embodiments are illustrative of the exemplary embodiments in which one of the capacitive elements is a region of the cover film 107 having a reduced thickness, as in the first embodiment. The capacitive element 110 is illustrated. Of course, in these embodiments, one of the capacitive elements may also be another insulating film disposed on the cover film 107, as in the second embodiment.

(Third embodiment)

The configuration of the above embodiment may be designed such that the uppermost wiring and the electrode pad constituting a capacitor element are respectively connected to different power supply potentials.

For example, when the uppermost wiring 105 under the flip chip pad 111 is a power supply wiring (VDD) or a ground wiring (GND), the following procedure is performed. When the uppermost layer wiring 105 is a power supply wiring, a pad 123 located on the side of the substrate (which is connected to the flip chip pad 111 constituting the capacitor) is assigned as a ground portion, and when the uppermost layer is The wiring 105 is a ground wiring, and the pad 123 located on the side of the substrate is assigned as a power supply portion. As described above, the uppermost layer wiring 105 and the pad 123 located on the side of the substrate (which is connected to the flip chip pad 111 facing the uppermost layer wiring 105) are respectively connected to different power supply portions having different potentials.

Fig. 3 is a cross-sectional view showing the structure of one of the semiconductor devices of the embodiment. In addition to the semiconductor device further comprising a substrate 121 having a pad 123 on one side of the substrate, and the pad 123 on the side of the substrate is bonded to the solder ball 113, the basic structure of the semiconductor device shown in FIG. The structure is similar to that of the semiconductor device 100 described in the first embodiment (Fig. 1).

The substrate 121 is a substrate that is flip-chip bonded to the ruthenium substrate 101. The substrate 121 is, for example, a packaged substrate or a package substrate.

The flip chip pad 111 may be connected to one of the wirings (not shown) provided in the substrate 121 via the pad 123 positioned on the side of the substrate. For example, the flip chip pad 111 may be connected to one of the power supply wirings or a ground wiring provided in the substrate 121. Moreover, the pad 123 located on the side of the substrate may be a power supply wiring (VDD) or a ground wiring (GND).

The structure shown in Fig. 3 was manufactured in accordance with the following procedure.

The process until the solder balls 113 are formed on the germanium substrate 101 is carried out by employing the processes in the first embodiment described above. The uppermost wiring 105 is connected to a first power supply potential. Further, a substrate 121 provided with a pad 123 positioned on the side of the substrate was prepared. In addition to the above, the pad 123 positioned on the side of the substrate is connected to, for example, a second power supply potential different from the first power supply potential.

Next, the pads 123 disposed on the substrate 121 on the side of the substrate are connected to the solder balls 113. At this time, a heating temperature and a heating time can be appropriately determined depending on the material type of the solder ball 113. For example, the heating action is carried out at a temperature of about 200 to 350 ° C for about a few minutes to tens of minutes to melt the solder balls 113 to provide coupling to one of the pads 123 located on the side of the substrate.

In this embodiment, the uppermost layer wiring 105 is connected to the first power source potential, and the pad 123 connected to the flip chip pad 111 on the side of the substrate is connected to the second power source different from the first power source potential. Potential. Since the second power source potential is not equivalent to the first power source potential, the capacitance between the uppermost layer wiring 105 and the flip chip pad 111 is formed at a different potential, and a noise caused by one of the power source potentials drifts. Etc. can be suppressed.

(Fourth embodiment)

Alternatively, the configuration of the above embodiment may be designed such that a single uppermost wiring system is disposed under the entire flip chip pad 111.

4A and 4B are views showing a configuration of a semiconductor device of the present embodiment. 4A is a plan view, and FIG. 4B is a cross-sectional view taken along line AA' of FIG. 4A.

The basic configuration of the semiconductor device of the present embodiment is similar to that in the first embodiment except that the semiconductor device further includes a single uppermost wiring 105 disposed on the entire area facing the lower surface of one of the flip chip pads 111 (FIG. 1). The configuration of the semiconductor device 100 described in FIG. 4A is as shown in FIG. 4A. This provides the largest dimension of the open region 115 in the flip chip pads 111 in any of the lower surface regions, thereby making the configuration of the device more suitable for increasing capacitance.

(Fifth Embodiment)

The present embodiment relates to a configuration in which the configuration of the first embodiment additionally includes a plurality of uppermost wirings disposed under the flip chip pads 111, and between the uppermost wirings, the specifics are selected. Wiring the capacitors contained on it.

5A and 5B are views showing the configuration of a semiconductor device of the present embodiment. Fig. 5A is a plan view, and Fig. 5B is a cross-sectional view taken along line B-B' of Fig. 5A.

The basic structure of the semiconductor device of the present embodiment is similar to that of the semiconductor described in the first embodiment (FIG. 1) except that the uppermost layer wiring 105 and the uppermost layer wiring 125 are disposed in the same layer as the uppermost layer wiring. The construction of device 100.

When the semiconductor device of the present embodiment is formed, first, the interlayer film 103 is formed on the germanium substrate 101, and the germanium substrate 101 has one semiconductor element/wiring and/or one of the circuits formed therein.

Next, the uppermost layer wiring 105 used for a power supply wiring or a signal wiring and having a relatively wide cross section, and the uppermost wiring 125 mainly used for a signal wiring and having a relatively narrow cross section are formed in In the same process in which the uppermost layer wiring is formed into a coplanar relationship. Then, a cover film 107 is formed.

Then, the opening region 115 is selectively formed only in the region above the uppermost wiring 105 to form a thinned region of the cover film 107. This thinned region serves as the capacitor film 109. Next, the flip chip pad 111 is formed on the capacitor film 109. The processes available to form the various layers and their construction may include the processes and configurations illustrated in the first embodiment.

In the present embodiment, between the plurality of uppermost wirings disposed under the flip chip pads 111, only such specific wirings can be employed as the lower electrodes of the capacitor elements. In addition, this provides a further improvement in the design flexibility of the layer under the flip chip pads 111.

(Sixth embodiment)

This embodiment relates to a configuration in which the uppermost wirings of the flip chip pads 111 in the first embodiment are a plurality of power supply wirings, signal wirings, or a combination thereof having different potentials.

6A and 6B are views showing the configuration of a semiconductor device of the present embodiment. 6A is a plan view, and FIG. 6B is a cross-sectional view taken along line CC' of FIG. 6A. The basic configuration of the semiconductor device of the present embodiment is similar to that of the semiconductor device 100 described in the first embodiment (FIG. 1) except for the following embodiments.

In the present embodiment, the uppermost layer wiring facing one of the flip chip pads 111 includes a first uppermost layer wiring (uppermost layer wiring 127) and a second uppermost layer wiring (uppermost layer wiring 129). The flip chip pad 111 and the uppermost layer wiring 127 constitute a first capacitor element, and the flip chip pad 111 and the uppermost layer wiring 129 constitute a second capacitor element. The uppermost layer wiring 127 and the uppermost layer wiring 129 are, for example, connected to different potentials. More specifically, the uppermost layer wiring 127 and the uppermost layer wiring 129 are respectively connected to power supply potentials of different potentials.

The semiconductor device shown in FIGS. 6A and 6B is obtained, for example, by performing the following procedure.

First, an interlayer film 103 is formed on a germanium substrate 101, and the germanium substrate 101 has a semiconductor element/wiring or a circuit formed therein. Then, the uppermost layer wiring 127 connected to a first power source potential and the uppermost layer wiring 129 connected to a second power source potential different from the first power source potential are formed in a common line for forming the uppermost layer wiring. The surface relationship is made in the same process.

Next, a cover film 107 is formed on the interlayer film 103. Then, the opening region 115 is formed to extend over a region above the uppermost wiring 127 and a region above the uppermost wiring 129 for forming the capacitor film 109. Next, the flip chip pad 111 is formed on the capacitor film 109. This provides a flip chip pad 111 formed to extend from the region above the uppermost layer wiring 127 to the region above the uppermost layer wiring 129. The processes available to form the various layers and their construction may include the processes and configurations illustrated in the first embodiment.

In the present embodiment, a capacitor element having an upper electrode of one of the flip chip pads 111 can be simultaneously formed on a plurality of power supply wirings having different potentials disposed under the flip chip pads 111. Furthermore, this provides a further improvement in the design flexibility of the area under the flip chip pads 111.

In the technique described in Japanese Laid-Open Patent Publication No. 2001-313,372, the above-mentioned related art shows that the lower plate is divided into two spacers between the wires constituting a capacitor. On the contrary, the present embodiment is different from this conventional configuration from the viewpoint of constituting a capacitor upper electrode (or flip chip pad 111) to exhibit a pad function. Moreover, in the present embodiment, the number of wires extending under the flip chip pads 111 is not limited to two, but three or more wires may be used, and the potential may be freely selected, and may even be possible. Configure a signal line. Also, as discussed later in the description of the ninth embodiment, it is possible to apply a capacitor to the only one of the uppermost layer wirings between the plurality of uppermost wirings, and the only one specific wiring may be connected to the flip chip Solder pad 111.

(Seventh embodiment)

The configuration of the sixth embodiment may alternatively be designed to connect the flip chip pad 111 to a third power supply potential which is different from the uppermost layer wiring 127 and the uppermost layer wiring 129 which are located on one side of the substrate. The third power supply potential may be selected to be, for example, a ground potential (GND).

7A and 7B are cross-sectional views showing the configuration of a semiconductor device of the present embodiment.

This semiconductor device is formed in accordance with the following procedure. The procedure from the formation of the germanium substrate 101 to the formation of the flip chip pads 111 is similar to the procedure in the sixth embodiment. Then, the solder balls 113 are formed on the flip chip pads 111, and the pads 123 on the sides of the substrate 121 are connected to the solder balls 113.

In addition to the above, the pad 123 on the side of the substrate is connected to a third power supply potential different from the first power supply potential of one of the uppermost wirings 127 and the second power supply potential of one of the uppermost wirings 129. Or, that is, a ground potential.

According to the present embodiment, as schematically shown in FIG. 7A, the capacitor can be simultaneously formed between three different potentials via flip chip pads 111, or, for example, between ground and the first power supply potential and at ground. Between the second power supply potentials. Further, in the present embodiment, a further improvement in the design flexibility of the region under the flip chip pad 111 can be provided.

(Eighth embodiment)

The configuration of the sixth embodiment may alternatively be designed such that the flip chip pad 111 is broken (OPEN) or, more specifically, the flip chip pad 111 is not connected to the pad 123 located on the side of the substrate 121. .

8A and 8B are cross-sectional views showing the configuration of a semiconductor device of the present embodiment. Although not shown in these figures, the semiconductor device of the present embodiment may include a flip chip bond pad for establishing a flip chip connection in the same layer including the flip chip pad 111 (for example, 16 flip chip pads 131).

In the process shown in Figs. 8A and 8B, the procedure from the formation of the germanium substrate 101 to the formation of the flip chip pad 111 is similar to that in the sixth embodiment.

Next, although a solder ball is formed on a flip chip bond pad (not shown) to provide a common coupling (which is formed in the same layer that also includes the flip chip pad 111), no solder balls are formed in the solder ball. Flip the die pad 111.

Then, the flip chip pads for establishing the flip-chip connection are connected to the pads 123 on the side of the substrate 121. This provides a configuration in which no solder balls appear on the flip chip pad 111 as shown in Fig. 8B, so that the flip chip pads 111 are in an electrically disconnected state.

In the present embodiment, as schematically shown in FIG. 8A, a capacitor is formed between the uppermost layer wiring 127 and the uppermost layer wiring 129 via the flip chip pad 111, and another capacitor is formed at the first power supply potential. Between the second power supply potential. Further, in the present embodiment, a further improvement in the design flexibility of the region under the flip chip pad 111 can be provided.

(Ninth embodiment)

The present embodiment is directed to a configuration in which a plurality of uppermost wiring layers are present under the flip chip pads 111 of the second embodiment and provide wiring to one of the flip chip pads 111 and constitute one of the capacitors. Wiring. The uppermost wiring under the flip chip pad 111 is a plurality of power supply wirings, signal wirings, or a combination thereof having different potentials, and a capacitor is selectively formed and connected to any of these wirings.

9A and 9B are views showing the configuration of a semiconductor device of the present embodiment. 9A is a plan view, and FIG. 9B is a cross-sectional view taken along line DD' of FIG. 9A.

In one semiconductor device shown in FIGS. 9A and 9B, the uppermost layer wiring facing one of the flip chip pads 111 includes a first uppermost wiring (uppermost wiring 127) and a second uppermost wiring ( The uppermost wiring 129).

The flip chip pad 111 is directly connected to the uppermost wiring 129 in a partial region of the lower surface, and a capacitor film 119 is disposed on the flip chip pad 111 and the uppermost wiring 127 in other regions of the lower surface. between. A region including the capacitor film 119 disposed therebetween serves as a capacitor element, and a bonding region between the uppermost layer wiring 129 and the flip chip pad 111 serves as an electrical coupling region between the wiring and the substrate 121 (not shown). ). More specifically, the flip chip pad 111 and the uppermost layer wiring 127 constitute a capacitor element, and the flip chip pad 111 is electrically connected to the uppermost layer wiring 129.

The semiconductor device is formed in accordance with the following procedure. The procedure until the uppermost layer wiring 127 and the uppermost layer wiring 129 are formed on the ruthenium substrate 101 is similar to the procedure in the sixth embodiment. Next, a cover film 107 is formed.

Then, in a region extending across one of the uppermost layer wiring 127 and the uppermost layer wiring 129, a portion of the cover film 107 is selectively removed to form a recess, thereby exposing the surface of the uppermost layer wiring 127 and the uppermost layer wiring 129.

Next, a high dielectric constant film is formed on the entire upper surface of the cover film 107. The high dielectric constant film is patterned, and the capacitor film 119 covers the uppermost layer wiring 127 to form an upper surface of the opening region 115 with respect to the exposed portion of the uppermost wiring 127, and a process is performed to The exposed portion of the upper wiring 129 or the capacitor film 119 is removed from the region above the pad hole 117 to form the capacitor film 119.

Then, a flip chip pad 111 is formed on the capacitor film 119 and the opening region 115. The processes available to form the various layers and their construction may include the processes and configurations illustrated in the second embodiment.

In the present embodiment, the flip chip pad 111 is electrically connected to the uppermost layer wiring 129, and a capacitor element is formed between the flip chip pad 111 and the uppermost layer wiring 127. Therefore, according to the present embodiment, a single flip chip pad 111 can simultaneously establish a coupling with the substrate 121 (not shown) and form a capacitive element.

Although the exemplary embodiment of the configuration in the second embodiment is shown in this embodiment, it should be noted that the capacitive film may alternatively be formed with the cover film 107, which is similar to the first embodiment. In this case, the thickness of the cover film 107 in the region above the uppermost wiring 127 is locally reduced, and the cover film 107 in the region above the uppermost wiring 129 is removed to expose the most Upper wiring 129.

Alternatively, similar to the seventh and eighth embodiments, coupling to the packaged substrate or package substrate may also be established.

(Tenth embodiment)

In the above embodiment, the description is mainly directed to the case where the geometry of the flip chip pads 111 constituting the capacitor elements is the same as the geometry of the flip chip pads for establishing a common coupling (for example, Figure 16 is a flip chip pad 131). Since the flip chip pads are usually arranged according to a predetermined arrangement rule, such as a grid shape or an array of fixed intervals, the above configuration is considered to configure the flip chip pads 111 constituting the capacitor elements according to the arrangement rules. There is no space in one of the flip chip pads for normal coupling.

However, the geometry available for the flip chip pad 111 is not particularly limited and can be freely designed in accordance with a two-dimensional geometry such as the width of one of the uppermost wirings and the like. In the present embodiment, another two-dimensional geometry of the flip chip pad 111 will be described.

The constructions of the ninth embodiment are described below or may be designed to be suitably employed to add a capacitance (i.e., area) to each flip chip bond pad.

10A and 10B are views showing the configuration of a semiconductor device of the present embodiment. Fig. 10A is a plan view, and Fig. 10B is a cross-sectional view taken along line EE' of Fig. 10A. The basic configuration of a semiconductor device shown in Figs. 10A and 10B and its basic process is similar to the basic configuration and basic process in the ninth embodiment.

However, in the present embodiment, one of the through holes provided in the flip chip pad 111 and the cover film 107 is designed in a predetermined form, and a larger opening portion is disposed on the cover film which is located as the portion of the capacitor. 107. Then, the capacitor film 119 and the flip chip pad 111 are formed in a predetermined region on the lower surface of one of the pad holes 117, similarly in the ninth embodiment.

The uniform geometry and height of the solder balls is preferably required to improve adhesion to the packaged substrate or package substrate, as determined by the geometry of one of the flip chip pads and the amount of solder. Therefore, in the configurations of the first to ninth embodiments, the geometry of the flip chip pad 111 is selected to be the same geometry as the flip chip bond pad used to establish the normal coupling ( For example, the flip chip pad 131 of FIG. 16 can provide a uniform geometry and height of the solder balls, and is considered to be a flip chip pad 111 that may form a solder ball. However, when the flip chip pad 111 is not connected to the pad located on the side of the substrate, the geometry of the flip chip pad 111 constituting the capacitor element can be freely designed similarly to the present embodiment, and is designed. The scope falls within the scope of the present invention which does not provide an effect on the surrounding flip chip pads. This configuration provides an increased capacitance area for each capacitive element, thereby facilitating an increase in this capacitance.

Although the exemplary embodiment of the configuration in the second embodiment is shown in the present embodiment, it should be noted that the capacitive film may alternatively form a cover film, similar to the first embodiment, or may adopt the configuration of the eighth embodiment.

Although the preferred embodiments of the present invention have been described with reference to the accompanying drawings, it is to be understood that structure.

For example, such a configuration including one or more uppermost wirings that are disposed to face the lower portion of the flip chip pad 111 is shown in the above-described embodiments and is opposite thereto to constitute a capacitive element. The plurality of flip chip pads 111 may be disposed to face an upper portion of the uppermost wiring. Alternatively, in this case, a plurality of flip chip pads 111 may also be connected to different potentials, respectively.

It is apparent that the present invention is not limited to the above-described embodiments, and variations and changes may be made without departing from the spirit and scope of the invention.

1‧‧‧ Single crystal germanium substrate

2A‧‧‧Wiring layer

2B‧‧‧Under metal layer

3‧‧‧First aluminum wiring/cerium oxide film

3A‧‧‧ dielectric material layer

4‧‧‧Upper Covering Wiring Layer/Upper Covering Metal Layer/Anti-Reflection Film/First Polysilicon Layout

5‧‧‧Second insulating interlayer

7‧‧‧Resistive metal/contact hole

7A-7D, 11‧‧‧ wiring

7a-7d, 11a‧‧‧ channel hole

8‧‧‧First (aluminum) metal wiring

9‧‧‧Second (aluminum) metal wiring

9A-9C‧‧‧ wiring layer

10‧‧‧Second aluminum wiring

14. . . well

16. . . Aluminum welding department

41. . . Titanium nitride (TiN) layer

42. . . Niobium oxynitride (SiON) layer

81. . . Upper electrode

82. . . Contact plug

100. . . Semiconductor device

101. . .矽 substrate

103. . . Interlayer film

105. . . Uppermost wiring

107. . . Cover film

109. . . Capacitor film

110. . . Capacitive component

111. . . Flip chip pad

113. . . Solder ball

115. . . Window area/open area

117. . . Solder pad hole

119. . . Capacitor film

120. . . Semiconductor device

121. . . Substrate

123. . . Solder pad

125. . . Uppermost wiring

127. . . Uppermost wiring

129. . . Uppermost wiring

130. . . Capacitive component

131. . . Flip chip pad

201. . . Semiconductor substrate

203. . . Interlayer film

205. . . Uppermost wiring

207. . . Cover film

211. . . Flip chip pad

213. . . Solder ball

217. . . Solder pad hole

310. . . Substrate

311. . . Wiring

312. . . Interlayer film

313. . . Capacitor lower electrode

314. . . Capacitor film

315. . . Capacitor upper electrode

316. . . Interlayer film

317. . . Contact plug

318. . . Overlay wiring

319. . . Interlayer film

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, advantages and features of the present invention will become more apparent from A cross-sectional view showing a configuration of a semiconductor device in an embodiment; FIG. 3 is a cross-sectional view showing a configuration of a semiconductor device in an embodiment; and FIGS. 4A and 4B are views showing a semiconductor device in an embodiment. 5A and 5B are structural diagrams showing a semiconductor device in an embodiment; FIGS. 6A and 6B are structural diagrams showing a semiconductor device in an embodiment; and FIGS. 7A and 7B are diagrams showing an implementation. FIG. 8A and FIG. 8B are structural diagrams showing a semiconductor device in an embodiment; FIGS. 9A and 9B are structural diagrams showing a semiconductor device in an embodiment; FIG. 10A 10B is a structural view showing a semiconductor device in an embodiment; FIG. 11 is a cross-sectional view showing a configuration of a conventional semiconductor device; and FIGS. 12A and 12B are diagrams showing a conventional semiconductor device. FIG. 13 is a cross-sectional view showing a configuration of a conventional semiconductor device; FIG. 14 is a cross-sectional view showing a configuration of a conventional semiconductor device; and FIG. 15 is a view showing a configuration of a conventional semiconductor device. FIG. 16 is a cross-sectional view showing the configuration of a semiconductor device in an embodiment.

100. . . Semiconductor device

101. . .矽 substrate

103. . . Interlayer film

105. . . Uppermost wiring

107. . . Cover film

109. . . Capacitor film

110. . . Capacitive component

111. . . Flip chip pad

113. . . Solder ball

115. . . Window area/open area

Claims (9)

A semiconductor device comprising: a semiconductor substrate; an insulating via disposed on the semiconductor substrate; a multilayer wiring buried in the insulating via; and an electrode pad disposed to face an uppermost wiring of the multilayer wiring a top surface on which a bump electrode for external connection is mounted; a first insulating film disposed between the uppermost layer wiring and the electrode pad; and the first insulating film covering an upper portion of the insulating layer, wherein the upper surface The semiconductor device includes a capacitor element including the uppermost layer wiring and the electrode pad, wherein the first insulating film is composed of a single material, wherein the first insulating film completely covers an upper surface of the uppermost layer wiring, wherein the The first insulating film is provided with a recess in a region facing the upper surface of the uppermost wiring, wherein the electrode pad is disposed to cover an inner wall surface of the recess and extend to the outside of the recess, and wherein In the formation region of the recess, one of the thicknesses of the first insulating film is thinned, and the capacitor element is formed in a region of the first insulating film having a reduced thickness. The semiconductor device of claim 1, further comprising a bump electrode bonded to the electrode pad. The semiconductor device of claim 1, wherein the first insulating film is an organic resin film. The semiconductor device according to claim 1, wherein the uppermost wiring constituting the capacitor element is a power supply wiring or a ground wiring. A semiconductor device according to claim 1, wherein the uppermost wiring constituting the capacitor element is a signal wiring. The semiconductor device of claim 1, further comprising a substrate flip-chip bonded to the semiconductor substrate, wherein the electrode pad is connected to one of the power supply wiring or the ground wiring disposed in the substrate. The semiconductor device of claim 1, wherein the uppermost layer wiring and the electrode pad constituting the capacitor element are respectively connected to different power source potentials. The semiconductor device of claim 1, wherein the uppermost layer wiring facing one of the electrode pads comprises a first uppermost layer wiring and a second uppermost layer wiring, wherein the electrode pad and the first layer An uppermost layer of wiring constitutes a first capacitive element, and wherein the electrode pad and the second uppermost layer of wiring form a second capacitive element. The semiconductor device of claim 1, wherein the uppermost layer wiring facing one of the electrode pads comprises a first uppermost layer wiring and a second uppermost layer wiring, wherein the electrode pad and the first layer A topmost wiring constitutes the capacitive element, and wherein the electrode pad is electrically connected to the second uppermost wiring.