TWI596793B - Light sensing device and method of manufacturing same - Google Patents
Light sensing device and method of manufacturing same Download PDFInfo
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- TWI596793B TWI596793B TW104137868A TW104137868A TWI596793B TW I596793 B TWI596793 B TW I596793B TW 104137868 A TW104137868 A TW 104137868A TW 104137868 A TW104137868 A TW 104137868A TW I596793 B TWI596793 B TW I596793B
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/80—Constructional details of image sensors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/021—Manufacture or treatment of multiple TFTs
- H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/441—Interconnections, e.g. scanning lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
- H10F39/014—Manufacture or treatment of image sensors covered by group H10F39/12 of CMOS image sensors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
- H10F39/016—Manufacture or treatment of image sensors covered by group H10F39/12 of thin-film-based image sensors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Solid State Image Pick-Up Elements (AREA)
- Light Receiving Elements (AREA)
Description
本發明是有關於一種感測裝置及其製造方法，且特別是有關於一種光感測裝置及其製造方法。The present invention relates to a sensing device and a method of fabricating the same, and more particularly to a light sensing device and a method of fabricating the same.
光感測單元普遍應用於手機、平板電腦或筆記型電腦等電子裝置中。此外，光感測單元也廣泛應用於醫療診斷輔助工具之使用，例如X-ray光感測用於人體乳房組織之攝影。且主要包括一個薄膜電晶體（thin film transistor，TFT）以及一個PIN二極體（PIN diode），其中薄膜電晶體作為讀取的開關元件，PIN二極體則扮演將光能轉換成電子訊號的感測元件。傳統上，光感測單元的製造流程是在薄膜電晶體上形成一層保護層後，才形成PIN二極體(PIN層)，前述保護層用來保護薄膜電晶體的通道層與第二導體層，以避免在後續形成PIN層時傷害到通道層與第二導體層。其中，當薄膜電晶體具有蝕刻阻擋層（Etch Stop Layer，ESL）型態時，光感測單元一般需要12道微影蝕刻製程（Photolithography and Etching Process，PEP）才能完成製作，而當薄膜電晶體為背通道蝕刻（Back Channel Etch，BCE）型態時，一般需要11道微影蝕刻製程才能完成製作。然而，由於PIN層必須與第二導體層電性接觸，故為了有效避免第二導體層在形成PIN層時受到傷害，絕緣層中的接觸窗的寬度必小於PIN層。如此一來，接觸窗的設計使得部分的PIN層無法與第二導體層電性接觸，因而限制了PIN二極體的感應面積。因此，如何改善光感測單元的製造流程，避免PIN二極體的感應面積受到限制，為目前極須克服的一個重要課題。The light sensing unit is commonly used in electronic devices such as mobile phones, tablet computers, and notebook computers. In addition, the light sensing unit is also widely used in the use of medical diagnostic aids, such as X-ray light sensing for photography of human breast tissue. And mainly includes a thin film transistor (TFT) and a PIN diode (PIN diode), wherein the thin film transistor is used as a read switching element, and the PIN diode acts to convert light energy into an electronic signal. Sensing element. Conventionally, the manufacturing process of the photo sensing unit is to form a PIN diode (PIN layer) after forming a protective layer on the thin film transistor, and the protective layer is used to protect the channel layer and the second conductor layer of the thin film transistor. To avoid damage to the channel layer and the second conductor layer when the PIN layer is subsequently formed. Wherein, when the thin film transistor has an Etch Stop Layer (ESL) type, the photo sensing unit generally needs 12 photolithography and Etching Process (PEP) to complete the fabrication, and when the thin film transistor For the Back Channel Etch (BCE) type, 11 lithography processes are generally required to complete the fabrication. However, since the PIN layer must be in electrical contact with the second conductor layer, in order to effectively prevent the second conductor layer from being damaged when the PIN layer is formed, the width of the contact window in the insulating layer must be smaller than that of the PIN layer. As a result, the contact window is designed such that part of the PIN layer cannot be electrically contacted with the second conductor layer, thereby limiting the sensing area of the PIN diode. Therefore, how to improve the manufacturing process of the light sensing unit and avoid the limitation of the sensing area of the PIN diode is an important subject that must be overcome at present.
本發明提供一種光感測裝置及其製造方法，可提升感測元件的感應面積。The invention provides a light sensing device and a manufacturing method thereof, which can improve the sensing area of the sensing component.
本發明的光感測裝置包括基板、主動元件及感測元件。主動元件配置在基板上且包括設置於基板上的第一導體層，設置於第一導體層上的閘極絕緣層，設置於閘極絕緣層上的通道層以及設置於通道層上的第二導體層。感測元件配置在第二導體層上且包括設置且覆蓋在第二導體層上的第一透明電極層，設置在第一透明電極層上的光電轉換層以及設置在光電轉換層上的第二透明電極層。The light sensing device of the present invention includes a substrate, an active component, and a sensing component. The active component is disposed on the substrate and includes a first conductor layer disposed on the substrate, a gate insulating layer disposed on the first conductor layer, a channel layer disposed on the gate insulating layer, and a second layer disposed on the channel layer Conductor layer. The sensing element is disposed on the second conductor layer and includes a first transparent electrode layer disposed on the second conductor layer, a photoelectric conversion layer disposed on the first transparent electrode layer, and a second disposed on the photoelectric conversion layer Transparent electrode layer.
本發明的光感測裝置的製造方法包括以下步驟。形成第一導體層於基板上。形成閘極絕緣層於第一導體層上。形成通道層於閘極絕緣層上。形成第二導體層於通道層上，其中第二導體層具有第一端與第二端，且第一導體層、閘極絕緣層、通道層以及第二導體層構成主動元件。形成第一透明電極層於第二導體層上。形成光電轉換層於第一透明電極層上。形成第二透明電極層於光電轉換層上，其中第一透明電極層、光電轉換層及第二透明電極層構成感測元件，且第一端與第二端的其中之一延伸至感測元件下方。The method of manufacturing the photo sensing device of the present invention includes the following steps. A first conductor layer is formed on the substrate. A gate insulating layer is formed on the first conductor layer. A channel layer is formed on the gate insulating layer. Forming a second conductor layer on the channel layer, wherein the second conductor layer has a first end and a second end, and the first conductor layer, the gate insulating layer, the channel layer, and the second conductor layer constitute an active element. A first transparent electrode layer is formed on the second conductor layer. A photoelectric conversion layer is formed on the first transparent electrode layer. Forming a second transparent electrode layer on the photoelectric conversion layer, wherein the first transparent electrode layer, the photoelectric conversion layer and the second transparent electrode layer constitute a sensing element, and one of the first end and the second end extends below the sensing element .
基於上述，在本發明的光感測裝置中，透過第二導體層上設置有第一透明電極層，使得第一透明電極層能夠保護第二導體層在形成光電轉換層的製程中不受到破壞，以及使得光電轉換層能夠完全且直接地與第一透明電極層接觸，因而提升感測元件的感應面積。Based on the above, in the light sensing device of the present invention, the first transparent electrode layer is disposed on the second conductive layer, so that the first transparent electrode layer can protect the second conductive layer from being damaged in the process of forming the photoelectric conversion layer. And enabling the photoelectric conversion layer to completely and directly contact the first transparent electrode layer, thereby increasing the sensing area of the sensing element.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施方式，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
圖1A至圖1K為本發明之第一實施方式的光感測裝置之製造流程的剖面示意圖。1A to 1K are schematic cross-sectional views showing a manufacturing flow of a photo sensing device according to a first embodiment of the present invention.
首先，請參照圖1A，於基板100上形成第一導體層M1。在本實施方式中，基板100可以是剛性基板，例如玻璃基板、石英基板或矽基板，或可以是可撓性基板，例如聚合物基板或塑膠基板。First, referring to FIG. 1A, a first conductor layer M1 is formed on a substrate 100. In the present embodiment, the substrate 100 may be a rigid substrate such as a glass substrate, a quartz substrate or a germanium substrate, or may be a flexible substrate such as a polymer substrate or a plastic substrate.
在本實施方式中，第一導體層M1即為閘極。基於導電性的考量，第一導體層M1一般是使用金屬材料。然而，本發明並不限於此，第一導體層M1也可以使用金屬材料以外的其他導電材料，例如：合金、金屬材料的氮化物、金屬材料的氧化物、金屬材料的氮氧化物、或是金屬材料與其它導電材料的堆疊層。另外，在本實施方式中，第一導體層M1透過第一道微影蝕刻製程而形成。另外一提的是，在本實施方式中，在形成第一導體層M1的同時，還可形成與第一導體層M1連接的閘極線（未繪示），意即第一導體層M1與閘極線屬於同一膜層。In the present embodiment, the first conductor layer M1 is a gate. The first conductor layer M1 is generally made of a metal material based on conductivity considerations. However, the present invention is not limited thereto, and the first conductor layer M1 may also use other conductive materials other than the metal material, such as an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or A stacked layer of metallic material and other conductive materials. Further, in the present embodiment, the first conductor layer M1 is formed by the first photolithography etching process. In addition, in the present embodiment, while forming the first conductor layer M1, a gate line (not shown) connected to the first conductor layer M1 may be formed, that is, the first conductor layer M1 and The gate lines belong to the same film layer.
接著，請參照圖1B，於第一導體層M1上形成閘極絕緣層GI。閘極絕緣層GI通常可以利用物理氣相沉積法或化學氣相沉積法全面性地沉積在基板100上。閘極絕緣層GI的材質例如是氧化矽（SiOx）、氮化矽（SiNx）或氮氧化矽等無機材料。Next, referring to FIG. 1B, a gate insulating layer GI is formed on the first conductor layer M1. The gate insulating layer GI can be generally deposited on the substrate 100 by physical vapor deposition or chemical vapor deposition. The material of the gate insulating layer GI is, for example, an inorganic material such as cerium oxide (SiOx), tantalum nitride (SiNx) or cerium oxynitride.
接著，於閘極絕緣層GI上形成通道層CH。詳細而言，通道層CH的材質可以是非晶矽、多晶矽或是其他半導體材料，或可以是氧化銦錫鋅（Indium-Tin-Zinc Oxide，ITZO）等的氧化物半導體材料。另外，在本實施方式中，通道層CH透過第二道微影蝕刻製程而形成。Next, a channel layer CH is formed on the gate insulating layer GI. In detail, the material of the channel layer CH may be amorphous germanium, polysilicon or other semiconductor material, or may be an oxide semiconductor material such as Indium-Tin-Zinc Oxide (ITZO). Further, in the present embodiment, the channel layer CH is formed by a second photolithography etching process.
另外一提的是，於閘極絕緣層GI上形成通道層CH後，可更包括於基板100的周邊區(非顯示區)內的閘極絕緣層GI中形成一接觸窗（未繪示），以於後續製程中形成用以與外部電路連接的連接線，其中外部電路例如是驅動晶片或軟性印刷電路（flexible printed circuit，FPC）。詳細而言，所述接觸窗透過第三道微影蝕刻製程而形成。In addition, after the channel layer CH is formed on the gate insulating layer GI, a contact window (not shown) may be formed in the gate insulating layer GI in the peripheral region (non-display region) of the substrate 100. In order to form a connection line for connecting with an external circuit in a subsequent process, for example, a driver chip or a flexible printed circuit (FPC). In detail, the contact window is formed through a third lithography process.
接著，請參照圖1C，於基板100上依序形成導體材料層M2’與透明電極材料層TE1’。基於導電性的考量，導體材料層M2’一般是使用金屬材料。然而，本發明並不限於此，導體材料層M2’也可以使用金屬材料以外的其他導電材料，例如：合金、金屬材料的氮化物、金屬材料的氧化物、金屬材料的氮氧化物、或是金屬材料與其它導電材料的堆疊層。透明電極材料層TE1’的材質包括氧化銦錫（ITO）、氧化銦鋅（IZO）、氧化鋁鋅（AlZO）、氧化鋁銦、氧化銦（InO）、氧化鎵（gallium oxide，GaO）、奈米碳管、奈米銀顆粒、厚度小於60奈米(nm)的金屬或合金、有機透明導電材料、或其它適合的透明導電材料。Next, referring to Fig. 1C, a conductor material layer M2' and a transparent electrode material layer TE1' are sequentially formed on the substrate 100. The conductor material layer M2' is generally made of a metal material based on conductivity considerations. However, the present invention is not limited thereto, and the conductive material layer M2' may also use other conductive materials other than the metal material, such as an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or A stacked layer of metallic material and other conductive materials. The material of the transparent electrode material layer TE1' includes indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AlZO), aluminum oxide indium, indium oxide (InO), gallium oxide (GaO), nai. Carbon nanotubes, nano-silver particles, metals or alloys having a thickness of less than 60 nanometers (nm), organic transparent conductive materials, or other suitable transparent conductive materials.
接著，請參照圖1D，於基板100上形成第一透明電極層TE1。詳細而言，在本實施方式中，第一透明電極層TE1的製造方法包括：利用一第四道光罩進行微影蝕刻製程，以將透明電極材料層TE1’圖案化而形成第一透明電極層TE1。另外，在本實施方式中，用以形成第一透明電極層TE1的微影蝕刻製程中的蝕刻步驟例如是濕式蝕刻步驟，蝕刻液例如是鋁酸。Next, referring to FIG. 1D, a first transparent electrode layer TE1 is formed on the substrate 100. In detail, in the present embodiment, the manufacturing method of the first transparent electrode layer TE1 includes: performing a photolithography etching process using a fourth photomask to pattern the transparent electrode material layer TE1' to form a first transparent electrode layer. TE1. In addition, in the present embodiment, the etching step in the lithography etching process for forming the first transparent electrode layer TE1 is, for example, a wet etching step, and the etching liquid is, for example, aluminate.
接著，請參照圖1E，於基板100上形成第二導體層M2。在本實施方式中，第二導體層M2的製造方法包括：同樣利用用以形成第一透明電極層TE1的同一張光罩(即所述第四道光罩)進行微影蝕刻製程，以將導體材料層M2’圖案化而形成第二導體層M2，其中第二導體層M2具有第一端102a與第二端102b。在本實施方式中，第一導體層M1、閘極絕緣層GI、通道層CH以及第二導體層M2構成主動元件TFT。具體而言，在本實施方式中，第二導體層M2的第一端102a用以作為主動元件TFT的源極，而第二端102b用以作為主動元件TFT的汲極。另外，在本實施方式中，主動元件TFT屬於背通道蝕刻型態。Next, referring to FIG. 1E, a second conductor layer M2 is formed on the substrate 100. In the present embodiment, the manufacturing method of the second conductor layer M2 includes: performing the lithography process using the same reticle (ie, the fourth reticle) for forming the first transparent electrode layer TE1 to The material layer M2' is patterned to form a second conductor layer M2, wherein the second conductor layer M2 has a first end 102a and a second end 102b. In the present embodiment, the first conductor layer M1, the gate insulating layer GI, the channel layer CH, and the second conductor layer M2 constitute an active device TFT. Specifically, in the present embodiment, the first end 102a of the second conductor layer M2 is used as the source of the active device TFT, and the second end 102b is used as the drain of the active device TFT. Further, in the present embodiment, the active device TFT belongs to the back channel etched type.
進一步而言，第一透明電極層TE1接觸第二導體層M2，以及第二導體層M2與第一透明電極層TE1具有相同的圖案。換言之，第一透明電極層TE1完全覆蓋該第二導體層M2，意即前述兩者實質上面積大小相同，但並不以此為限。另外，在本實施方式中，用以形成第二導體層M2的微影蝕刻製程中的蝕刻步驟可以是濕式蝕刻步驟或乾式蝕刻步驟，其中當蝕刻步驟為濕式蝕刻步驟時，蝕刻液例如是草酸。Further, the first transparent electrode layer TE1 contacts the second conductor layer M2, and the second conductor layer M2 has the same pattern as the first transparent electrode layer TE1. In other words, the first transparent electrode layer TE1 completely covers the second conductor layer M2, that is, the two surfaces have substantially the same size, but are not limited thereto. In addition, in the embodiment, the etching step in the lithography etching process for forming the second conductor layer M2 may be a wet etching step or a dry etching step, wherein when the etching step is a wet etching step, the etching liquid is, for example, It is oxalic acid.
從結構觀點而言，在本實施方式中，第二導體層M2與第一透明電極層TE1共同形成暴露出部分通道層CH的第一開口OP1，而第二導體層M2的第一端102a與第二端102b即位於第一開口OP1的相對兩側。From a structural point of view, in the present embodiment, the second conductor layer M2 and the first transparent electrode layer TE1 together form a first opening OP1 exposing a portion of the channel layer CH, and the first end 102a of the second conductor layer M2 is The second ends 102b are located on opposite sides of the first opening OP1.
另外一提的是，在本實施方式中，在形成第二導體層M2的同時，還可形成與第二導體層M2的第一端102a連接的資料線（未繪示），意即第二導體層M2的與資料線屬於同一膜層。In addition, in the embodiment, while forming the second conductor layer M2, a data line (not shown) connected to the first end 102a of the second conductor layer M2 may be formed, that is, the second The conductor layer M2 belongs to the same film layer as the data line.
由於，第二導體層M2與第一透明電極層TE1使用具有選擇性蝕刻，因此蝕刻第一透明電極層TE1時能確保第二導體層M2不會受到傷害。舉例而言，用以形成第二導體層M2與第一透明電極層TE1的微影蝕刻製程中的蝕刻步驟都是濕式蝕刻步驟，其中第二導體層M2使用鋁酸作為蝕刻液而第一透明電極層TE1使用草酸作為蝕刻液；或是用以形成第二導體層M2的微影蝕刻製程中的蝕刻步驟是乾式蝕刻步驟，而用以形成第一透明電極層TE1的微影蝕刻製程中的蝕刻步驟則是濕式蝕刻步驟，且使用草酸作為蝕刻液，但本發明不以此為限。Since the second conductive layer M2 and the first transparent electrode layer TE1 are selectively etched, it is ensured that the second conductive layer M2 is not damaged when the first transparent electrode layer TE1 is etched. For example, the etching step in the lithography etching process for forming the second conductor layer M2 and the first transparent electrode layer TE1 is a wet etching step, wherein the second conductor layer M2 is firstly treated with alumina acid as an etchant. The transparent electrode layer TE1 uses oxalic acid as an etching solution; or the etching step in the lithography etching process for forming the second conductive layer M2 is a dry etching step, and the lithography etching process for forming the first transparent electrode layer TE1 The etching step is a wet etching step, and oxalic acid is used as an etching liquid, but the invention is not limited thereto.
接著，請同時參照圖1F及圖1G，於第一透明電極層TE1上形成光電轉換層PS以及第二透明電極層TE2，其中第二透明電極層TE2的材質包括氧化銦錫、氧化銦鋅、氧化鋁鋅、氧化鋁銦、氧化銦、氧化鎵、奈米碳管、奈米銀顆粒、厚度小於60奈米(nm)的金屬或合金、有機透明導電材料、或其它適合的透明導電材料。具體而言，光電轉換層PS以及第二透明電極層TE2的製造方法包括以下步驟：首先，請先參照圖1F，於基板100上依序形成N型半導體材料層104a、本質半導體材料層104b、P型半導體材料層104c及透明導體材料層（未繪示）。在本實施方式中，本質半導體材料層104b的材料包括本質非晶矽，其中常用的製程氣體包括氫氣(H2 )與矽甲烷(SiH4 )。N型半導體材料層104a的材料包括N型摻雜非晶矽，其中常用的製程氣體包括磷化氫(PH3 )、氫氣(H2 )與矽甲烷(SiH4 )。P型半導體材料層104c的材料包括P型摻雜非晶矽，其中常用的製程氣體包括硼酸三甲酯、氫氣(H2 )與矽甲烷(SiH4 )。透明導體材料層的材料包括銦錫氧化物、銦鋅氧化物、鋁鋅氧化物或其他適合的透明導電材料，然上述材料並非用以限制本發明。Next, referring to FIG. 1F and FIG. 1G, a photoelectric conversion layer PS and a second transparent electrode layer TE2 are formed on the first transparent electrode layer TE1, wherein the material of the second transparent electrode layer TE2 includes indium tin oxide, indium zinc oxide, Alumina zinc, aluminum oxide indium, indium oxide, gallium oxide, carbon nanotubes, nano silver particles, metals or alloys having a thickness of less than 60 nanometers (nm), organic transparent conductive materials, or other suitable transparent conductive materials. Specifically, the method for manufacturing the photoelectric conversion layer PS and the second transparent electrode layer TE2 includes the following steps: First, referring to FIG. 1F, the N-type semiconductor material layer 104a and the intrinsic semiconductor material layer 104b are sequentially formed on the substrate 100. P-type semiconductor material layer 104c and transparent conductor material layer (not shown). In the present embodiment, the material of the intrinsic semiconductor material layer 104b includes an intrinsic amorphous germanium, and commonly used process gases include hydrogen (H 2 ) and germanium methane (SiH 4 ). The material of the N-type semiconductor material layer 104a includes an N-type doped amorphous germanium, and common process gases include phosphine (PH 3 ), hydrogen (H 2 ), and germanium methane (SiH 4 ). The material of the P-type semiconductor material layer 104c includes a P-type doped amorphous germanium, and common process gases include trimethyl borate, hydrogen (H 2 ), and germanium methane (SiH 4 ). The material of the transparent conductor material layer includes indium tin oxide, indium zinc oxide, aluminum zinc oxide or other suitable transparent conductive material, and the above materials are not intended to limit the present invention.
接著，圖案化所述透明導體材料層，以於P型半導體材料層104c上形成第二透明電極層TE2（如圖1F所示）。詳細而言，在本實施方式中，第二透明電極層TE2是透過第五道微影蝕刻製程而形成的，其中第五道微影蝕刻製程中的蝕刻步驟例如是濕式蝕刻步驟，蝕刻液例如包括草酸或鋁酸。Next, the transparent conductor material layer is patterned to form a second transparent electrode layer TE2 on the P-type semiconductor material layer 104c (as shown in FIG. 1F). In detail, in the embodiment, the second transparent electrode layer TE2 is formed through a fifth lithography process, wherein the etching step in the fifth lithography process is, for example, a wet etching step, an etchant For example, it includes oxalic acid or aluminum acid.
之後，請參照圖1G，圖案化N型半導體材料層104a、本質半導體材料層104b以及P型半導體材料層104c，以形成包括互相堆疊的N型半導體層106a、本質半導體層106b及P型半導體層106c的光電轉換層PS。換言之，在本實施方式中，光電轉換層PS包括N型半導體層106a、配置在N型半導體層106a上的本質半導體層106b及配置在本質半導體層106b上的P型半導體層106c。詳細而言，在本實施方式中，光電轉換層PS是透過第六道微影蝕刻製程而形成的，其中第六道微影蝕刻製程中的蝕刻步驟例如是乾式蝕刻步驟，乾式蝕刻氣體包括六氟化硫(SF6 )與氯氣(Cl2 )等氣體。另外，光電轉換層PS具有與第一透明電極層TE1相接觸的底面S1以及與第二透明電極層TE2相接觸的頂面S2。Thereafter, referring to FIG. 1G, the N-type semiconductor material layer 104a, the intrinsic semiconductor material layer 104b, and the P-type semiconductor material layer 104c are patterned to form an N-type semiconductor layer 106a, an intrinsic semiconductor layer 106b, and a P-type semiconductor layer including stacked on each other. Photoelectric conversion layer PS of 106c. In other words, in the present embodiment, the photoelectric conversion layer PS includes the N-type semiconductor layer 106a, the intrinsic semiconductor layer 106b disposed on the N-type semiconductor layer 106a, and the P-type semiconductor layer 106c disposed on the intrinsic semiconductor layer 106b. In detail, in the embodiment, the photoelectric conversion layer PS is formed through a sixth lithography etching process, wherein the etching step in the sixth lithography etching process is, for example, a dry etching step, and the dry etching gas includes six A gas such as sulfur fluoride (SF 6 ) and chlorine gas (Cl 2 ). Further, the photoelectric conversion layer PS has a bottom surface S1 that is in contact with the first transparent electrode layer TE1 and a top surface S2 that is in contact with the second transparent electrode layer TE2.
如上所述，在本實施方式中，第二透明電極層TE2是在形成光電轉換層PS之前形成，藉此可避免因先形成了光電轉換層PS，而使得在對透明導體材料層進行微影蝕刻製程時影響了本質半導體層106b的品質以及對第一透明電極層TE1與第二導體層M2造成破壞。從另一觀點而言，第六道微影蝕刻製程中所使用的蝕刻氣體不會與第一透明電極層TE1及通道層CH發生反應。也就是說，在本實施方式中，透過於第二導體層M2上形成第一透明電極層TE1，能夠避免第二導體層M2在用以形成光電轉換層PS的乾式蝕刻步驟中受到破壞。As described above, in the present embodiment, the second transparent electrode layer TE2 is formed before the photoelectric conversion layer PS is formed, whereby lithography of the transparent conductor material layer can be avoided by forming the photoelectric conversion layer PS first. The etching process affects the quality of the intrinsic semiconductor layer 106b and causes damage to the first transparent electrode layer TE1 and the second conductor layer M2. From another point of view, the etching gas used in the sixth lithography process does not react with the first transparent electrode layer TE1 and the channel layer CH. That is, in the present embodiment, by forming the first transparent electrode layer TE1 on the second conductor layer M2, it is possible to prevent the second conductor layer M2 from being damaged in the dry etching step for forming the photoelectric conversion layer PS.
另外，在本實施方式中，第一透明電極層TE1、光電轉換層PS及第二透明電極層TE2構成感測元件SE。具體而言，在本實施方式中，第一透明電極層TE1中與光電轉換層PS相接觸的部分用以作為感測元件SE的下電極，而第二透明電極層TE2用以作為感測元件SE的上電極。Further, in the present embodiment, the first transparent electrode layer TE1, the photoelectric conversion layer PS, and the second transparent electrode layer TE2 constitute the sensing element SE. Specifically, in the present embodiment, a portion of the first transparent electrode layer TE1 that is in contact with the photoelectric conversion layer PS is used as a lower electrode of the sensing element SE, and a second transparent electrode layer TE2 is used as a sensing element. The upper electrode of the SE.
進一步而言，如前文所述，由於第二導體層M2與第一透明電極層TE1是透過使用同一張光罩(即第四道光罩)而形成，且第二導體層M2與第一透明電極層TE1的材質皆具有導電性，而感測元件SE又形成於第二導體層M2上，意即第二導體層M2的第二端102b延伸至感測元件SE下方，因此主動元件TFT的汲極（即第二端102b）與感測元件SE的下電極（即部分的第一透明電極層TE1）電性連接。Further, as described above, the second conductive layer M2 and the first transparent electrode layer TE1 are formed by using the same photomask (ie, the fourth photomask), and the second conductor layer M2 and the first transparent electrode are formed. The material of the layer TE1 is electrically conductive, and the sensing element SE is formed on the second conductor layer M2, that is, the second end 102b of the second conductor layer M2 extends below the sensing element SE, so the 元件 of the active device TFT The pole (ie, the second end 102b) is electrically connected to the lower electrode of the sensing element SE (ie, a portion of the first transparent electrode layer TE1).
值得說明的是，如前文所述，由於第一透明電極層TE1能夠保護第二導體層M2在形成光電轉換層PS時不受到破壞，意即第一透明電極層TE1做為一種蝕刻保護層，且部分的第一透明電極層TE1得以作為感測元件SE的下電極，因此光電轉換層PS能夠完全且直接地與第一透明電極層TE1接觸，而使得感測元件SE之底部的感應面積(即光電轉換層PS與第一透明電極層TE1的接觸面積)能夠增加，也就是說感測元件SE之底部的感應面積實質上等於光電轉換層PS之底面S1的面積。It is to be noted that, as described above, the first transparent electrode layer TE1 can protect the second conductive layer M2 from being damaged when the photoelectric conversion layer PS is formed, that is, the first transparent electrode layer TE1 serves as an etching protection layer. And a part of the first transparent electrode layer TE1 is used as the lower electrode of the sensing element SE, so that the photoelectric conversion layer PS can completely and directly contact the first transparent electrode layer TE1, so that the sensing area of the bottom of the sensing element SE ( That is, the contact area of the photoelectric conversion layer PS and the first transparent electrode layer TE1 can be increased, that is, the sensing area of the bottom of the sensing element SE is substantially equal to the area of the bottom surface S1 of the photoelectric conversion layer PS.
接著，請參照圖1H，於基板100上形成保護層BP1，以覆蓋主動元件TFT及感測元件SE，其中保護層BP1具有第二開口OP2及第三開口OP3，第二開口OP2暴露部分的第一透明電極層TE1，而第三開口OP3暴露部分的第二透明電極層TE2。詳細而言，保護層BP1透過第七道微影蝕刻製程而形成。保護層BP1的材質包括氧化矽、氮化矽或氮氧化矽等無機材料或其他有機材料。Next, referring to FIG. 1H, a protective layer BP1 is formed on the substrate 100 to cover the active device TFT and the sensing element SE, wherein the protective layer BP1 has a second opening OP2 and a third opening OP3, and the second opening OP2 exposes a portion A transparent electrode layer TE1, and the third opening OP3 exposes a portion of the second transparent electrode layer TE2. In detail, the protective layer BP1 is formed through a seventh lithography process. The material of the protective layer BP1 includes an inorganic material such as cerium oxide, cerium nitride or cerium oxynitride or other organic materials.
接著，請參照圖1I，於保護層BP1上形成第三透明電極層TE3，其中第三透明電極層TE3透過第三開口OP3與第二透明電極層TE2接觸。詳細而言，第三透明電極層TE3透過第八道微影蝕刻製程而形成。第三透明電極層TE3的材質包括氧化銦錫、氧化銦鋅、氧化鋁鋅、氧化鋁銦、氧化銦、氧化鎵、奈米碳管、奈米銀顆粒、厚度小於60奈米(nm)的金屬或合金、有機透明導電材料、或其它適合的透明導電材料。另外，在本實施方式中，第三透明電極層TE3可作為用以與外部電路連接的連接線。Next, referring to FIG. 1I, a third transparent electrode layer TE3 is formed on the protective layer BP1, wherein the third transparent electrode layer TE3 is in contact with the second transparent electrode layer TE2 through the third opening OP3. In detail, the third transparent electrode layer TE3 is formed through an eighth lithography process. The material of the third transparent electrode layer TE3 includes indium tin oxide, indium zinc oxide, aluminum zinc oxide, aluminum oxide indium, indium oxide, gallium oxide, carbon nanotubes, nano silver particles, and a thickness of less than 60 nanometers (nm). Metal or alloy, organic transparent conductive material, or other suitable transparent conductive material. Further, in the present embodiment, the third transparent electrode layer TE3 can serve as a connection line for connection to an external circuit.
接著，請參照圖1J，於保護層BP1上形成第三導體層M3，其中第三導體層M3透過第二開口OP2與第一透明電極層TE1接觸。詳細而言，第三導體層M3透過第九道微影蝕刻製程而形成。第三導體層M3的材質可以是金屬材料，或可以是合金、金屬材料的氮化物、金屬材料的氧化物、金屬材料的氮氧化物、或是金屬材料與其它導電材料的堆疊層等的導電材料。另外，第三導體層M3於垂直投影方向上與主動元件TFT至少部分重疊。詳細而言，在本實施方式中，第三導體層M3於垂直投影方向上至少與主動元件TFT的通道層CH重疊。這是因為通道層CH的材質一般為具有光電轉換特性的半導體材料，若通道層CH未被有效遮蔽，則在照光時容易在通道層CH產生光載子，光載子會使通道導通，而將使主動元件TFT無法關閉而失去開關的功能。Next, referring to FIG. 1J, a third conductor layer M3 is formed on the protective layer BP1, wherein the third conductor layer M3 is in contact with the first transparent electrode layer TE1 through the second opening OP2. In detail, the third conductor layer M3 is formed through a ninth lithography process. The material of the third conductor layer M3 may be a metal material, or may be an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or a conductive layer of a metal material and other conductive materials. material. In addition, the third conductor layer M3 at least partially overlaps the active device TFT in the vertical projection direction. In detail, in the present embodiment, the third conductor layer M3 overlaps at least the channel layer CH of the active device TFT in the vertical projection direction. This is because the material of the channel layer CH is generally a semiconductor material having photoelectric conversion characteristics. If the channel layer CH is not effectively shielded, photocarriers are easily generated in the channel layer CH during illumination, and the photocarriers turn on the channel. The active element TFT will not be turned off and the function of the switch will be lost.
接著，請參照圖1K，在製作完第三導體層M3之後，於基板100上可更包括形成保護層BP2。保護層BP2覆蓋主動元件TFT以及感測元件SE，用以防止主動元件TFT以及感測元件SE受到外界之濕氣、熱量及雜訊等影響，並保護主動元件TFT以及感測元件SE免於外力的破壞。保護層BP2通常可以利用物理氣相沉積法或化學氣相沉積法全面性地沉積在基板100上。保護層BP2的材質例如是氧化矽、氮化矽、氮氧化矽等無機材料或有機材料。Next, referring to FIG. 1K, after the third conductive layer M3 is formed, the protective layer BP2 may be further formed on the substrate 100. The protective layer BP2 covers the active device TFT and the sensing element SE to prevent the active device TFT and the sensing element SE from being affected by external moisture, heat and noise, and protects the active device TFT and the sensing element SE from external forces. The destruction. The protective layer BP2 can be generally deposited on the substrate 100 in a comprehensive manner by physical vapor deposition or chemical vapor deposition. The material of the protective layer BP2 is, for example, an inorganic material such as cerium oxide, cerium nitride or cerium oxynitride or an organic material.
另外一提的是，於基板100上全面性地沉積保護層BP2後，可更包括在位於周邊區(非顯示區)內的保護層BP2中形成一接觸窗（未繪示），以作為連接例如是驅動晶片或軟性印刷電路等的外部電路之用。詳細而言，所述接觸窗透過第十道微影蝕刻製程而形成。In addition, after the protective layer BP2 is comprehensively deposited on the substrate 100, a contact window (not shown) may be formed in the protective layer BP2 located in the peripheral region (non-display area) as a connection. For example, it is used to drive an external circuit such as a chip or a flexible printed circuit. In detail, the contact window is formed through a tenth lithography process.
基於上述，藉由進行上述所有步驟（圖1A至圖1K）後，將可完成本發明之第一實施方式的光感測裝置10的製作。另外，在上述第一實施方式中，光感測裝置10藉由十道微影蝕刻製程即可完成製作。也就是說，與包括背通道蝕刻型態之主動元件的習知光感測裝置相比，光感測裝置10能夠透過較少的微影蝕刻製程數來製造，藉此可降低光罩的使用而降低製程複雜度及製程成本。Based on the above, the fabrication of the light sensing device 10 of the first embodiment of the present invention can be completed by performing all of the above steps (Figs. 1A to 1K). In addition, in the first embodiment described above, the photo sensing device 10 can be fabricated by a ten-dimensional lithography etching process. That is to say, the light sensing device 10 can be manufactured by a smaller number of lithography etching processes than the conventional light sensing device including the active device of the back channel etching type, thereby reducing the use of the reticle and reducing the use of the reticle. Process complexity and process cost.
圖2A至圖2G為本發明之第二實施方式的光感測裝置之製造流程的剖面示意圖。其中，圖2A為接續圖1E之後所進行的步驟。此外，第二實施方式和第一實施方式中相同或相類似之構件得以採用相同的材料或方法來進行，故下文中針對與第一實施方式相同的描述將不再贅述，而主要以第二實施方式與第一實施方式間的差異處進行說明。2A to 2G are schematic cross-sectional views showing a manufacturing flow of a photo sensing device according to a second embodiment of the present invention. 2A is a step performed subsequent to FIG. 1E. In addition, the same or similar components in the second embodiment and the first embodiment can be carried out by the same material or method, and therefore the same description as the first embodiment will not be described again, but mainly in the second. The difference between the embodiment and the first embodiment will be described.
首先，請參照圖2A，於基板100上形成先行保護層FBP，以覆蓋部分的第一透明電極層TE1。詳細而言，先行保護層FBP具有一開口OP，以暴露出部分的第一透明電極層TE1。在本實施方式中，先行保護層FBP是透過第五道微影蝕刻製程而形成。先行保護層FBP的材質包括氧化矽、氮化矽或氮氧化矽等無機材料或其他有機材料。First, referring to FIG. 2A, a preceding protective layer FBP is formed on the substrate 100 to cover a portion of the first transparent electrode layer TE1. In detail, the leading protective layer FBP has an opening OP to expose a portion of the first transparent electrode layer TE1. In the present embodiment, the advance protection layer FBP is formed by a fifth lithography process. The material of the first protective layer FBP includes inorganic materials such as cerium oxide, cerium nitride or cerium oxynitride or other organic materials.
接著，請同時參照圖2B及圖2C，於第一透明電極層TE1上形成光電轉換層PS以及第二透明電極層TE2。詳細而言，在本實施方式中，光電轉換層PS形成在先行保護層FBP的開口OP內且不與先行保護層FBP相接觸。另外，在本實施方式中，第二透明電極層TE2是透過第六道微影蝕刻製程而形成，而光電轉換層PS是透過第七道微影蝕刻製程而形成。另外，光電轉換層PS具有與第一透明電極層TE1相接觸的底面S1以及與第二透明電極層TE2相接觸的頂面S2。Next, referring to FIG. 2B and FIG. 2C, the photoelectric conversion layer PS and the second transparent electrode layer TE2 are formed on the first transparent electrode layer TE1. In detail, in the present embodiment, the photoelectric conversion layer PS is formed in the opening OP of the preceding protective layer FBP and is not in contact with the preceding protective layer FBP. In addition, in the present embodiment, the second transparent electrode layer TE2 is formed through a sixth lithography process, and the photoelectric conversion layer PS is formed through a seventh lithography process. Further, the photoelectric conversion layer PS has a bottom surface S1 that is in contact with the first transparent electrode layer TE1 and a top surface S2 that is in contact with the second transparent electrode layer TE2.
值得一提的是，如第一實施方式中所述，透過第二透明電極層TE2在光電轉換層PS之前形成，使得可避免在對透明導體材料層進行微影蝕刻製程時影響了本質半導體層106b的品質以及對第一透明電極層TE1與第二導體層M2造成破壞。另外，由於第七道微影蝕刻製程中所使用的蝕刻氣體不會與第一透明電極層TE1及通道層CH發生反應，故透過於第二導體層M2上形成第一透明電極層TE1，能夠避免第二導體層M2在用以形成光電轉換層PS的乾式蝕刻步驟中受到破壞。另外，由於第一透明電極層TE1能夠保護第二導體層M2在光電轉換層PS形成時不受到破壞，且部分的第一透明電極層TE1得以作為感測元件SE的下電極，因此光電轉換層PS能夠完全且直接地與第一透明電極層TE1接觸，而使得感測元件SE之底部的感應面積(即光電轉換層PS與第一透明電極層TE1的接觸面積)能夠增加，也就是說感測元件SE之底部的感應面積實質上等於光電轉換層PS之底面S1的面積。It is worth mentioning that, as described in the first embodiment, the second transparent electrode layer TE2 is formed before the photoelectric conversion layer PS, so that the intrinsic semiconductor layer is affected when the transparent conductive material layer is subjected to the photolithography etching process. The quality of 106b and damage to the first transparent electrode layer TE1 and the second conductor layer M2. In addition, since the etching gas used in the seventh lithography process does not react with the first transparent electrode layer TE1 and the channel layer CH, the first transparent electrode layer TE1 is formed on the second conductor layer M2. The second conductor layer M2 is prevented from being damaged in the dry etching step for forming the photoelectric conversion layer PS. In addition, since the first transparent electrode layer TE1 can protect the second conductor layer M2 from being damaged when the photoelectric conversion layer PS is formed, and a part of the first transparent electrode layer TE1 functions as a lower electrode of the sensing element SE, the photoelectric conversion layer The PS can completely and directly contact the first transparent electrode layer TE1, so that the sensing area of the bottom of the sensing element SE (ie, the contact area of the photoelectric conversion layer PS and the first transparent electrode layer TE1) can be increased, that is, the sense The sensing area at the bottom of the measuring element SE is substantially equal to the area of the bottom surface S1 of the photoelectric conversion layer PS.
接著，請參照圖2D，於基板100上形成保護層BP1。詳細而言，在本實施方式中，保護層BP1及先行保護層FBP共同具有第二開口OP2’，而保護層BP1還具有第三開口OP3，其中第二開口OP2’暴露部分的第一透明電極層TE1，而第三開口OP3暴露部分的第二透明電極層TE2。另外，在本實施方式中，保護層BP1是透過第八道微影蝕刻製程而形成。Next, referring to FIG. 2D, a protective layer BP1 is formed on the substrate 100. In detail, in the present embodiment, the protective layer BP1 and the preceding protective layer FBP have a second opening OP2', and the protective layer BP1 further has a third opening OP3, wherein the second opening OP2' exposes a portion of the first transparent electrode The layer TE1, and the third opening OP3 exposes a portion of the second transparent electrode layer TE2. Further, in the present embodiment, the protective layer BP1 is formed by an eighth lithography etching process.
接著，請參照圖2E，於保護層BP1上形成第三透明電極層TE3，其中第三透明電極層TE3透過第三開口OP3與第二透明電極層TE2接觸。詳細而言，在本實施方式中，第三透明電極層TE3是透過第九道微影蝕刻製程而形成。Next, referring to FIG. 2E, a third transparent electrode layer TE3 is formed on the protective layer BP1, wherein the third transparent electrode layer TE3 is in contact with the second transparent electrode layer TE2 through the third opening OP3. In detail, in the present embodiment, the third transparent electrode layer TE3 is formed by a ninth lithography process.
接著，請參照圖2F，於保護層BP1上形成第三導體層M3。詳細而言，在本實施方式中，第三導體層M3是透過第二開口OP2’與第一透明電極層TE1接觸。另外，在本實施方式中，第三導體層M3透過第十道微影蝕刻製程而形成。Next, referring to FIG. 2F, a third conductor layer M3 is formed on the protective layer BP1. In detail, in the present embodiment, the third conductor layer M3 is in contact with the first transparent electrode layer TE1 through the second opening OP2'. Further, in the present embodiment, the third conductor layer M3 is formed by a tenth pass lithography process.
接著，請參照圖2G，在製作完第三導體層M3之後，於基板100上更包括形成保護層BP2。如第一實施方式中所述，於基板100上全面性地沉積保護層BP2後，可更包括在位於周邊區(非顯示區)內的保護層BP2中形成一接觸窗（未繪示），以作為連接例如是驅動晶片或軟性印刷電路等的外部電路之用。詳細而言，在本實施方式中，所述接觸窗是透過第十一道微影蝕刻製程而形成。Next, referring to FIG. 2G, after the third conductor layer M3 is formed, the protective layer BP2 is further formed on the substrate 100. After the protective layer BP2 is comprehensively deposited on the substrate 100, as described in the first embodiment, the contact layer (not shown) may be formed in the protective layer BP2 located in the peripheral region (non-display region). It is used as an external circuit for connecting, for example, a driving chip or a flexible printed circuit. In detail, in the present embodiment, the contact window is formed through an eleventh lithography process.
基於上述，藉由進行上述所有步驟（圖2A至圖2G）後，將可完成本發明之第二實施方式的光感測裝置20的製作。另外，在上述第二實施方式中，雖然光感測裝置20需要透過進行十一道微影蝕刻製程來製作，但透過於第二導體層M2上設置具有導電性的第一透明電極層TE1，使得光感測裝置20中的感測元件SE的感應面積得以增加。Based on the above, the fabrication of the light sensing device 20 of the second embodiment of the present invention can be completed by performing all of the above steps (Figs. 2A to 2G). Further, in the second embodiment, the photo sensing device 20 is required to be formed by performing an eleven lithography process, but the first transparent electrode layer TE1 having conductivity is provided on the second conductor layer M2. The sensing area of the sensing element SE in the light sensing device 20 is increased.
圖3A至圖3K為本發明之第三實施方式的光感測裝置之製造流程的剖面示意圖。其中，圖3A為接續圖1A之後所進行的步驟。此外，第三實施方式和第一實施方式中相同或相類似之構件得以採用相同的材料或方法來進行，故下文中針對與第一實施方式相同的描述將不再贅述，而主要以第三實施方式與第一實施方式間的差異處進行說明。3A to 3K are schematic cross-sectional views showing a manufacturing flow of a photo sensing device according to a third embodiment of the present invention. FIG. 3A is a step performed subsequent to FIG. 1A. In addition, the same or similar components in the third embodiment and the first embodiment can be carried out by the same material or method, and therefore the same description as the first embodiment will not be described again, but mainly in the third. The difference between the embodiment and the first embodiment will be described.
首先，請參照圖3A，於第一導體層M1上依序形成閘極絕緣層GI及通道層CH。詳細而言，在本實施方式中，通道層CH的材質包括氧化銦鎵鋅（Indium-Gallium-Zinc Oxide，IGZO）、氧化鋅、氧化錫（SnO）、氧化銦鋅、氧化鎵鋅（Gallium-Zinc Oxide，GZO）、氧化鋅錫（Zinc-Tin Oxide，ZTO）或氧化銦錫等的氧化物半導體材料。另外，在本實施方式中，通道層CH是透過第二道微影蝕刻製程而形成。First, referring to FIG. 3A, a gate insulating layer GI and a channel layer CH are sequentially formed on the first conductor layer M1. In detail, in the present embodiment, the material of the channel layer CH includes Indium-Gallium-Zinc Oxide (IGZO), zinc oxide, tin oxide (SnO), indium zinc oxide, gallium zinc oxide (Gallium- Zinc Oxide, GZO), zinc oxide tin (Zinc-Tin Oxide, ZTO) or indium tin oxide oxide semiconductor materials. Further, in the present embodiment, the channel layer CH is formed by a second lithography etching process.
另外一提的是，在本實施方式中，於閘極絕緣層GI上形成通道層CH後，可更包括於基板100的周邊區(非顯示區)內的閘極絕緣層GI中形成一接觸窗（未繪示），以於後續製程中形成用以與外部電路連接的連接線，其中外部電路例如是驅動晶片或軟性印刷電路。詳細而言，所述接觸窗是透過第三道微影蝕刻製程而形成。In addition, in the present embodiment, after the channel layer CH is formed on the gate insulating layer GI, a contact may be formed in the gate insulating layer GI in the peripheral region (non-display region) of the substrate 100. a window (not shown) for forming a connection line for connection with an external circuit in a subsequent process, such as a driver chip or a flexible printed circuit. In detail, the contact window is formed through a third lithography process.
接著，請參照圖3B，於通道層CH上形成蝕刻終止層ES，其中蝕刻終止層ES具有暴露出部分通道層CH的第一接觸洞V1與第二接觸洞V2。詳細而言，在本實施方式中，蝕刻終止層ES是透過第四道微影蝕刻製程而形成。蝕刻終止層ES的材質包括氧化矽等。Next, referring to FIG. 3B, an etch stop layer ES is formed on the channel layer CH, wherein the etch stop layer ES has a first contact hole V1 and a second contact hole V2 exposing a portion of the channel layer CH. In detail, in the present embodiment, the etch stop layer ES is formed by a fourth lithography process. The material of the etch stop layer ES includes ruthenium oxide or the like.
接著，請參照圖3C，於基板100上依序形成導體材料層M2’與透明電極材料層TE1’。基於導電性的考量，導體材料層M2’一般是使用金屬材料。然而，本發明並不限於此，導體材料層M2’也可以使用金屬材料以外的其他導電材料，例如：合金、金屬材料的氮化物、金屬材料的氧化物、金屬材料的氮氧化物、或是金屬材料與其它導電材料的堆疊層。透明電極材料層TE1’的材質包括氧化銦錫（ITO）、氧化銦鋅（IZO）、氧化鋁鋅（AlZO）、氧化鋁銦、氧化銦（InO）、氧化鎵（gallium oxide，GaO）、奈米碳管、奈米銀顆粒、厚度小於60奈米(nm)的金屬或合金、有機透明導電材料、或其它適合的透明導電材料。Next, referring to Fig. 3C, a conductor material layer M2' and a transparent electrode material layer TE1' are sequentially formed on the substrate 100. The conductor material layer M2' is generally made of a metal material based on conductivity considerations. However, the present invention is not limited thereto, and the conductive material layer M2' may also use other conductive materials other than the metal material, such as an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or A stacked layer of metallic material and other conductive materials. The material of the transparent electrode material layer TE1' includes indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AlZO), aluminum oxide indium, indium oxide (InO), gallium oxide (GaO), nai. Carbon nanotubes, nano-silver particles, metals or alloys having a thickness of less than 60 nanometers (nm), organic transparent conductive materials, or other suitable transparent conductive materials.
接著，請參照圖3D，於基板100上形成第一透明電極層TE1。詳細而言，在本實施方式中，第一透明電極層TE1的製造方法包括：利用一第五道光罩進行微影蝕刻製程，以將透明電極材料層TE1’圖案化而形成第一透明電極層TE1。另外，在本實施方式中，用以形成第一透明電極層TE1的微影蝕刻製程中的蝕刻步驟例如是濕式蝕刻步驟，蝕刻液例如是鋁酸。Next, referring to FIG. 3D, a first transparent electrode layer TE1 is formed on the substrate 100. In detail, in the present embodiment, the method of manufacturing the first transparent electrode layer TE1 includes: performing a photolithography process using a fifth mask to pattern the transparent electrode material layer TE1' to form a first transparent electrode layer. TE1. In addition, in the present embodiment, the etching step in the lithography etching process for forming the first transparent electrode layer TE1 is, for example, a wet etching step, and the etching liquid is, for example, aluminate.
接著，請參照圖3E，於基板100上形成第二導體層M2。詳細而言，在本實施方式中，部分的第一端102a及部分的第二端102b分別藉由第一接觸洞V1及第二接觸洞V2與通道層CH相接觸。也就是說，在本實施方式中，主動元件TFT的源極及汲極分別藉由第一接觸洞V1及第二接觸洞V2與通道層CH相接觸。具體而言，在本實施方式中，主動元件TFT屬於蝕刻阻擋層型態。Next, referring to FIG. 3E, a second conductor layer M2 is formed on the substrate 100. In detail, in the present embodiment, a portion of the first end 102a and a portion of the second end 102b are in contact with the channel layer CH by the first contact hole V1 and the second contact hole V2, respectively. That is, in the present embodiment, the source and the drain of the active device TFT are in contact with the channel layer CH through the first contact hole V1 and the second contact hole V2, respectively. Specifically, in the present embodiment, the active device TFT belongs to an etch barrier type.
另外，第一透明電極層TE1接觸第二導體層M2，以及第二導體層M2與第一透明電極層TE1具有相同的圖案。換言之，第一透明電極層TE1完全覆蓋該第二導體層M2，意即前述兩者實質上面積大小相同。具體而言，在本實施方式中，第二導體層M2的製造方法包括：同樣利用用以形成第一透明電極層TE1的同一張光罩(即所述第五道光罩)進行微影蝕刻製程，以將導體材料層M2’圖案化而形成第二導體層M2。進一步而言，在本實施方式中，用以形成第二導體層M2的微影蝕刻製程中的蝕刻步驟可以是濕式蝕刻步驟或乾式蝕刻步驟，其中當蝕刻步驟為濕式蝕刻步驟時，蝕刻液例如是草酸。從另一觀點而言，第二導體層M2與第一透明電極層TE1共同形成暴露出部分蝕刻終止層ES的第一開口OP1，而第二導體層M2的第一端102a與第二端102b即位於第一開口OP1的相對兩側。In addition, the first transparent electrode layer TE1 contacts the second conductor layer M2, and the second conductor layer M2 has the same pattern as the first transparent electrode layer TE1. In other words, the first transparent electrode layer TE1 completely covers the second conductor layer M2, that is, the two are substantially the same in area. Specifically, in the present embodiment, the manufacturing method of the second conductor layer M2 includes: performing the lithography process using the same photomask (ie, the fifth reticle) for forming the first transparent electrode layer TE1. The second conductor layer M2 is formed by patterning the conductor material layer M2'. Further, in the embodiment, the etching step in the lithography etching process for forming the second conductor layer M2 may be a wet etching step or a dry etching step, wherein when the etching step is a wet etching step, etching is performed. The liquid is, for example, oxalic acid. From another point of view, the second conductor layer M2 and the first transparent electrode layer TE1 together form a first opening OP1 exposing a portion of the etch stop layer ES, and the first end 102a and the second end 102b of the second conductor layer M2 That is, on opposite sides of the first opening OP1.
由於，第二導體層M2與第一透明電極層TE1使用具有選擇性蝕刻，因此蝕刻第一透明電極層TE1時能確保第二導體層M2不會受到傷害。舉例而言，用以形成第二導體層M2與第一透明電極層TE1的微影蝕刻製程中的蝕刻步驟都是濕式蝕刻步驟，其中第二導體層M2使用鋁酸作為蝕刻液而第一透明電極層TE1使用草酸作為蝕刻液；或是用以形成第二導體層M2的微影蝕刻製程中的蝕刻步驟是乾式蝕刻步驟，而用以形成第一透明電極層TE1的微影蝕刻製程中的蝕刻步驟則是濕式蝕刻步驟，且使用草酸作為蝕刻液，但本發明不以此為限。Since the second conductive layer M2 and the first transparent electrode layer TE1 are selectively etched, it is ensured that the second conductive layer M2 is not damaged when the first transparent electrode layer TE1 is etched. For example, the etching step in the lithography etching process for forming the second conductor layer M2 and the first transparent electrode layer TE1 is a wet etching step, wherein the second conductor layer M2 is firstly treated with alumina acid as an etchant. The transparent electrode layer TE1 uses oxalic acid as an etching solution; or the etching step in the lithography etching process for forming the second conductive layer M2 is a dry etching step, and the lithography etching process for forming the first transparent electrode layer TE1 The etching step is a wet etching step, and oxalic acid is used as an etching liquid, but the invention is not limited thereto.
接著，請同時參照圖3F及圖3G，於第一透明電極層TE1上形成光電轉換層PS以及第二透明電極層TE2。詳細而言，在本實施方式中，第二透明電極層TE2是透過第六道微影蝕刻製程而形成，而光電轉換層PS是透過第七道微影蝕刻製程而形成。另外，光電轉換層PS具有與第一透明電極層TE1相接觸的底面S1以及與第二透明電極層TE2相接觸的頂面S2。Next, referring to FIG. 3F and FIG. 3G, the photoelectric conversion layer PS and the second transparent electrode layer TE2 are formed on the first transparent electrode layer TE1. In detail, in the present embodiment, the second transparent electrode layer TE2 is formed through a sixth lithography process, and the photoelectric conversion layer PS is formed through a seventh lithography process. Further, the photoelectric conversion layer PS has a bottom surface S1 that is in contact with the first transparent electrode layer TE1 and a top surface S2 that is in contact with the second transparent electrode layer TE2.
值得一提的是，如第一實施方式中所述，透過第二透明電極層TE2在光電轉換層PS之前形成，使得可避免在對透明導體材料層進行微影蝕刻製程時影響了本質半導體層106b的品質以及對第一透明電極層TE1與第二導體層M2造成破壞。另外，由於第七道微影蝕刻製程中所使用的蝕刻氣體不會與第一透明電極層TE1及通道層CH發生反應，故透過於第二導體層M2上形成第一透明電極層TE1，能夠避免第二導體層M2在用以形成光電轉換層PS的乾式蝕刻步驟中受到破壞。另外，由於第一透明電極層TE1能夠保護第二導體層M2在光電轉換層PS形成時不受到破壞，且部分的第一透明電極層TE1得以作為感測元件SE的下電極，因此光電轉換層PS能夠完全且直接地與第一透明電極層TE1接觸，而使得感測元件SE之底部的感應面積(即光電轉換層PS與第一透明電極層TE1的接觸面積)能夠增加，也就是說感測元件SE之底部的感應面積實質上等於光電轉換層PS之底面S1的面積。It is worth mentioning that, as described in the first embodiment, the second transparent electrode layer TE2 is formed before the photoelectric conversion layer PS, so that the intrinsic semiconductor layer is affected when the transparent conductive material layer is subjected to the photolithography etching process. The quality of 106b and damage to the first transparent electrode layer TE1 and the second conductor layer M2. In addition, since the etching gas used in the seventh lithography process does not react with the first transparent electrode layer TE1 and the channel layer CH, the first transparent electrode layer TE1 is formed on the second conductor layer M2. The second conductor layer M2 is prevented from being damaged in the dry etching step for forming the photoelectric conversion layer PS. In addition, since the first transparent electrode layer TE1 can protect the second conductor layer M2 from being damaged when the photoelectric conversion layer PS is formed, and a part of the first transparent electrode layer TE1 functions as a lower electrode of the sensing element SE, the photoelectric conversion layer The PS can completely and directly contact the first transparent electrode layer TE1, so that the sensing area of the bottom of the sensing element SE (ie, the contact area of the photoelectric conversion layer PS and the first transparent electrode layer TE1) can be increased, that is, the sense The sensing area at the bottom of the measuring element SE is substantially equal to the area of the bottom surface S1 of the photoelectric conversion layer PS.
接著，請參照圖3H，於基板100上形成保護層BP1，其中保護層BP1具有第二開口OP2及第三開口OP3，第二開口OP2暴露部分的第一透明電極層TE1，而第三開口OP3暴露部分的第二透明電極層TE2。詳細而言，在本實施方式中，保護層BP1是透過第八道微影蝕刻製程而形成。Next, referring to FIG. 3H, a protective layer BP1 is formed on the substrate 100, wherein the protective layer BP1 has a second opening OP2 and a third opening OP3, the second opening OP2 exposes a portion of the first transparent electrode layer TE1, and the third opening OP3 A portion of the second transparent electrode layer TE2 is exposed. In detail, in the present embodiment, the protective layer BP1 is formed by an eighth pass lithography process.
接著，請參照圖3I，於保護層BP1上形成第三透明電極層TE3，其中第三透明電極層TE3透過第三開口OP3與第二透明電極層TE2接觸。詳細而言，在本實施方式中，第三透明電極層TE3是透過第九道微影蝕刻製程而形成。Next, referring to FIG. 3I, a third transparent electrode layer TE3 is formed on the protective layer BP1, wherein the third transparent electrode layer TE3 is in contact with the second transparent electrode layer TE2 through the third opening OP3. In detail, in the present embodiment, the third transparent electrode layer TE3 is formed by a ninth lithography process.
接著，請參照圖3J，於保護層BP1上形成第三導體層M3，其中第三導體層M3透過第二開口OP2與第一透明電極層TE1接觸。詳細而言，第三導體層M3透過第十道微影蝕刻製程而形成。Next, referring to FIG. 3J, a third conductor layer M3 is formed on the protective layer BP1, wherein the third conductor layer M3 is in contact with the first transparent electrode layer TE1 through the second opening OP2. In detail, the third conductor layer M3 is formed through a tenth lithography process.
接著，請參照圖3K，在製作完第三導體層M3之後，於基板100上更包括形成保護層BP2。如第一實施方式中所述，於基板100上全面性地沉積保護層BP2後，可更包括在位於周邊區(非顯示區)內的保護層BP2中形成一接觸窗（未繪示），以作為連接例如是驅動晶片或軟性印刷電路等的外部電路之用。詳細而言，在本實施方式中，所述接觸窗是透過第十一道微影蝕刻製程而形成。Next, referring to FIG. 3K, after the third conductor layer M3 is formed, the protective layer BP2 is further formed on the substrate 100. After the protective layer BP2 is comprehensively deposited on the substrate 100, as described in the first embodiment, the contact layer (not shown) may be formed in the protective layer BP2 located in the peripheral region (non-display region). It is used as an external circuit for connecting, for example, a driving chip or a flexible printed circuit. In detail, in the present embodiment, the contact window is formed through an eleventh lithography process.
基於上述，藉由進行上述所有步驟（圖3A至圖3K）後，將可完成本發明之第三實施方式的光感測裝置30的製作。另外，在上述第三實施方式中，光感測裝置30藉由十一道微影蝕刻製程即可完成製作。也就是說，與包括蝕刻阻擋層型態之主動元件的習知光感測裝置相比，光感測裝置30能夠透過較少的微影蝕刻製程數來製造，藉此可降低光罩的使用而降低製程複雜度及製程成本。Based on the above, the fabrication of the photo sensing device 30 of the third embodiment of the present invention can be completed by performing all of the above steps (Figs. 3A to 3K). In addition, in the third embodiment described above, the photo sensing device 30 can be fabricated by an eleven lithography process. That is, the light sensing device 30 can be fabricated with fewer lithography processes than conventional light sensing devices including an etch stop type active device, thereby reducing the use of the reticle to reduce Process complexity and process cost.
綜上所述，在本發明的光感測裝置中，透過第二導體層上設置有第一透明電極層，且部分的第一透明電極層作為感測元件的下電極，使得第一透明電極層能夠保護第二導體層在形成光電轉換層的製程中不受到破壞，以及使得光電轉換層能夠完全且直接地與第一透明電極層接觸，因而提升感測元件的感應面積。In summary, in the light sensing device of the present invention, the first transparent electrode layer is disposed on the second conductor layer, and a portion of the first transparent electrode layer serves as a lower electrode of the sensing element, such that the first transparent electrode The layer can protect the second conductor layer from being damaged in the process of forming the photoelectric conversion layer, and enables the photoelectric conversion layer to completely and directly contact the first transparent electrode layer, thereby increasing the sensing area of the sensing element.
雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。The present invention has been disclosed in the above embodiments, but it is not intended to limit the invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
10、20、30‧‧‧光感測裝置
100‧‧‧基板
102a‧‧‧第一端
102b‧‧‧第二端
104a‧‧‧N型半導體材料層
104b‧‧‧本質半導體材料層
104c‧‧‧P型半導體材料層
106a‧‧‧N型半導體層
106b‧‧‧本質半導體層
106c‧‧‧P型半導體層
BP1、BP2‧‧‧保護層
CH‧‧‧通道層
ES‧‧‧蝕刻終止層
FBP‧‧‧先行保護層
GI‧‧‧閘極絕緣層
M1‧‧‧第一導體層
M2‧‧‧第二導體層
M2’‧‧‧導體材料層
M3‧‧‧第三導體層
OP1‧‧‧第一開口
10, 20, 30‧‧‧Light sensing device
100‧‧‧Substrate
102a‧‧‧ first end
102b‧‧‧second end
104a‧‧‧N type semiconductor material layer
104b‧‧‧Intrinsic semiconductor material layer
104c‧‧‧P type semiconductor material layer
106a‧‧‧N type semiconductor layer
106b‧‧‧ Essential semiconductor layer
106c‧‧‧P type semiconductor layer
BP1, BP2‧‧‧ protective layer
CH‧‧‧ channel layer
ES‧‧‧etch stop layer
FBP‧‧‧ first protective layer
GI‧‧‧ gate insulation
M1‧‧‧first conductor layer
M2‧‧‧Second conductor layer
M2'‧‧‧ conductor material layer
M3‧‧‧ third conductor layer
OP1‧‧‧ first opening
OP2、OP2’‧‧‧第二開口 OP2, OP2’‧‧‧ second opening
OP3‧‧‧第三開口 OP3‧‧‧ third opening
OP‧‧‧開口 OP‧‧‧ openings
PS‧‧‧光電轉換層 PS‧‧‧ photoelectric conversion layer
S1‧‧‧底面 S1‧‧‧ bottom
S2‧‧‧頂面 S2‧‧‧ top surface
SE‧‧‧感測元件 SE‧‧‧Sensor components
TE1‧‧‧第一透明電極層 TE1‧‧‧first transparent electrode layer
TE1’‧‧‧透明電極材料層 TE1'‧‧‧Transparent electrode material layer
TE2‧‧‧第二透明電極層 TE2‧‧‧Second transparent electrode layer
TE3‧‧‧第三透明電極層 TE3‧‧‧ third transparent electrode layer
TFT‧‧‧主動元件 TFT‧‧‧ active components
V1‧‧‧第一接觸洞 V1‧‧‧ first contact hole
V2‧‧‧第二接觸洞 V2‧‧‧Second contact hole
圖1A至圖1K為本發明之第一實施方式的光感測裝置之製造流程的剖面示意圖。 圖2A至圖2G為本發明之第二實施方式的光感測裝置之製造流程的剖面示意圖。 圖3A至圖3K為本發明之第三實施方式的光感測裝置之製造流程的剖面示意圖。1A to 1K are schematic cross-sectional views showing a manufacturing flow of a photo sensing device according to a first embodiment of the present invention. 2A to 2G are schematic cross-sectional views showing a manufacturing flow of a photo sensing device according to a second embodiment of the present invention. 3A to 3K are schematic cross-sectional views showing a manufacturing flow of a photo sensing device according to a third embodiment of the present invention.
10‧‧‧光感測裝置 10‧‧‧Light sensing device
100‧‧‧基板 100‧‧‧Substrate
102a‧‧‧第一端 102a‧‧‧ first end
102b‧‧‧第二端 102b‧‧‧second end
106a‧‧‧N型半導體層 106a‧‧‧N type semiconductor layer
106b‧‧‧本質半導體層 106b‧‧‧ Essential semiconductor layer
106c‧‧‧P型半導體層 106c‧‧‧P type semiconductor layer
BP1、BP2‧‧‧保護層 BP1, BP2‧‧‧ protective layer
CH‧‧‧通道層 CH‧‧‧ channel layer
GI‧‧‧閘極絕緣層 GI‧‧‧ gate insulation
M1‧‧‧第一導體層 M1‧‧‧first conductor layer
M2‧‧‧第二導體層 M2‧‧‧Second conductor layer
M3‧‧‧第三導體層 M3‧‧‧ third conductor layer
OP2‧‧‧第二開口 OP2‧‧‧ second opening
OP3‧‧‧第三開口 OP3‧‧‧ third opening
PS‧‧‧光電轉換層 PS‧‧‧ photoelectric conversion layer
SE‧‧‧感測元件 SE‧‧‧Sensor components
TE1‧‧‧第一透明電極層 TE1‧‧‧first transparent electrode layer
TE2‧‧‧第二透明電極層 TE2‧‧‧Second transparent electrode layer
TE3‧‧‧第三透明電極層 TE3‧‧‧ third transparent electrode layer
TFT‧‧‧主動元件 TFT‧‧‧ active components
Claims (15)
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| TW104137868A TWI596793B (en) | 2015-11-17 | 2015-11-17 | Light sensing device and method of manufacturing same |
| CN201511000665.3A CN105552086A (en) | 2015-11-17 | 2015-12-28 | Light sensing device and manufacturing method thereof |
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| CN108766989B (en) | 2018-06-01 | 2021-09-03 | 京东方科技集团股份有限公司 | Optical sensing device, manufacturing method thereof, display device and display equipment |
| CN109742126B (en) | 2019-01-11 | 2022-02-11 | 京东方科技集团股份有限公司 | Display substrate and preparation method thereof, display panel, and display device |
| CN111192889A (en) | 2020-01-07 | 2020-05-22 | 京东方科技集团股份有限公司 | Photodetector module, method for manufacturing the same, and photodetector substrate |
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| US6774396B1 (en) * | 1999-01-20 | 2004-08-10 | Lg Philips Lcd Co., Ltd. | Thin film transistor type optical sensor |
| JP2006343713A (en) * | 2005-06-09 | 2006-12-21 | Lg Philips Lcd Co Ltd | Liquid crystal display device, manufacturing method thereof, and image sensing method using liquid crystal display device |
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| TW201209783A (en) * | 2010-08-24 | 2012-03-01 | Chunghwa Picture Tubes Ltd | Photosensor array substrate and method for fabricating the same |
| US20130265166A1 (en) * | 2012-04-10 | 2013-10-10 | E Ink Holdings Inc. | Electric apparatus |
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| JPH0787243B2 (en) * | 1990-10-18 | 1995-09-20 | 富士ゼロックス株式会社 | Semiconductor device |
| JPH065834A (en) * | 1992-06-22 | 1994-01-14 | Fuji Xerox Co Ltd | Image sensor |
| JP2011091236A (en) * | 2009-10-23 | 2011-05-06 | Epson Imaging Devices Corp | Imaging device and x-ray imaging device |
| KR101094288B1 (en) * | 2010-01-27 | 2011-12-19 | 삼성모바일디스플레이주식회사 | X-ray detection device |
| CN103137641B (en) * | 2013-01-25 | 2015-10-21 | 北京京东方光电科技有限公司 | A kind of array base palte and preparation method thereof, X-ray flat panel detector |
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| US6774396B1 (en) * | 1999-01-20 | 2004-08-10 | Lg Philips Lcd Co., Ltd. | Thin film transistor type optical sensor |
| JP2006343713A (en) * | 2005-06-09 | 2006-12-21 | Lg Philips Lcd Co Ltd | Liquid crystal display device, manufacturing method thereof, and image sensing method using liquid crystal display device |
| JP2011227863A (en) * | 2010-03-31 | 2011-11-10 | Casio Comput Co Ltd | Optical sensor device and driving method for optical sensor device |
| TW201135697A (en) * | 2010-04-15 | 2011-10-16 | Chimei Innolux Corp | Pixel array substrate and driving method thereof |
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| US20130265166A1 (en) * | 2012-04-10 | 2013-10-10 | E Ink Holdings Inc. | Electric apparatus |
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| CN105552086A (en) | 2016-05-04 |
| TW201719918A (en) | 2017-06-01 |
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