TWI521379B - Layout encryption method and machine readable media - Google Patents

Description

Layout security method and machine readable media

Embodiments of the present invention are related to circuit security methods, and more particularly to a layout security method for securing circuits on at least one particular material layer in a layout, and related machine readable media.

Chemical Mechanical Polishing (CMP) is one of the processes in semiconductor manufacturing to achieve flattening to improve yield. In general, there is a corresponding density specification for semiconductor materials laid on layers of a wafer, such as a diffusion layer, a poly layer, and a metal layer. To ensure uniform distribution of materials in each floor plan. Moreover, as the precision of the process is getting higher and higher, the density specification for chemical mechanical polishing is becoming more and more strict, and it has become an important part that designers have to confirm in the design.

However, when the designer needs to integrate the separately purchased Intellectual Property into the original design, because the supplier of Zhizhicai will often consider the layout of each layer in the wisdom of the enterprise because of the consideration of trade secrets. The content of the diagram is provided directly to the designer. The designer can only get the model of the intellectual property with interface information and carry out rough integration and simulation until the wafer is sent to the fab and ready for production. The layout of the Zhizhicai is merged with other design layouts. At this time, the density specification of the chemical mechanical polishing process for the materials of each layer layout of the whole wafer is inspected. There is a situation in which there is a violation of the density specification of the chemical mechanical polishing process with other circuits, and the modification is often one. Large projects are time consuming and expensive; sometimes there is not enough time to test or correct them, resulting in a drop in yield.

In view of this, how to balance the trade secrets of Zhizhicai and the density specification test of the early chemical mechanical polishing process has become an urgent problem to be solved in this field.

In accordance with an exemplary embodiment of the present invention, a layout security method for securing circuitry on at least one particular material layer in a layout, and associated machine readable medium, are disclosed to address the above problems.

According to a first embodiment of the present invention, a layout security method for securing a circuit on at least one specific material layer in a layout includes: calculating one of at least one region of the specific material layer The circuit density is converted to an area; and the circuit of the at least one region of the particular material layer is replaced by a pattern having a particular shape and substantially the same as the converted area.

According to a second embodiment of the present invention, a machine readable medium is provided for storing a code that, when executed by a processor, causes the processor to perform a layout security method for Securing a circuit on at least one particular material layer in a layout, the method comprising the steps of: calculating a circuit density of at least one region of the particular material layer and converting it to an area; and The circuit of at least one region is replaced by a pattern having a specific shape and corresponding to the converted area.

The layout image secrecy method proposed by the invention not only prevents others from knowing the (circuit) structure of a specific material layer in the original layout map, but also preserves the density information as much as possible, so as to facilitate the verification of the density specification and the obtained inspection. The result is a certain degree of precision.

S102~S110‧‧‧Steps

400‧‧‧ computer system

402‧‧‧Processor

404‧‧‧ machine readable media

1 is a flow chart of an exemplary embodiment of a floor plan secrecy method of the present invention.

Figure 2 is a schematic illustration of a diffusion layer in a layout.

Figure 3 is a schematic diagram of a diffusion layer after a confidential process in a layout.

Figure 4 is a schematic diagram of an embodiment of a computer system for performing the floor plan security method of the present invention.

Certain terms are used throughout the description and following claims to refer to particular elements. It should be understood by those of ordinary skill in the art that manufacturers may refer to the same elements by different nouns. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to".

1 is a flow chart of an exemplary embodiment of a layout privacy method of the present invention. The layout security method is used to perform security processing on at least one specific material layer in a layout. For example, the layout may be an Ethernet physical layer wafer layout. The figure, and the particular material, can be a diffusion layer, a poly layer, or a metal layer. After the security of the layout security method is processed, the information of each region density can be kept as much as possible, so that the density specification verification can be performed, but the structure of the original circuit cannot be known. However, the above is for illustrative purposes only and the invention is not limited thereto. If the same result is generally achieved, it does not necessarily need to be performed in the order of steps in the flow shown in FIG. 1, and the steps shown in FIG. 1 do not have to be performed continuously, that is, other steps may be inserted therein. . Moreover, some of the steps in FIG. 1 may be omitted in accordance with various embodiments or design requirements. The detailed steps of the layout security method of Fig. 1 are explained below.

First, at the beginning of the process of step S102, in addition to obtaining the layout map and determining the specific material layer to be processed (for example, only a part or all of the specific material layer in the layout image may be processed), It is necessary to have a fab's density specification for that particular material layer. For example, a fab's density specification for a 40 nm process diffusion layer is specified in a (specific) region of 150 microns by 150 microns. At least 20% or more and no more than 80% of the diffusion layer shall be contained, and the maximum width of the diffusion layer shall not exceed 75 microns and shall not be less than 5 microns. Next, in step S104, a specific region of the specific material layer of the layout map is determined according to at least one of a maximum width specification and a minimum width specification provided by the fab for the specific material layer. 150 micrometers by 150 micrometers are divided into a plurality of regions. Please refer to FIG. 2, which is a schematic diagram of a diffusion layer in a layout. The black square area is the portion of the diffusion layer that is retained. For example, when using the fab 40 nm process, the diffusion layer can be divided into 15 micrometers by 15 micrometer squares as shown in FIG. However, the above is only illustrative, and the invention is not limited thereto. For example, it may be divided into a square of 30 micrometers by 30 micrometers, or a rectangle of 15 micrometers by 30 micrometers. Basically, the purpose of this step is to reprocess the complete layer of the particular material at a coarser resolution, which is determined by the apparent density specification and the accuracy of the desired density information. That is to say, the resolution needs to be able to make the circuit on the specific material layer after the security processing is not recognizable or reversed, and at the same time, for the specific material layer after the security processing. The results obtained by the density specification test cannot be too much error (such as within 5% of the error) between the results obtained by performing the density specification test on the original material layer. Preferably, the particular region (e.g., 150 microns by 150 microns) is divided into a plurality of regions that are 4 times 4 (equal to 16) or more.

In step S106, a circuit density of each of the plurality of regions of the specific material layer is calculated and converted into an area, for example, for each 15 micron and 15 micrometer square regions in FIG. 2, respectively, the diffusion layer is calculated. Density, and converted to area. Next, please refer to Figure 3, Figure 3 is a schematic diagram of a diffusion layer after a confidential process in a layout. In step S108, the diffusion layer in each square region of 15 micrometers multiplied by 15 micrometers in FIG. 2 is replaced by substantially the same area (or density) corresponding to the corresponding conversion according to the converted area. The squares are placed at the respective center points of each 15 micron by 15 micrometer square area. However, the above is only for illustrative purposes, and the present invention is not limited thereto. For example, the diffusion layer in each square region of 15 micrometers multiplied by 15 micrometers in FIG. 2 may be replaced by the converted area. Correspondingly, the converted area (or density) is substantially the same as a rectangle or a circle, and is placed in the lower right corner of each of 15 micrometers by 15 micrometers. For example, the diffusion layer in each of the 15 micrometers by 15 micrometers in the square region in Fig. 2 may be replaced by substantially the same as the corresponding converted total area (or density) according to the converted area. A 7.5 micron multiplied by a 7.5 micron square area. In one embodiment, substantially the same means that the area of the two differs by less than 5%. The process ends when it is completed (step S110). The confidentially processed diffusion layer can be output as an electronic file and can be used for density specification testing.

Referring to FIG. 4, FIG. 4 is a schematic diagram of an embodiment of a computer system 400 for performing a floor plan security method of the present invention. The computer system 400 includes a processor 402 and a machine readable medium 404. For example, the computer system 400 can be a personal computer, and the machine readable medium 404 can be any storage device having a data storage function in a personal computer, such as volatilizing. Sexual memory, non-volatile memory, hard drive, CD, etc. In the present embodiment, a program code PROG is stored in the machine readable medium 404. Therefore, when the code PROG is loaded and executed by the processor 402, the code PROG causes the processor 402 to execute the present invention for a layout. The disclosed layout security method (ie, steps 102-110 shown in FIG. 1). Since those skilled in the art can easily understand the operations performed by the processor 502 executing the program code PROG after reading the above-mentioned contents for the timing analysis method, further description is omitted here for brevity.

The layout picture confidentiality method proposed by the invention not only prevents others from knowing the original cloth The structure of a particular material layer in the map can also maintain density information as much as possible to facilitate the verification of density specifications, to save time or cost, and to obtain a certain degree of accuracy.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

S102~S110‧‧‧Steps

Claims (11)

A layout security method for conserving a circuit on at least one specific material layer in a layout, comprising: calculating a circuit density of at least one region of a specific region of the specific material layer, and converting An area; and a circuit of the at least one region of the particular region of the particular material layer being replaced by a pattern having a particular shape and substantially the same as the scaled area. The method of claim 1, wherein the specific material layer is a diffusion layer. The method of claim 1, wherein the specific material layer is a poly layer. The method of claim 1, further comprising: determining, according to a maximum width specification of the specific material layer and at least one of a minimum width specification, the specific region of the specific material layer of the layout map Divided into a plurality of regions, wherein the regions include the at least one region. The method of claim 4, wherein the specific region of the specific material layer of the layout map is separately classified according to the maximum width specification of the specific material layer and at least one of the minimum width specifications. The steps of the regions include: dividing the specific region of the specific material layer of the layout into a plurality of rectangles having a side length between the maximum width specification and the minimum width specification as the regions. The method of claim 5, wherein the specific material layer of the layout map is respectively The step of dividing the specific area into a plurality of rectangles having a side length between the maximum width specification and the minimum width specification as the regions includes: dividing the specific area into at least 16 plural rectangles as the plurality of rectangles region. A machine readable medium storing a code that, when executed by a processor, causes the processor to perform a layout security method for securing at least one particular material in a layout a circuit on a layer, the method comprising the steps of: calculating a circuit density of at least one region of a particular region of the particular material layer and converting to an area; and the at least one of the particular region of the particular material layer The circuit of the region is replaced by a pattern having a specific shape and corresponding to the area being converted. The machine-readable medium of claim 7, wherein the method further comprises: selecting the specific material of the layout according to a maximum width specification of the specific material layer and a minimum width specification The specific regions of the layer are each divided into a plurality of regions, wherein the regions include the at least one region. The machine readable medium of claim 8, wherein the specific area of the specific material layer of the layout map is respectively determined according to the maximum width specification of the specific material layer and at least one of the minimum width specifications The step of dividing into the regions includes: dividing the specific region of the specific material layer of the layout map into a plurality of rectangles having a side length between the maximum width specification and the minimum width specification as the regions. The machine-readable medium of claim 9, wherein the specific area of the specific material layer of the layout map is respectively divided into a plurality of rectangles having a side length between the maximum width specification and the minimum width specification The steps to be the regions include: dividing the specific region into at least 16 plural rectangles as the regions. The machine readable medium of claim 10, wherein the area converted is within 5% of the area of the pattern.