TWI697987B - Resistive memory structure - Google Patents

Abstract

The present invention provides a resistive memory structure, including a composite substrate formed by a metal oxide semiconductor process, a composite material layer is formed on the composite substrate, the composite material layer has a unit cell area and a logic area, and a first shielding layer is formed on the composite substrate. In the material layer and on the combined substrate, the first shielding layer forms the unit cell area on the combined substrate, the second shielding layer is formed in the combined material layer, the combined substrate and the first shielding layer, and the first metal layer is provided on the second shielding Among the layers, the metal composite layer is located on the composite material layer. Compared with the conventional structure, the present invention can reduce at least one manufacturing process, and can reduce the damage caused by the conventional etching.

Description

Resistive memory structure

The present invention relates to a memory structure, in particular to a resistive memory structure after an improved manufacturing process.

Resistive components can be used as semiconductor switches or memory components. Memory devices are usually provided in integrated circuits in computers or other electronic devices. They are stored in different types of memory, including random access memory (RAM). , Read Only Memory (ROM), Static Random Access Memory (Static Random Access Memory, SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Flash Memory ( Flash Memory), resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), magnetoresistive random access memory (Magnetoresistive Random Access Memory, MRAM), etc.

In the application of semiconductor devices, many circuit components can be packaged in a single small area to form an integrated circuit (IC). With the size change of the integrated circuit, users need to set the component circuit components or component devices in a limited range. In the range of space, it becomes very important to make effective and accurate formation or isolation between circuit elements.

Non-volatile resistive random access memory, hereinafter referred to as resistive memory, which stores data by changing the resistance of a resistive element. Resistive memory has characteristics that exceed other types of memory devices, such as low power Consumption, high speed and better bit resolution. Here, because of the separation between the high resistance state and the low resistance and the relatively large resistance ratio, the read or write cycle durability of the charge storage type memory is not limited.

Please refer to the first figure, the conventional resistive memory 10 can be formed by a general standard complementary metal-oxide-semiconductor (Complementary Metal-Oxide-Semiconductor, CMOS) process to form the contact layer 12, and then the IMD0 material is deposited , Then the pattern of the first metal layer 14 is manufactured by the yellow light lithography/etching process, and the first metal layer is covered by the physical vapor deposition (Physical Vapor Deposition, PVD)/atomic layer deposition technology (Atomic Layer Deposition, ALD) and electroplating The wafer is then polished and flattened by Chemical-Mechanical Planarization (CMP), and the subsequent process of forming the first metal layer 14 of copper is completed according to the Back End Of Line (BEOL), and the There is a second metal layer 16 and a third metal layer 18, and a resistance change layer is provided between the second metal layer 16 and the third metal layer 18 to deposit the resistance change layer of the resistive memory 10, for example, using physical gas Phase deposition (Physical Vapor Deposition, PVD)/Atomic Layer Deposition (Atomic Layer Deposition, ALD), and then the resistance change layer pattern of the resistive memory 10 is manufactured through a yellow light lithography (Photo)/etching (Etch) process, and a The unit cell of the RRAM, for example, can be composed of a transistor and a variable resistance element.

However, in the conventional resistive memory structure, the unit cell of the resistive memory is fabricated on the channel layer (Via). When fabricating upwards, at least two masks are required for connection. In addition, when a resistive switching element needs to be added in the upward manufacturing, dry etching (Dry Etch) will erode the surrounding cell area.

Therefore, in order to improve the deficiency of the conventional resistive memory structure, the present invention proposes an innovative resistive memory structure to improve the deficiency of the conventional technology.

The main purpose of the present invention is to provide a resistive memory structure, which utilizes structural improvements so that at least one mask can be reduced in the manufacturing process, reducing the time and steps of manufacturing, and through the reduction of process steps, the process time is also reduced. Failure to happen can also bring cost savings to users.

Another object of the present invention is to provide a resistive memory structure. In addition to the difference in structure, chemical mechanical planarization and polishing can also be used to replace the conventional resistive memory structure using dry etching technology to reduce Damage to the unit cell.

In order to achieve the above objective, the present invention provides a resistive memory structure, which includes a composite substrate formed by a metal oxide semiconductor process, and a composite material layer is formed flat on the composite substrate by deposition, photolithography, and etching. The material layer has at least one unit cell area and at least one logic area. At least one first shielding layer is formed in the combined material layer and on the combined substrate. The first shielding layer makes the unit cell area formed in the combined material layer and on the combined substrate. At least one second shielding layer is formed in the composite material layer, on the composite substrate and the first shielding layer, at least two first metal layers are disposed in the second shielding layer, and at least one metal composite layer is located on the composite material layer.

In the present invention, the first metal layer is copper, cobalt, or aluminum metal or a combination thereof.

In the present invention, the combined substrate includes at least two contact layers and a plurality of electronic components. The contact layers are arranged corresponding to at least one first shielding layer and at least one second shielding layer and connected to them. The electronic components can be located on the two contact layers respectively. side.

In the present invention, the electronic component is a metal oxide semiconductor field effect transistor.

In the present invention, after the composite material layer is formed on the composite substrate, it can be polished by chemical mechanical planarization, and after at least two first metal layers are disposed on the at least one second shielding layer, they can be polished by chemical mechanical planarization.

In the present invention, the first metal layer is formed by electroplating or physical vapor deposition (Physical Vapor Deposition, PVD).

In the present invention, the first shielding layer includes an upper electrode layer, a lower electrode layer and a resistive memory layer, and the resistive memory layer is disposed between the upper electrode layer and the lower electrode layer.

In the present invention, the metal combination layer further includes a first channel layer (Via 1) on the first metal layer and a second metal layer on the first channel layer.

In the present invention, at least one second channel layer and at least one third metal layer may be stacked on the second metal layer. The second channel layer is located on the second metal layer, and the third metal layer is located on the second metal layer. On the channel layer.

In the present invention, the second shielding layer can be selectively disposed on the first shielding layer.

Detailed descriptions are given below with specific embodiments and accompanying drawings, so that it is easier to understand the purpose, technical content, characteristics and effects of the present invention.

The resistive memory structure proposed by the present invention is different from the conventional resistive memory structure. By simplifying the manufacturing process and reducing a mask, the structure is different, and the conventional resistive memory can be prevented from being etched on the cell layer. The damage brought by it provides a more competitive resistive memory structure.

First, referring to the second figure of the present invention, a resistive memory structure 20 includes a composite substrate 22, a composite material layer 24, at least one first shielding layer 26, at least one second shielding layer 27, and at least a second shielding layer. One metal layer 28 and at least one metal combination layer 30. In this embodiment, the number of at least two first metal layers 28 is four as an example, and at least one metal combination layer 30 is three as an example. The combined material layer 24 is located on the combined substrate 22, at least one first shielding layer 26 is formed in the combined material layer 24 and on the combined substrate 22, and the first shielding layer 26 is formed in the unit cell region 242 in the combined material layer 24, At least one second shielding layer 27 is formed in the combined material layer 24, the combined substrate 22 and the first shielding layer 26. In this embodiment, there are three first shielding layers 26, so that the displayed unit cell area 242 is three, and the second shielding layer 27 is four, so that the displayed logic area can be one, but the present invention is not limited to this number. The composite substrate 22 also includes at least two contact layers ( Contact) 222 and a plurality of electronic components 224. Each first shielding layer 26 or each second shielding layer 27 corresponds to a contact layer 222 of the combined substrate 22 and is connected to the contact layer 222, while the electronic components 224 are respectively They are arranged on both sides of the contact layer 222, but are not limited thereto. In this embodiment, the number of electronic components 224 is four, such as four as an example, but the present invention is not limited to these numbers. The first metal layer 28 is disposed on the second shielding layer 27 in the cell region 242 and the logic region 244. In the present invention, the number of the metal combination layer 30 does not have to be the same as the first metal layer 28, but these metal combinations The layer 30 is located on the composite material layer 24, and the metal composite layer 30 further includes a first channel layer (Via) 302 located on the first metal layer 28, and a second metal layer 304 located on the first channel layer At 302, in addition, at least one second channel layer 306 and at least one third metal layer 308 may be stacked on the second metal layer 304. In this embodiment, the second channel layer 306 is located on the second metal layer 304 , The third metal layer 308 is located on the second channel layer 306. However, the present invention is not limited to this. For example, the second metal layer may also have a plurality of third metal layers located on the second channel layer, which means that there is a second channel layer on the second metal layer and a The third metal layer can have a new second channel layer on the third metal layer, and a new third metal layer on it, and so on.

Following the previous paragraph, in the present invention, the first metal layer 28 is made of copper (Cu), cobalt (Co), or aluminum (Al) metal or a combination of metals, and the above-mentioned electronic component 224 may be a metal oxide semiconductor field effect transistor. (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET). In addition, please refer to the fourth figure of the present invention. The first shielding layer 26 includes an upper electrode layer 32, a lower electrode layer 34 and a resistive memory layer 36, but the present invention is not limited to these structures. The resistive memory layer 36 is disposed between the upper electrode layer 32 and the lower electrode layer 34, and the second shielding layer 27 may be a combination layer of tantalum (Ta) and tantalum nitride (TaN), but the present invention is not The restriction of the first shielding layer 26 or the second shielding layer 27.

After describing the structure of the present invention, the process method of how to fabricate the resistive memory structure of the present invention will be described in detail, and please refer to the third a to third i and the second diagram. First, referring to the third figure a, the composite substrate 22 is provided first. The contact layers 222 and the electronic components 224 are formed by a standard metal oxide semiconductor (MOS) process, such as a CMOS process. Next, in the third figure b, a material layer 38 of IMD0 material is deposited on the combined substrate 22, and in the third figure c, a unit cell lithography/etching process is performed on the material layer 38, and unnecessary PR materials are removed. In the third figure d, the upper electrode layer, the resistive memory layer material, and the lower electrode layer are deposited to form the unit cell region 242 and the first shielding layer 26 in the combined material layer 24. The shielding layer 26 forms a groove shape in the cell region 242, and after the first shielding layer 26 is formed, the first shielding layer 26 on the composite material layer 24 will be removed by chemical-mechanical planarization (CMP). As shown in the third e figure. Then, as shown in the third figure f, the yellow light lithography/etching process is performed from the logic region 244 in the combined material layer 24, and then the material is deposited to form the second shielding layer 27 in the logic region 244 in the combined material layer 24 And the second shielding layer 27 can be selectively correspondingly disposed on the first shielding layer 26. In the third g figure, the material for the first metal layer 28 is filled on the second shielding layer 27, and then in the third h figure, the excess material of the second shielding layer 27 is smoothed by chemical mechanical planarization to The first metal layer 28 is disposed in the second shielding layer 27, and copper is mainly formed in the second shielding layer 27 by electroplating, and then the excess copper is smoothed by CMP to form the first metal layer 28. Finally, as shown in the third figure i, the metal combination layer 3 can be formed on part of the first metal layer 28, which can then be completed by a standard BEOL process, which can be determined according to the user’s design. The present invention does not limit the subsequent Process.

From the resistive memory structure disclosed in the present invention, it can be clearly known that the first metal layer (M1) in the unit cell layer is obviously different from the conventional metal layer (M1). There is a first shielding layer and a second shielding layer, in addition to the difference in structure, it is also obvious from the manufacturing process that the present invention can reduce at least one photomask manufacturing process compared with the conventional resistive memory structure to form the RRAM cell Area, and can avoid the damage of dry etching to the cell area.

Therefore, the resistive memory structure provided by the present invention can replace the conventional structure, provide users with more competitive resistive memory devices, can improve the production yield, or even reduce the production cost. The present invention is more helpful To enhance the competitiveness of the industry.

The above-mentioned embodiments are only to illustrate the technical ideas and features of the present invention. Their purpose is to enable those who are familiar with the art to understand the content of the present invention and implement them accordingly. When they cannot be used to limit the patent scope of the present invention, That is, all equal changes or modifications made in accordance with the spirit of the present invention should still be covered by the patent scope of the present invention.

10: Resistive memory 12: Contact layer 14: The first metal layer 16: second metal layer 18: The third metal layer 20: Resistive memory structure 22: Combined substrate 222: contact layer 224: electronic components 24: Combined material layer 242: unit cell area 244: logical area 26: The first shielding layer 27: second shielding layer 28: The first metal layer 30: Metal combination layer 302: The first channel layer 304: second metal layer 306: second channel layer 308: third metal layer 32: Upper electrode layer 34: Lower electrode layer 36: Resistive memory layer 38: Material layer

The first figure is a schematic diagram of a conventional resistive memory structure. The second figure is a schematic diagram of the resistive memory structure of the present invention. The third a to the third i are schematic diagrams of each step of the manufacturing process of the resistive memory structure of the present invention. The fourth figure is a schematic diagram of the structure of the first shielding layer in the present invention.

20: Resistive memory structure

22: Combined substrate

222: contact layer

224: electronic components

24: Combined material layer

242: unit cell area

244: logical area

26: The first shielding layer

27: second shielding layer

28: The first metal layer

30: Metal combination layer

302: The first channel layer

304: second metal layer

306: second channel layer

308: third metal layer

Claims (9)

A resistive memory structure includes: a combined substrate formed by a metal oxide semiconductor process; a combined material layer formed on the combined substrate by deposition, yellow light lithography, and etching. The material layer has at least one unit cell area and at least one logic area; at least one first shielding layer is formed in the composite material layer and on the composite substrate, and the first shielding layer forms the at least one unit cell area On the composite substrate; at least one second shielding layer, which is formed in the composite material layer, on the composite substrate and the at least one first shielding layer; at least two first metal layers, which are each provided on the at least A second shielding layer; and at least one metal combination layer located on the combination material layer; wherein the first shielding layer includes an upper electrode layer, a lower electrode layer and a resistive memory layer, the resistive memory The body layer is arranged between the upper electrode layer and the lower electrode layer; wherein, the first shielding layer is in the at least one unit cell region and does not exceed the surface of the composite material layer. The resistive memory structure according to claim 1, wherein the first metal layer is copper (Cu), cobalt (Co), or aluminum (Al) metal or a composite metal thereof. The resistive memory structure according to claim 1, wherein the composite substrate includes at least two contact layers and a plurality of electronic components, and the at least two contact layers correspond to at least one first shielding layer and at least one second shield The layers are arranged and connected, and the electronic components are respectively located on two sides of the contact layers. The resistive memory structure according to claim 1, wherein after the composite material layer is formed on the composite substrate, it can be flattened by chemical-mechanical planarization (CMP). The resistive memory structure according to claim 1, wherein after each of the at least two first metal layers is disposed on the at least one second shielding layer, they can be flattened by chemical mechanical planarization. The resistive memory structure according to claim 1, wherein the at least two first metal layers are formed by electroplating or physical vapor deposition (Physical Vapor Deposition, PVD). The resistive memory structure of claim 1, wherein the metal combination layer further includes: a first channel layer located on the first metal layer; and a second metal layer located on the first metal layer On the channel layer. The resistive memory structure according to claim 8, wherein at least one second channel layer and at least one third metal layer can be stacked on the second metal layer, and the second channel layer is located on the second metal The third metal layer is located on the second channel layer. The resistive memory structure according to claim 1, wherein the at least one second shielding layer can be selectively disposed on the at least one first shielding layer.

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