TWI701835B - High electron mobility transistor - Google Patents

Abstract

A High Electron Mobility Transistor (HEMT) includes a buffer layer having a Group-III-element nitride disposed on the substrate, a channel layer disposed on the buffer layer having the Group-III-element nitride, a barrier layer disposed on the channel layer, a source/a drain disposed on the barrier layer and separated with each other, and a gate structure disposed on the barrier layer and between the source and the drain. The gate structure includes a first GaN layer disposed on the barrier layer, wherein the first GaN layer is unintentionally doped, a second GaN layer disposed on the first GaN layer and having a conductivity-type dopant including a first metal element, a metal nitride layer disposed on the second GaN layer and having a second metal element identical to the first metal element, and a gate electrode disposed on the second GaN layer.

Description

High electron mobility transistor

This disclosure is about a semiconductor device and its manufacturing method. In particular, it relates to a High Electron Mobility Transistor (HEMT) and its manufacturing method.

The high electron mobility transistor has the characteristics of a larger band gap, a higher breakdown voltage (and a higher.) and a higher saturation voltage (saturation voltage), so it has high temperature resistance, The effect of high voltage, high current density and high frequency operation; mainly used in power circuits as high power switches or radio frequency components.

A typical high electron mobility transistor, taking the semiconductor aluminum gallium nitride/gallium nitride (AlGaN/GaN) high electron mobility transistor as an example, is based on the heterojunction of aluminum gallium nitride/gallium nitride (heterojunction). ) Structure, a high polarization field is generated between the source and drain, so that electrons are highly accumulated near the interface between the upper aluminum gallium nitride layer and the lower gallium nitride layer to form two-dimensional electrons Gas (Two Dimensional Electron Gas, 2DEG) channel.

However, the high electron mobility transistor is usually a normally-on (depletion mode) device. Therefore, an additional negative bias is needed to make In addition to the relatively inconvenient use of the closed component, it also limits the scope of use of the component. In order to solve this problem, Enhancement-mode high electron mobility transistors have been proposed, which utilizes the formation of nitrogen with high concentration of P-type impurities on the aluminum gallium nitride/gallium nitride heterojunction structure. The gallium nitride layer forms a PN junction with the aluminum gallium nitride layer below; or before the metal gate is formed, bombardment with fluorine ions is used to destroy the lattice structure of the aluminum gallium nitride layer; or etching the aluminum gallium nitride layer A recess is formed in the layer, and a metal gate is formed at the bottom of the recess. By thinning the aluminum gallium nitride layer under the metal gate, the two-dimensional electron gas can be turned off without applying additional bias. Normally-off mode components.

However, the above methods have their own technical bottlenecks. For example, when an etching process is used to form a cavity structure to increase the breakdown voltage of a high electron mobility transistor, it is difficult to control the thickness of the aluminum gallium nitride layer at the bottom of the cavity within a specific range because the etching accuracy is not easy to control. The pinch-off voltage between the same high-electron mobility transistor components has a great variation. Due to the small atomic size of fluorine, high electron mobility transistors bombarded by fluorine ions can easily diffuse out of the aluminum gallium nitride layer under long-term high temperature and high pressure operation, which makes it easy to make enhanced high electron mobility transistors The component is reversed into a depletion type component, causing the overall circuit to fail. In addition, the method of forming the P-type doped gallium nitride layer on the aluminum gallium nitride/gallium nitride layer is difficult to control the diffusion depth of the doping process, and it is easy to diffuse high-concentration P-type impurities, such as magnesium ions. Entering the active region and channel layer underneath causes the threshold voltage of the high electron mobility transistor to drift, and then atypical behavior occurs; the device is prone to failure under long-term operation.

Therefore, there is a need to provide an advanced high electron mobility transistor and a manufacturing method thereof to solve the problems faced by the conventional technology.

An embodiment of this specification discloses a High Electron Mobility Transistor device, including: a substrate, a buffer layer, a channel layer, a barrier layer, a source, a Drain and a gate structure. The buffer layer is located on the substrate and has Group-III-element nitride. The channel layer is located on the buffer layer and has group III element nitrides. The barrier layer is located on the channel layer. The source is located on the barrier layer. The drain is located on the barrier layer and isolated from the source. The gate structure is located on the barrier layer and between the source and the drain. The gate structure includes a first gallium nitride layer, a second gallium nitride layer, a metal nitride layer, and a gate electrode layer. The first gallium nitride layer is located on the barrier layer, and the first gallium nitride layer is not intentionally doped with impurities. The second gallium nitride layer is located on the first gallium nitride layer and has a conductive type impurity containing a first metal element. A metal nitride layer is located on the second gallium nitride layer and has a second metal element; wherein the second metal element is the same as the first metal element of the conductive impurity. The gate electrode layer is located on the second gallium nitride layer.

Another embodiment of this specification discloses a high electron mobility transistor device, including: a substrate, a buffer layer, a channel layer, an aluminum gallium nitride barrier layer, a source, a drain, and a gate极结构。 The structure. The buffer layer is located on the substrate and has a group III element nitride. The channel layer is located on the buffer layer and has a third group element nitrogen Chemical. The aluminum gallium nitride barrier layer is on the channel layer. The source is located on the barrier layer. The drain is located on the barrier layer and isolated from the source. The gate structure is located on the barrier layer and between the source and drain. The gate structure includes: a first gallium nitride layer, a first metal nitride layer, a second gallium nitride layer, and a gate electrode layer. The first gallium nitride layer is located on the aluminum gallium nitride barrier layer and has a conductivity type impurity. The first metal nitride layer is located on the first gallium nitride layer. The second gallium nitride layer is located on the first metal nitride layer and has this conductivity type impurity. The gate electrode layer is located on the second gallium nitride layer. Wherein, a part of the first gallium nitride layer is projected on the edge of the first gallium nitride layer from the gate electrode layer, and extends toward the source and drain directions respectively.

Another embodiment of this specification discloses a high electron mobility transistor device, including: a substrate, a buffer layer, a channel layer, a first barrier layer, a second barrier layer, a source electrode, a Drain and a gate structure. The buffer layer is located on the substrate and has group III element nitrides. The channel layer is located on the buffer layer. The first barrier layer is located on the channel layer. The second barrier layer is located on the first barrier layer. The source is located on the first barrier layer. The drain is located on the first barrier layer and is isolated from the source. The gate structure is located on the first barrier layer and between the source and the drain. The gate structure includes: a first gallium nitride layer, a second gallium nitride layer, and a gate electrode layer. The first gallium nitride layer is located on the first barrier layer and has p-type conductivity. The second gallium nitride layer is located on the first barrier layer and has p-type conductivity, wherein the area of the first gallium nitride layer is larger than that of the second gallium nitride layer, and the first gallium nitride layer faces the source and Extend in the drain direction. Wherein, the second barrier layer covers a part of the first gallium nitride layer and the second gallium nitride layer, exposing another part of the second gallium nitride layer, and the gate electrode layer is formed on the second nitride layer. The gallium oxide layer is exposed on the outer part.

An embodiment of the present specification is to provide a high electron mobility transistor and a manufacturing method thereof, by forming a first gallium nitride layer including a first gallium nitride layer stacked sequentially over a buffer layer, a channel layer, and a barrier layer , A gate structure of a second gallium nitride layer, a metal nitride layer and a gate electrode layer. And make the second gallium nitride layer have a plurality of conductivity type impurities. After that, the source and drain electrodes that are isolated from each other are formed on the barrier layer, so that the gate structure is located between the source and the drain to form an enhanced high electron mobility transistor.

In an embodiment of this specification, the first gallium nitride layer is not intentionally doped with impurities. In the process of making high electron mobility transistors, the first gallium nitride layer that is not deliberately doped with impurities is used as the buffer layer, and the metal atoms of the metal nitride layer are diffused to the first nitrogen that is not deliberately doped with impurities. The gallium nitride layer is formed to form the second gallium nitride layer, and the doping depth of the doping process for forming the second gallium nitride layer can be accurately grasped. It can prevent the conventional technology from directly growing a P-type electrical gallium nitride layer on the barrier layer and diffusing P-type impurities into the barrier layer and the buffer layer, causing the problem of the overall circuit failure.

In another embodiment of this specification, the first gallium nitride layer and the second gallium nitride layer are composed of gallium nitride with the same conductivity type impurity; and the first stacked layer has an extension, which is formed by the gate The edges of the electrode layer projected on the first gallium nitride layer respectively extend toward the source and drain directions. The electrons accumulated in the two-dimensional electron gas channel on the heterojunction of the buffer layer and the barrier layer can be exhausted during the forward operation, and the current collapse phenomenon of the high electron mobility transistor element can be prevented. In the reverse operation, it is easier to form a depletion zone in the channel region, to suppress the leakage current of the gate electrode, and to increase the breakdown voltage of the high electron mobility transistor element. In addition, in the process of making the first gallium nitride layer, the metal nitride layer (aluminum nitride layer) below it is used as an etching stop layer to pattern the doped gallium nitride layer, which can precisely control the etching process. In order to make the patterned first gallium nitride layer have a desired thickness. It can effectively expand the processing window of the high electron mobility transistor device.

In another embodiment of this specification, the first gallium nitride layer and the second gallium nitride layer are composed of gallium nitride with the same conductivity type impurity; and the first stacked layer has an extension, which is formed by the gate The edge of the electrode layer projected on the first gallium nitride layer extends toward the source and drain directions respectively; and a second barrier layer with the same material as the barrier layer is additionally formed to cover the first gallium nitride layer and the second barrier layer. A part of the gallium nitride layer exposes another part of the second gallium nitride layer, and the gate electrode layer is formed on the exposed part of the second gallium nitride layer. In this way, the extension of the first gallium nitride layer provides an additional electric field to increase the width of the depletion region between the drain and the gate, thereby alleviating the peak electric field at the edge of the gate and effectively improving the high electron mobility electric field. The breakdown voltage of the crystal element, and reduce the gate leakage current.

100, 200, 300, 400, 500, 600, 700: high electron mobility transistor components

101, 401: substrate

102, 402: channel layer

103, 403: barrier layer

104, 204, 304, 412, 712: gate structure

105: Gallium nitride layer without deliberate doping of impurities

105A: first aluminum gallium nitride layer

105B: second aluminum gallium nitride layer

106, 206, 306: metal nitride layer

106a: Magnesium ion

106b, 206b: opening

107: Heat treatment process

108, 208, 308: gate electrode layer

109A, 413A: source

109B, 413B: drain

110: buffer layer

111: etching process

311: third gallium nitride layer

404: First P-type GaN layer

404A: Patterned first P-type gallium nitride layer

404A1: Stacking section

404A2: Extension

404A3: Edge

405: first aluminum nitride layer

405A: Patterned first aluminum nitride layer

406: second P-type gallium nitride layer

406A: Patterned second P-type gallium nitride layer

407, 707: gate electrode layer

408: The first etching process

409: The second etching process

410, 701, 710: patterned photoresist

411: The third etching process

414: passivation layer

515: patterned second metal nitride layer

716: second barrier layer

In order to have a better understanding of the above and other aspects of this specification, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows:

Figures 1A to 1E are schematic cross-sectional diagrams of a series of process structures for fabricating high electron mobility transistors according to an embodiment of this specification; Figure 2 is a schematic diagram of a series of process structures drawn according to another embodiment of this specification A cross-sectional view of the structure of a high-electron mobility transistor device; Figure 3 is a cross-sectional view of the structure of a high-electron mobility transistor device according to another embodiment of this specification; Figures 4A to 4E are schematic cross-sectional diagrams of a series of process structures for fabricating high electron mobility transistor devices according to yet another embodiment of this specification; Figure 5 is a schematic diagram of a series of process structures according to yet another embodiment of this specification A cross-sectional view of the structure of a high electron mobility transistor device shown

Figures 6A to 6B are schematic cross-sectional diagrams of part of the process structure for fabricating a high electron mobility transistor device according to another embodiment of this specification; and Figures 7A to 7C are based on another embodiment of this specification. A cross-sectional schematic diagram of a part of the process structure for manufacturing a high electron mobility transistor device shown in an embodiment.

This manual provides a method for manufacturing high electron mobility transistor components, which can increase the breakdown voltage of high electron mobility transistor components, reduce gate leakage current, and effectively expand the manufacturing process margin of high electron mobility transistor components . In order to make the above-mentioned embodiments and other purposes, features, and advantages of this specification more comprehensible, a plurality of embodiments are specifically listed below in conjunction with the accompanying drawings for detailed description.

However, it must be noted that these specific implementation cases and methods are not intended to limit the present invention. The present invention can still be implemented using other features, elements, methods and parameters. The presenting of the preferred embodiments is only used to illustrate the technical features of the present invention, and not to limit the scope of patent application of the present invention. Those with ordinary knowledge in this technical field will be able to follow the description of the following specification without departing from the essence of the present invention Make equal modifications and changes within the scope of God. In the different embodiments and drawings, the same elements will be represented by the same element symbols.

Please refer to FIG. 1A to FIG. 1E. FIG. 1A to FIG. 1E are cross-sectional schematic diagrams of a series of process structures for manufacturing a high electron mobility transistor 100 according to an embodiment of the present specification. In this embodiment, the method of manufacturing the high electron mobility transistor 100 includes the following steps:

First, a substrate 101 is provided, and a buffer layer 110 and a channel layer 102 with a group III element nitride are formed on the substrate 101. After that, a first barrier layer 103 with a group III element nitride is formed on the channel layer 102 (as shown in FIG. 1A). In some embodiments of this specification, the substrate 101 may be a semiconductor substrate, an insulating substrate, a plasticized substrate, or a composite substrate. The semiconductor substrate includes a silicon substrate, a GaN substrate, or a SiC substrate; the insulating material includes a sapphire substrate, or a glass substrate. The plasticized substrate includes polyimide (PI) and polyethylene naphthalate (polyethylene naphthalate two formic acid glycol ester, PEN) or polyethylene terephthalate (polyethylene terephthalate, PET) and other substrates, wherein the plasticized substrate can have flexible characteristics; the composite substrate includes silicon and SOI substrate (silicon on insulator) composed of insulators. The group III element nitride constituting the buffer layer 110 and the channel layer 102 may be a group III-nitride semiconductor material, including aluminum nitride (AlN), gallium nitride (GaN) or aluminum gallium nitride ( Aluminum Gallium nitride, AlGaN).

In this embodiment, the substrate 101 may be a silicon substrate or an SOI substrate, and the thickness of the silicon substrate may be between 200 nanometers (nm) and 2 centimeters (millimeter, mm). The buffer layer 110 includes gallium nitride, aluminum gallium nitride or the above combination. The channel layer is made of gallium nitride; the barrier layer 103 is made of aluminum gallium nitride semiconductor material. The thickness of the buffer layer 110 can range from 10 nanometers (nm) to 100 microns (micrometer, μm); the thickness of the channel layer 102 can range from 10 nanometers (nm) to 10 microns (micrometer, μm). ); the thickness of the first barrier layer 103 can be between 1 nanometer (nm) and 100 nanometers.

Next, a gate structure 104 is formed on the barrier layer 103. In some embodiments of this specification, the manufacturing method of the gate structure 104 includes the following steps: Referring to FIG. 1B, firstly form the barrier layer 103 in sequence A gallium nitride layer 105 that is not intentionally doped with impurities and a metal nitride layer 106. Among them, the gallium nitride layer 105 that is not deliberately doped with impurities is a semiconductor layer, and the semiconductor material it contains is an intrinsic semiconductor. The gallium nitride layer 105 that is not deliberately doped with impurities is not doped during the epitaxial process. Impurities, but may contain essential impurities of the material. The thickness of the gallium nitride layer 105 that is not deliberately doped with impurities is substantially between 40 nanometers (nm) and 100 nanometers. In some embodiments of this specification, the thickness of the gallium nitride layer 105 that is not intentionally doped with impurities is preferably greater than 60 nm. Preferably it is 70 nm.

After that, referring to FIG. 1C, at least one heat treatment process 107 is performed, so that the metal atoms 106a in the metal nitride layer 106 diffuse into the gallium nitride layer 105 that is not intentionally doped with impurities. Among them, the metal atoms of the metal nitride layer 106 include magnesium (Mg), beryllium (Be), calcium (Ca), zinc (Zn), etc., which can form a p-type nitride material. In this embodiment, the metal nitride layer 106 is a magnesium nitride layer, and the depth and range of the diffusion of a plurality of magnesium atoms 106a into the gallium nitride layer 105 without intentional doping of impurities can be determined by the temperature and time of the heat treatment process 107 Effective control and adjustment can prevent magnesium atoms from diffusing into the barrier layer 103 and the channel layer 102, causing external defects to capture carriers during 2DEG transmission. In this embodiment, by disposing the gallium nitride layer 105 without intentional impurity doping under the metal nitride layer 106 and in contact with the barrier layer 103, in the heat treatment process 107, after magnesium atoms 106a diffuse, the original The unintentionally doped gallium nitride layer 105 is transformed into a first gallium nitride layer 105A composed of unintentionally doped gallium nitride that does not substantially contain magnesium atom diffusion 106a, and a first gallium nitride layer 105A located in the first nitride On the gallium layer 105A, the second gallium nitride layer 105B (as shown in FIG. 1C) is composed of gallium nitride containing magnesium atoms 106a (P-type conductivity). In this embodiment, the thickness of the metal nitride layer 106 is substantially between 3 nanometers and 20 nanometers. The thickness of the first gallium nitride layer 105A that is not deliberately doped with impurities can be between 1 nanometer and 20 nanometers; the thickness of the second gallium nitride layer 105B can be between 40 nanometers and 80 nanometers; And the second gallium nitride layer 105B has a doping concentration of magnesium atoms substantially between 5E18 pieces/cm ³ to 1E20 pieces/cm ³ .

After the heat treatment process 107, a patterning process, such as a reactive ion etching (RIE) process, is performed on the magnesium nitride layer 106, the second gallium nitride layer 105B, and the first gallium nitride layer 105A to combine a Part of the barrier layer 103 is exposed to the outside. After that, another etching process 111 may be selectively used to pattern the magnesium nitride layer 106 to form an opening 106b in the magnesium nitride layer 106, exposing a part of the second gallium nitride layer 105B to the outside, (eg (Shown in Figure 1D). In the step of the etching process 111, the thickness of the magnesium nitride layer 106 can be used to determine whether an opening is required. In one embodiment, the thickness of the magnesium nitride layer 106 is about 3 to 5 nm, and the opening 106b step may not be performed.

Next, a metal deposition process is performed on the patterned magnesium nitride layer 106, and the opening 106b is filled with a metal material, such as titanium (Ti), tungsten (W), or other metals and alloys thereof, to form a gate electrode in the opening 106b Layer 108 and form an ohmic contact with the second gallium nitride 105B to complete the fabrication of the gate structure 104 Made. Subsequently, a source 109A and a drain 109B isolated from each other are formed on the barrier layer 103, and an ohmic contact is formed with the barrier layer 103, and the gate structure 104 is located between the source 109A and the drain 109B. The preparation of the high electron mobility transistor 100 shown in Figure 1E.

Wherein, the source electrode 109A and the drain electrode 109B may include a titanium aluminum (TiAl) alloy. It should be noted that although in this embodiment, the source electrode 109A and the drain electrode 109B are formed behind the gate electrode layer 108. However, in some embodiments of this specification, the source electrode 109A and the drain electrode 109B may also be formed before the gate electrode layer 108. In other embodiments, due to the thermal budget for forming the source 109A and drain 109B and the gate electrode layer 108, it is sufficient to drive the plurality of magnesium ions 106a in the magnesium nitride layer 106 into nitrogen that is not intentionally doped with impurities. The top of the gallium layer 105. Therefore, the heat treatment process 107 can be omitted.

In this embodiment, the PIN junction formed by the second gallium nitride layer 105B, the gallium nitride layer 105A, and the channel layer 102 can increase the threshold voltage during forward operation and increase the stability under long-term operation.性; In the reverse operation can significantly reduce the leakage path of the high electron mobility transistor 100 and increase the breakdown voltage. In addition, in the process of fabricating the high electron mobility transistor 100, a gallium nitride layer 105 without intentional doping with impurities is formed between the magnesium nitride layer 106 and the barrier layer 103, and then the nitrogen is removed by heat treatment. The magnesium ions of the magnesium sulfide layer 106 diffuse into the gallium nitride layer 105 without deliberately doping impurities to form a second gallium nitride layer 105B made of gallium nitride with P-type electrical properties. Compared with the prior art, which directly grows a P-type electrical gallium nitride layer on the barrier layer 103, this embodiment can more accurately control the doping depth of the P-type impurity and avoid the diffusion of magnesium ions into the active region and the channel ( The barrier layer 103 and the channel layer 102). In addition, the magnesium nitride layer 106 can provide protection for the second gallium nitride layer 105B during the manufacturing process, avoiding The surface of the second gallium nitride layer 105B is exposed to the atmosphere, which helps to improve the process yield of the high electron mobility transistor 100.

However, the arrangement of the gate structure in the high electron mobility transistor is not limited to this. For example, please refer to FIG. 2. FIG. 2 is a cross-sectional view of a high electron mobility transistor 200 according to another embodiment of the present specification. The structure of the high electron mobility transistor 200 is substantially similar to the structure and manufacturing process of the high electron mobility transistor 100 shown in FIG. 1D. The difference between the two is that the gate electrode layer 208 is not in direct contact with the second gallium nitride layer 105B below.

In this embodiment, due to the process of forming the opening 206b, the opening 206b does not completely penetrate the metal nitride layer 206, such as a magnesium nitride layer. Therefore, the gate electrode layer 208 subsequently formed in the opening 206b still retains a part of the magnesium nitride layer 206 underneath it, and does not directly contact the second gallium nitride layer 105B. Such an arrangement of the gate structure 204 can prevent leakage current from the gate electrode layer 208 during the operation of the high electron mobility transistor 200 and increase the reliability of the operation of the high electron mobility transistor 200.

Please refer to FIG. 3. FIG. 3 is a cross-sectional view of a high electron mobility transistor 300 according to another embodiment of the present specification. The structure of the high electron mobility transistor 300 is substantially similar to the structure and manufacturing process of the high electron mobility transistor 100 shown in FIG. 1D. The difference between the two is that the gate structure 304 of the high electron mobility transistor 300 further includes a third gallium nitride layer 311 located between the magnesium nitride layer 306 and the gate electrode layer 308.

In this embodiment, a metal nitride layer 306, such as a magnesium nitride layer, is formed between the third gallium nitride layer 311 and the gallium nitride layer 105 without intentional impurity doping shown in FIG. 1B, and then By the thermal process 107, the magnesium ions in the magnesium nitride layer 306 are brought down and Diffuse upward into the gallium nitride layer 105 and the third gallium nitride layer 311, so that the two layers are diffused by magnesium ions into the second gallium nitride layer 105B and the third gallium nitride layer 311 with P-type electrical properties , And a part of the first gallium nitride layer 105A that is not deliberately doped with impurities remains. In one embodiment, the magnesium ions contained in the third gallium nitride layer 311 near the magnesium nitride layer 306 are higher than the magnesium contained in the third gallium nitride layer 311 away from the magnesium nitride layer 306. ion. When the high electron mobility transistor 300 is operating, the third gallium nitride layer 311 with P-type conductivity has the effect of suppressing the leakage current of the gate electrode layer 308, which can increase the operation of the high electron mobility transistor 300. Reliability.

Please refer to FIG. 4A to FIG. 4E. FIG. 4A to FIG. 4E are cross-sectional schematic diagrams of a series of process structures for fabricating a high electron mobility transistor 400 according to another embodiment of this specification. In this embodiment, the method of manufacturing the high electron mobility transistor 400 includes the following steps:

First, a substrate 401 is provided, and a buffer layer 110 and a channel layer 402 with semiconductor group III element nitrides are sequentially formed on the substrate 401. After that, a first barrier layer 403 with group III element nitride is formed on the channel layer 402. In some embodiments of this specification, the substrate 401 may be a semiconductor substrate, an insulating substrate, a plasticized substrate, or a composite substrate. The semiconductor substrate includes a silicon substrate, a GaN substrate, or a SiC substrate; the insulating material includes a sapphire substrate, or a glass substrate. The plasticized substrate includes polyimide (PI) and polyethylene naphthalate (polyethylene naphthalate two formic acid glycol ester, PEN) or polyethylene terephthalate (polyethylene terephthalate, PET) and other substrates, wherein the plasticized substrate can have flexible characteristics; the composite substrate includes silicon and SOI substrate (silicon on insulator) composed of insulators.

In this embodiment, the substrate 401 may be a silicon substrate or an SOI substrate. The buffer layer 110 includes gallium nitride, aluminum gallium nitride, or a combination thereof. The channel layer 402 is made of gallium nitride; the first barrier layer 403 is made of aluminum gallium nitride. The thickness of the buffer layer 110 can be between 10 nanometers and 100 microns; the thickness of the channel layer 402 can be between 10 nanometers and 10 microns; the thickness of the first barrier layer 403 can be between 1 nanometers and 100 microns. Between nanometers.

Thereafter, a semiconductor stack of a first P-type gallium nitride layer 404, a first metal nitride layer 405, and a second P-type gallium nitride layer 406 are sequentially formed on the first barrier layer 403. After that, a gate electrode layer 407 is formed on the second P-type gallium nitride layer 406 (as shown in FIG. 4A). In some embodiments of the present specification, the first metal nitride layer 405 may include aluminum nitride. The thickness of the first P-type gallium nitride layer 404 may be between 1 nanometer and 3 nanometers. The thickness of the first metal nitride layer 405 can be between 1 nanometer and 3 nanometers; the thickness of the second P-type gallium nitride layer 406 can be between 30 nanometers and 100 nanometers.

Next, using the gate electrode layer 407 as an etching mask and the first metal nitride layer 405 as an etching stop layer, a first etching process 408 is performed, thereby patterning the second P-type gallium nitride layer 406. After removing a part of the second P-type gallium nitride layer 406, a part of the first metal nitride layer 405 is exposed to the outside (as shown in FIG. 4B).

Using the gate electrode layer 407 and the patterned second P-type gallium nitride layer 406 as an etching mask, and the first P-type gallium nitride layer 404 as an etching stop layer, a second etching process 409 is performed, thereby patterning The first metal nitride layer 405. After removing a portion of the first metal nitride layer 405, a portion of the first P-type gallium nitride layer 404 is exposed to the outside (as shown in FIG. 4C).

Then, using the patterned photoresist 410 as an etching mask, and the first barrier layer 403 as an etching stop layer, a third etching process 411 is performed to pattern the first P-type gallium nitride layer 404. After removing a part of the first P-type gallium nitride layer 404, a part of the first barrier layer 403 is exposed to the outside to form a gate structure 412 as shown in FIG. 4D. In some embodiments of the present specification, the gate structure 412 includes a patterned first P-type gallium nitride layer 404A, a patterned first metal nitride layer 405A, and a patterned second P-type nitride layer. Gallium layer 406A and gate electrode layer 407. The planar size of the patterned first P-type gallium nitride layer 404A is substantially larger than that of the patterned first metal nitride layer 405A, the patterned second P-type gallium nitride layer 406A, and the gate electrode layer 407 plane size.

In detail, after the first etching process 408 and the second etching process 409, the patterned first metal nitride layer 405A, the patterned second P-type gallium nitride layer 406A, and the gate electrode layer 407 are three Have the same plane size or similar shape. In one embodiment, the patterned first metal nitride layer 405A, the patterned second P-type gallium nitride layer 406A, and the gate electrode layer 407 have overlapping edges. The patterned first P-type gallium nitride layer 404A includes a stack portion 404A1 and an extension portion 404A2. The stacked portion 404A1 is substantially aligned and overlapped with the patterned first metal nitride layer 405A, the patterned second P-type gallium nitride layer 406A, and the gate electrode layer 407. The extension 404A2 is projected from the gate electrode layer 407 (the patterned first metal nitride layer 405A and the patterned second P-type gallium nitride layer 406A) on the patterned first P-type gallium nitride layer The edge 404A3 on 404A extends a certain distance outward. For example, in this embodiment, the extension 404A2 is formed by the gate electrode layer 407, the patterned first metal nitride layer 405A, or the patterned second P-type gallium nitride layer 406A. The edge 404A3 projected on the patterned first P-type gallium nitride layer 404A extends outward about 8 to 12 microns.

Subsequently, a source 413A and a drain 413B isolated from each other are formed on the first barrier layer 403, so that the gate structure 412 is located between the source 413A and the drain 413B. A passivation layer 414 is formed to cover a portion of the first barrier layer 403 exposed to the outside, and the preparation of the high electron mobility transistor 400 as shown in FIG. 4E is completed. In this embodiment, the source electrode 413A and the drain electrode 413B may be respectively about 3 microns away from the extension 404A2 of the patterned first P-type gallium nitride layer 404A.

In this embodiment, the patterned first P-type gallium nitride layer 404A is placed on the first barrier layer 403, which helps to pass the first barrier layer during the reverse operation. 403 and the electrons trapped at the interface between the first P-type gallium nitride layer 404A and the first barrier layer 403 are guided to the gate electrode 407, thereby reducing the current collapse of the high electron mobility transistor 400 phenomenon. During the reverse operation, a local depletion region is formed between the first barrier layer 403 and the channel layer 402 under the extension 404A2, so that the leakage current of the gate structure 412 can be suppressed and the high electron mobility transistor 400 can be improved The breakdown voltage.

In the process of fabricating the gate structure 412, by forming a first metal nitride layer 405 under the second P-type gallium nitride layer 406 as an etch stop layer, the etchant is applied to the second P-type gallium nitride layer during the etching process. The gallium nitride layer 406 and the first metal nitride layer 405 have different etching rates, and the etching depth of the first etching process 408 can be controlled more accurately, so that the patterned second P-type gallium nitride layer 406A Have the expected thickness. In one embodiment, aluminum nitride is selected as the first gold For the material of the nitride layer 405, the etching rate of the etchant on the second P-type gallium nitride layer 406 is greater than that of the first metal nitride layer 405, which can avoid over-etching. By the same principle, a suitable etchant can also be selected to effectively control the etching depth of the second etching process 409, so that the patterned first metal nitride layer 405A also has a desired thickness. By the same principle, the etching depth of the third etching process 411 can also be effectively controlled, so that the patterned first P-type gallium nitride layer 404A has a desired thickness, thereby expanding the manufacturing process of the high electron mobility transistor 400 Margin. In an embodiment, the first metal nitride layer 405 may be formed between the gate electrode layer 407 and the patterned second P-type gallium nitride layer 406A, and the material of the first metal nitride layer 405 includes aluminum nitride And gallium nitride.

Please refer to FIG. 5. FIG. 5 is a structural cross-sectional view of a high electron mobility transistor 500 according to yet another embodiment of the present specification. The structure of the high electron mobility transistor 500 is similar to the structure of the high electron mobility transistor 400 depicted in FIG. 4E. The difference is that the high electron mobility transistor 500 further includes a second The metal nitride layer 515.

In this embodiment, in order to more accurately control the thickness of the patterned first P-type gallium nitride layer 404A. In some implementations of this specification, before forming the first P-type gallium nitride layer 404, it is preferable to form a second metal nitride layer on the first barrier layer 403 so that the second metal nitride layer is located on the first barrier layer 403. Between a barrier layer 403 and the first P-type gallium nitride layer 404 formed subsequently. While patterning the first P-type gallium nitride layer 404, a part of the second metal nitride layer is removed by the third etching process 411 to form a patterned second metal nitride layer 515. The patterned second metal nitride layer 515 and the patterned first The P-type gallium nitride layer 404A has the same planar size. In one embodiment, the step of forming the patterned second metal nitride layer 515 is separated from the third etching process 411. After the third etching process 411 is completed, the second metal nitride layer is patterned by another etching process Layer to form a patterned second metal nitride layer 515.

In some embodiments of the present specification, the material constituting the patterned second metal nitride layer 515 may be the same as or different from the material constituting the patterned first metal nitride layer 405A. In this embodiment, both the second metal nitride layer 515 and the patterned first metal nitride layer 405A include aluminum nitride.

Please refer to FIGS. 6A to 6B. FIGS. 6A to 6B are schematic cross-sectional diagrams of a part of the process structure for fabricating a high electron mobility transistor 600 according to yet another embodiment of this specification. In this embodiment, the structure of the high electron mobility transistor element 600 is roughly similar to the structure of the high electron mobility transistor element 400 depicted in FIG. 4E, except that the high electron mobility transistor element 600 also includes A second barrier layer 616. Since the first-stage process of manufacturing the high electron mobility transistor 600 is the same as the steps described in FIG. 4A to FIG. 4C, it will not be repeated. In an embodiment, the high electron mobility transistor 600 may optionally not have the first metal nitride layer 405A.

After the gate structure 412 is formed, a second barrier layer 616 is formed on a portion of the first barrier layer 403 not covered by the gate structure 412 to cover the patterned first P-type gallium nitride layer 404A And a part of the patterned second P-type gallium nitride layer 406A, and expose another part of the second P-type gallium nitride layer 406A to the outside, and the gate electrode layer 407 is formed on the patterned second The P-type gallium nitride layer 406A is exposed on this outer part. For example, in this embodiment, as shown in FIG. 6A, the second barrier layer 616 may be covered after patterning. Above the extension 404A1 of the first P-type gallium nitride layer 404A, but does not cover the top of the patterned second P-type gallium nitride layer 406A. The lower half of the patterned second P-type gallium nitride layer 406A is embedded in the second barrier layer 616, and the upper half of the patterned second P-type gallium nitride layer 406A And the gate electrode layer 407 is exposed to the outside. Subsequently, a source 413A and a drain 413B are formed on the second barrier layer 616 to be isolated from each other, so that the gate structure 412 is located between the source 413A and the drain 413B (as shown in FIG. 6B).

In other embodiments of this specification, the step of forming the second barrier layer may be earlier than the formation of the gate. For example, please refer to FIG. 7A to FIG. 7C. FIG. 7A to FIG. 7B are schematic cross-sectional diagrams of a part of the process structure for fabricating a high electron mobility transistor 700 according to yet another embodiment of this specification.

First, at least one patterned photoresist layer 701 (instead of using the gate electrode 407 shown in FIGS. 4A to 4D) can be used as an etching mask, and the second P-type gallium nitride layer 406 And the first metal nitride layer 405 are etched to form a patterned second P-type gallium nitride layer 406A and a patterned first metal nitride layer 405A (as shown in FIG. 7A).

After the patterned photoresist layer 701 is removed, another patterned photoresist 710 is used as an etching mask, and the first barrier layer 403 is used as an etching stop layer to etch the first P-type gallium nitride layer 404 to form a pattern Of the first P-type gallium nitride layer 404 (as shown in FIG. 7B).

After the patterned photoresist 710 is removed, a second barrier layer 716 is formed on the patterned first P-type gallium nitride layer 404A and the first barrier layer 403 by epitaxial re-growth (regrowth) technology. The exposed part of the first barrier layer 403, the patterned first P-type gallium nitride layer 404A, the patterned The lower half of the first metal nitride layer 405A and the patterned second P-type gallium nitride layer 406A; and the upper half and the top of the patterned second P-type gallium nitride layer 406A are exposed to the outside . Subsequently, by a deposition and patterning process, a gate 707 is formed on the top of the patterned second P-type gallium nitride layer 406A, and a source 413A and a drain 413B isolated from each other are formed on the second barrier layer 716 , The gate structure 712 (including the gate 707, the patterned first P-type gallium nitride layer 404A, the patterned first metal nitride layer 405A, and the patterned second P-type gallium nitride layer 406A ) Is located between the source 413A and the drain 413B, completing the preparation of the high electron mobility transistor 700 as shown in FIG. 7C.

In the embodiment shown in FIGS. 6A to 7C, the material constituting the second barrier layer 616/716 may be the same as or different from the material constituting the first barrier layer 403. The thickness of the second barrier layer 616/716 may be between 20 nanometers and 100 nanometers. In this embodiment, the material of the second barrier layer 616/716 and the first barrier layer 403 are both made of aluminum gallium nitride. Therefore, the first barrier layer 403 and the second barrier layer 616/716 can be integrated into one aluminum gallium nitride layer, so that the patterned first P-type gallium nitride layer 404A is integrated into the aluminum gallium nitride layer Fully covered.

In the foregoing embodiment, the patterned first P-type gallium nitride layer 404A or the patterned second P-type gallium nitride layer 406A can be formed in the device by the method of the foregoing embodiment. Doped gallium nitride layer, and insert a magnesium nitride layer above or below it, and diffuse magnesium ions in the magnesium nitride layer to the unintentionally doped gallium nitride layer through heat treatment to form P-type gallium nitride Layer, and then perform the step of patterning the first P-type gallium nitride layer 404A and the second P-type gallium nitride layer 406A.

Because the patterned first P-type gallium nitride layer 404A coated in the aluminum gallium nitride layer has an extension that extends beyond the edge of the gate electrode layer 407/707 404A2 can be used as a field plate to provide an additional electric field to the covered area to effectively deplete the electrons accumulated in the covered area, increase the width of the depletion region between the drain and the gate, and cause the redistribution of the electric field , Thereby alleviating the original peak electric field at the edge of the gate, effectively increasing the breakdown voltage of the high electron mobility transistor 600, and reducing the gate leakage current. In addition, the additional aluminum gallium nitride second barrier layer 616/716 also has a current compensation function.

In actual operation, the thickness of the extended portion 404A2 of the first p-type gallium nitride layer 404A after patterning and the doping concentration of p-type impurities, such as Mg, are preferably referred to the high electron mobility transistor 600/700 The carrier concentration in the two-dimensional electron gas channel under the extension 404A2 is determined. In other words, the extension 404A2 is used as a field plate to determine the extent to which the two-dimensional electron gas in the two-dimensional electron gas channel under the covered area is locally depleted. For example, in some embodiments of this specification, when the p-type impurity doping concentration of the first p-type gallium nitride layer 404A in the high electron mobility transistor 600/700 is 1E20/cm ³ , the extension 404A2 When the thickness of is preferably less than or equal to 2 nm, the two-dimensional electron gas under the extension 404A2 is partially depleted. When the p-type impurity doping concentration of the first p-type gallium nitride layer 404A in the electron mobility transistor 600/700 is 5E19/cm ³ , the thickness of the extension 404A2 is preferably less than or equal to 3 nm, The two-dimensional electron gas under the extension 404A2 is partially depleted.

According to the above-mentioned embodiments, this specification is to provide a high electron mobility transistor and a manufacturing method thereof, by forming a first gallium nitride layer and a second gallium nitride layer stacked in sequence on the buffer layer, the channel layer and the barrier layer. The gate structure of the gallium nitride layer, the metal nitride layer and the gate electrode layer. And make the second gallium nitride layer have a plurality of P/N conductivity type impurities. After that, source and drain isolated from each other are formed on the barrier layer. The gate electrode structure is located between the source electrode and the drain electrode to form an enhanced high electron mobility transistor.

In an embodiment of this specification, the first gallium nitride layer is not intentionally doped with impurities. In the process of manufacturing the high electron mobility transistor, the first gallium nitride layer without deliberately doped impurities is used as the buffer layer, so that the doping depth of the doping process for forming the second gallium nitride layer can be accurately grasped. It can prevent the conventional technology from directly growing a P-type electrical gallium nitride layer on the barrier layer and diffusing P-type impurities into the barrier layer and the buffer layer, causing the problem of the overall circuit failure.

In another embodiment of this specification, the first gallium nitride layer and the second gallium nitride layer are composed of gallium nitride with the same conductivity type impurity; and the first stacked layer has an extension, which is formed by the gate The edges of the electrode layer projected on the first gallium nitride layer respectively extend toward the source and drain directions. The electrons accumulated in the two-dimensional electron gas channel on the heterojunction surface of the buffer layer and the barrier layer can be exhausted during the forward operation, and the current collapse phenomenon of the high electron mobility transistor element can be prevented. In the reverse operation, it is easier to form a depletion zone in the channel region, to suppress the leakage current of the gate electrode, and to increase the breakdown voltage of the high electron mobility transistor element. In addition, in the process of fabricating the first gallium nitride layer, the doped gallium nitride layer is patterned by using the metal nitride layer (aluminum nitride layer) underneath it as an etching stop layer to precisely control the etching process To make the patterned first gallium nitride layer have a desired thickness. It can effectively expand the process margin of the high electron mobility transistor device.

In another embodiment of this specification, the first gallium nitride layer and the second gallium nitride layer are composed of gallium nitride with the same conductivity type impurity; and the first stacked layer has an extension, which is formed by the gate The edge of the electrode layer projected on the first gallium nitride layer extends toward the source and drain directions respectively; and an additional barrier layer is formed The second barrier layer of the same quality covers part of the first gallium nitride layer and the second gallium nitride layer, exposing the other part of the second gallium nitride layer, and the gate electrode layer is formed here The second gallium nitride layer is exposed on the outer part. In this way, the extension of the first gallium nitride layer provides an additional electric field to increase the width of the depletion region between the drain and the gate, thereby alleviating the peak electric field at the edge of the gate and effectively improving the high electron mobility electric field. The breakdown voltage of the crystal element, and reduce the gate leakage current.

Although the present invention has been disclosed as above in preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to those defined by the attached patent scope.

100‧‧‧High Electron Mobility Transistor Element

101‧‧‧Substrate

102‧‧‧Passage layer

103‧‧‧Barrier layer

104‧‧‧Gate structure

105‧‧‧Gallium nitride layer without deliberate impurity doping

105A‧‧‧The first aluminum gallium nitride layer

105B‧‧‧Second aluminum gallium nitride layer

106‧‧‧Metal nitride layer

106a‧‧‧Metal atom

106b‧‧‧Open

107‧‧‧Heat treatment process

108‧‧‧Gate electrode layer

109A‧‧‧Source

109B‧‧‧Dip pole

110‧‧‧Buffer layer

111‧‧‧Etching process

Claims (9)

A high electron mobility transistor (High Electron Mobility Transistor) device includes: a substrate; a buffer layer on the substrate and having a III-nitride; a channel layer on the substrate On the buffer layer, there is the group III element nitride; a barrier layer (barrier layer) on the channel layer; a source electrode on the barrier layer; a drain electrode on the barrier layer, and Isolated from the source; and a gate structure located on the barrier layer and between the source and the drain, including: a first gallium nitride (Gallium nitride) layer located on the barrier layer Above, wherein the first gallium nitride layer is not deliberately doped with impurities; a second gallium nitride layer is located on the first gallium nitride layer and has a conductive type impurity, wherein the conductive type impurity includes a first Metal element; a metal nitride layer is located on the second gallium nitride layer, wherein the metal nitride layer includes a metal nitride material MN, where N is nitrogen element, M is a second metal element, the second metal The element is the same as the first metal element of the conductivity type impurity; and a gate electrode layer is located on the second gallium nitride layer. The high electron mobility transistor device described in claim 1, wherein the metal nitride layer includes a magnesium nitride layer, the magnesium nitride layer has an opening, and the gate layer passes through the opening and The second gallium nitride layer is in contact, or the gate layer is located in the opening and is not in contact with the second gallium nitride layer. The high-electron-mobility transistor device described in item 1 of the patent application further includes a third gallium nitride layer located between the metal nitride layer and the gate layer, and the third gallium nitride layer Have this conductivity type impurity. The high electron mobility transistor device described in claim 1, wherein the material of the metal nitride layer includes magnesium nitride, and the first metal element and the second metal element include a magnesium element. A high electron mobility transistor element, comprising: a substrate; a buffer layer on the substrate and having a group III element nitride; and a channel layer on the buffer layer and having the group III element nitride ; A barrier layer located on the channel layer; a source located on the barrier layer; a drain located on the barrier layer and isolated from the source; and a gate structure located on the barrier On the barrier layer and located between the source and the drain, including: a first gallium nitride layer on the barrier layer and having a conductivity type impurity; A first metal nitride layer located on the first gallium nitride layer; a second gallium nitride layer located on the first metal nitride layer and having the conductivity type impurity; a second metal nitride layer, Located between the first gallium nitride layer and the barrier layer, wherein the first metal nitride layer and the second metal nitride layer have the same material; and a gate electrode layer located on the second gallium nitride Wherein, a part of the first gallium nitride layer is projected from the gate electrode layer on an edge of the first gallium nitride layer, respectively extending toward the source and the drain direction. In the high electron mobility transistor device described in claim 5, the material of the first metal nitride layer and the second metal nitride layer includes aluminum nitride. A high-electron mobility transistor element, comprising: a substrate; a buffer layer on the substrate with a group III element nitride; a channel layer on the buffer layer; a first barrier layer, It includes aluminum gallium nitride and is located on the channel layer; a second barrier layer includes aluminum gallium nitride and is located on the first barrier layer; a source electrode is located on the first barrier layer; a drain electrode , Located on the first barrier layer and isolated from the source; A gate structure located on the first barrier layer and between the source electrode and the drain electrode, including: a first gallium nitride layer located on the first barrier layer, having a p-type conductivity A second gallium nitride layer, located on the first barrier layer, having the p-type conductivity, wherein an area of the first gallium nitride layer is larger than an area of the second gallium nitride layer, and The first gallium nitride layer extends toward the source and drain directions; and a gate electrode layer; wherein the second barrier layer covers one of the first gallium nitride layer and the second gallium nitride layer Partly, another part of the second gallium nitride layer is exposed, and the gate electrode layer is formed on the other part. The high electron mobility transistor device described in item 7 of the patent application further includes a metal nitride layer located between the first gallium nitride layer and the second gallium nitride layer. In the high electron mobility transistor device described in item 8 of the scope of patent application, the material of the metal nitride layer includes aluminum nitride.

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