TWI864499B - Testing system - Google Patents

Abstract

A testing system includes a DRAM module under test, a test equipment, and a power supply. The test equipment is coupled to the DRAM module under test, and is configured to generate a first voltage and a test signal to the DRAM module under test. The power supply is coupled to the DRAM module under test and the test equipment, and is configured to generate a second voltage to the DRAM module under test. The DRAM module under test is configured to execute a test procedure to generate a test result to the test equipment according to the test signal. Each of the first voltage and the second voltage includes a working voltage of the DRAM module under test.

Description

Test system

This case involves an electronic system. More specifically, this case involves a testing system.

The existing fourth-generation memory module has been improved and developed into the fifth-generation memory module. However, the fifth-generation memory module has changed the circuit architecture of power management, integrating the voltage regulation circuit of the existing test machine into the fifth-generation memory module. At the same time, the operating voltage required by the fifth-generation memory module cannot be provided by the existing test machine.

Therefore, the above-mentioned technology still has many defects, and it is necessary for practitioners in this field to develop other suitable testing systems.

One aspect of the present invention relates to a test system. The test system includes a memory module to be tested, a test machine, and a power supply. The test machine is coupled to the memory module to be tested, and is used to generate a first voltage and a test signal to the memory module to be tested. The power supply is coupled to the memory module to be tested and the test machine, and is used to generate a second voltage to the memory module to be tested. The memory module to be tested executes a test procedure according to the test signal to generate a test result to the test machine. Each of the first voltage and the second voltage includes an operating voltage of the memory module to be tested.

The following will use diagrams and detailed descriptions to clearly explain the spirit of this case. After understanding the implementation examples of this case, any person with ordinary knowledge in the relevant technical field can make changes and modifications based on the technology taught by this case, which does not deviate from the spirit and scope of this case.

The terms used in this article are only for describing specific embodiments and are not intended to be limiting of this case. Singular forms such as "one", "this", "this", "this" and "the" as used in this article also include plural forms.

The words "include", "including", "have", "contain", etc. used in this article are open terms, meaning including but not limited to.

The terms used in this document generally have the ordinary meanings of each term used in this field, in the context of this case and in the specific context, unless otherwise specified. Certain terms used to describe this case will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing this case.

FIG. 1 is a circuit block diagram of a test system 100 according to some embodiments of the present invention. In some embodiments, referring to FIG. 1 , the test system 100 includes a memory module 110 to be tested, a test machine 120 and a power supply 130.

In some embodiments, the test machine 120 is coupled to the memory module 110 under test and is used to generate a first voltage and a test signal to the memory module 110 under test.

In some embodiments, the power supply 130 is coupled to the memory module 110 under test and the test machine 120, and is used to generate a second voltage to the memory module 110 under test. The memory module 110 under test executes a test procedure according to the test signal to generate a test result to the test machine 120. Each of the first voltage and the second voltage includes an operating voltage of the memory module 110 under test.

In some embodiments, the memory module 110 under test includes a fifth generation double data rate synchronous DRAM dual in-line memory module (DDR5 SDRAM DIMM).

FIG. 2 is a schematic diagram of a test system 100 according to some embodiments of the present invention. In some embodiments, referring to FIG. 2 , a test machine 120 includes a test head 121 and a disassembled test board 122 .

In some embodiments, the disassembly test board 122 is disposed on the test head 121 and is used to place the memory module 110 to be tested. It should be noted that the surface of the disassembly test board 122 includes a plurality of serial peripheral interface interfaces to electrically connect the memory module 110 to be tested and the test head 121 of the test machine 120.

It should be further explained that the number of disassembled test plates 122 is not limited to the illustrated embodiment.

In some embodiments, the test machine 120 is coupled to the memory module 110 under test through a test head 121 and a disassembled test board 122. The test machine 120 is used to generate a first voltage V1 and a test signal to the memory module 110 under test. The test machine 120 is further used to generate a control command SPI to the power supply 130 to adjust the second voltage V2 output by the power supply 130. It should be noted that the wires of the power supply 130 are electrically connected to the memory module 110 under test through connection holes (not shown) of the disassembled test board 122.

In some embodiments, the control command SPI is a programmable command. The test machine 120 can control the voltage conversion efficiency (slew rate), output current and output voltage of the power supply 130 through the control command SPI.

FIG. 3 is an enlarged schematic diagram of a local area Z of a test machine 120 of a test system 100 according to some embodiments of the present invention. In some embodiments, please refer to FIG. 2 and FIG. 3, the embodiment of FIG. 3 is an enlarged schematic diagram of a local area Z corresponding to the embodiment of FIG. 2.

In some embodiments, referring to FIG. 2 and FIG. 3 , the disassembled test board 122 includes a connection hole H. The connection hole H of FIG. 3 is used to couple the power supply 130 of FIG. 2 and the memory module 110 to be tested. The signal line or wire of the power supply 130 is coupled to the printed circuit board PCB of the memory module 110 to be tested through the connection hole H of the disassembled test board 122.

FIG. 4 is a schematic diagram of the internal partial circuit of the memory module 110 to be tested of the test system 100 of FIG. 1 or FIG. 2 according to some embodiments of the present invention. In some embodiments, please refer to FIG. 4, the memory module 110 to be tested includes a voltage regulating circuit 111. It should be noted that the memory module 110 to be tested in FIG. 4 only shows a partial internal circuit structure. The memory module 110 to be tested further includes other multifunctional circuits. The voltage regulating circuit 111 is directly set in the memory module 110 to be tested, thereby improving the stability and integrity of the signal of the memory module 110 to be tested.

It should be noted that the purpose of setting the voltage regulating circuit 111 in the memory module 110 to be tested is to ensure that when the memory chip of the fifth-generation memory module is operating at an operating voltage of 1.1V and an operating frequency of 4800 (MT/s up), the memory chip can receive accurate and stable voltage and signal.

Then, the voltage regulating circuit 111 is coupled to the test machine 120 and the power supply 130 of the test system 100 of FIG. 1 or FIG. 2. The voltage regulating circuit 111 is used to receive the first voltage V1 and the second voltage V2 to execute the test procedure according to the test signal to generate the test result to the test machine 120.

In some embodiments, please refer to FIG. 4, the voltage regulation circuit 111 includes a power management micro memory module PMIC. The power management micro memory module PMIC is used to receive the first voltage V1 and the second voltage V2, so as to convert the first voltage V1 and the second voltage V2 into a plurality of supply voltages (for example: supply voltage VOUT1, supply voltage VOUT2, supply voltage VOUTA, supply voltage VOUTB, supply voltage VOUTC and supply voltage VOUTD) inside the memory module 110 to be tested. In some embodiments, each of the first voltage V1 and the second voltage V2 includes the operating voltage of the power management micro memory module PMIC of the memory module 110 to be tested.

In some embodiments, the supply voltage VOUT1 and the supply voltage VOUT2 are mainly used to provide the supply voltage of the voltage regulator (Low Dropout, LDO). The supply voltage VOUT1 is 1.0V. The supply voltage VOUT2 is 1.8V.

In some embodiments, the supply voltage VOUTA to the supply voltage VOUTD are mainly used to provide the supply voltage of the switch regulator. The supply voltage VOUTA and the supply voltage VOUTB are both 1.1V, which are mainly used as the core power voltage of the memory chip. The supply voltage VOUTC is 1.1V, which is mainly used as the data operation voltage of the memory chip. The supply voltage VOUTD is 1.8V, which is mainly used as the data flow start voltage of the memory chip.

In some embodiments, the first value range of the first voltage V1 generated by the test machine 120 is between 0V and 3.3V. In some embodiments, the first voltage V1 includes 3.3V.

In some embodiments, the second voltage V2 generated by the power supply 130 has a second value range between 0V and 12V. In some embodiments, the second voltage V2 includes 12V.

According to the above-mentioned embodiments, the present case provides a test system, which provides the working voltage (e.g., 12V) required by the memory module by setting a power supply, so as to solve the problem that the existing test equipment cannot supply a voltage higher than 4V.

Although the present invention is disclosed in detail with the embodiments as above, the present invention does not exclude other feasible embodiments. Therefore, the protection scope of the present invention shall be subject to the scope of the attached patent application, and shall not be limited by the aforementioned embodiments.

For those skilled in the art, various modifications and improvements can be made to the present invention without departing from the spirit and scope of the present invention. Based on the above embodiments, all modifications and improvements made to the present invention are also covered by the protection scope of the present invention.

100: Test system 110: Memory module to be tested 120: Test machine 121: Test head 122: Disassemble test board 130: Power supply V1: First voltage V2: Second voltage SPI: Control command Z: Local area H: Connection hole PCB: Printed circuit board 111: Voltage regulation circuit PMIC: Power management micro memory module VOUT1~VOUT2, VOUTA~VOUTD: Supply voltage

The content of this case can be better understood by referring to the implementation methods in the following paragraphs and the following figures: Figure 1 is a schematic diagram of a circuit block of a test system according to some embodiments of this case; Figure 2 is a schematic diagram of an actual system of a test system according to some embodiments of this case; Figure 3 is an enlarged schematic diagram of a local area of a test machine of a test system according to some embodiments of this case; and Figure 4 is a schematic diagram of an internal circuit of a memory module to be tested of a test system according to some embodiments of this case.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

100:Test system

110: Memory module to be tested

120: Testing machine

121: Test head

122: Disassemble the test board

130: Power supply

V1: first voltage

V2: Second voltage

SPI: control commands

Z: Local area

Claims (10)

A test system includes: a memory module to be tested; a test machine coupled to the memory module to be tested and used to generate a first voltage and a test signal to the memory module to be tested; and a power supply coupled to the memory module to be tested and the test machine and used to generate a second voltage to the memory module to be tested, wherein the memory module to be tested executes a test procedure according to the test signal to generate a test result to the test machine, wherein each of the first voltage and the second voltage includes a working voltage of the memory module to be tested. The test system as described in claim 1, wherein the memory module under test comprises a fifth-generation double data rate synchronous dynamic random access memory module (double data rate fifth-generation synchronous DRAM dual in-line memory module, DDR5 SDRAM DIMM). The test system as described in claim 2, wherein the memory module to be tested comprises: A voltage regulating circuit coupled to the test machine and the power supply and used to receive the first voltage and the second voltage to execute the test procedure according to the test signal to generate the test result to the test machine. The test system as described in claim 3, wherein the voltage regulation circuit comprises: A power management micro memory module for receiving the first voltage and the second voltage, so as to convert the first voltage and the second voltage into a plurality of supply voltages inside the memory module to be tested. A test system as described in claim 4, wherein each of the first voltage and the second voltage includes an operating voltage of the power management micro memory module of the memory module to be tested. A test system as described in claim 5, wherein the test machine comprises: a test head; and a disassembly test board, which is disposed on the test head and is used to place the memory module to be tested. The test system as described in claim 6, wherein the disassembly test board comprises: A connection hole for coupling the power supply and the memory module to be tested. The test system as described in claim 1, wherein the test machine is further used to generate a control command to the power supply to adjust the second voltage output by the power supply. The test system as described in claim 1, wherein a first value range of the first voltage generated by the test equipment is between 0V and 3.3V. A test system as described in claim 9, wherein a second value range of the second voltage generated by the power supply is between 0V and 12V.

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