TWI881774B - Memory structure, manufacturing method thereof, operating method thereof, and memory array - Google Patents

Abstract

A memory structure includes insulating layers, gate layers, a first doping layer, second doping layers, third doping layers, a columnar channel, a first dielectric layer, second dielectric layers, and a third dielectric layer. The first doping layer and the columnar channel penetrate through the insulating layers and the gate layers that are alternately stacked. The second doping layers are in direct contact with the first doping layer to form tunnel diodes, in which the second doping layers and the insulating layers are alternately stacked. The third doping layers surround the columnar channel and are connected to the second doping layers. The first dielectric layer is between the first doping layer and the gate layers. The second dielectric layers are between the third doping layers and the gate layers. The third dielectric layer is between the columnar channel and the third doping layers.

Description

Memory structure, manufacturing method thereof, operation method thereof and memory array

This disclosure relates to a memory structure, a method for manufacturing a memory structure, a method for operating a memory structure, and a memory array.

Dynamic random access memory (DRAM) has the advantages of high density, low cost, and low power consumption, so it has been widely used. However, as memory technology gradually approaches physical limits, traditional DRAM (such as DRAM with one transistor and one capacitor (1T1C)) is facing many severe challenges in development. For example, DRAM size is not easy to be miniaturized, DRAM process tends to be complex, and the aspect ratio of capacitors increases significantly with the size reduction. In view of the above, it is necessary to provide a new dynamic random access memory and its manufacturing method to overcome the above problems.

The present disclosure provides a memory structure, which includes a plurality of insulating layers, a plurality of gate layers, a first doped layer, a plurality of second doped layers, a columnar channel, a plurality of third doped layers, a fourth doped layer, a fifth doped layer, a first dielectric layer, a plurality of second dielectric layers, a third dielectric layer, and a plurality of fourth dielectric layers. These insulating layers and these gate layers are alternately stacked. The first doped layer penetrates these insulating layers and these gate layers and has a first conductivity type. The second doped layers are each directly in contact with the first doped layer and have a second conductivity type different from the first conductivity type, wherein the first doped layer and the second doped layers form a plurality of tunnel diodes, and the second doped layers and the insulating layers are alternately stacked. The columnar channels penetrate the insulating layers and the gate layers. The third doped layers each surround the columnar channels, wherein the third doped layers are each connected to the second doped layers, and the third doped layers have the second conductivity type. The fourth doped layer and the fifth doped layer are coupled to the columnar channels. The first dielectric layer is disposed between the first doped layer and the gate layers. The second dielectric layers are disposed between the third doped layers and the gate layers. The third dielectric layer is disposed between the columnar channel and the third doped layers. The plurality of fourth dielectric layers are disposed between the second doped layers and the gate layers.

In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type.

In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type.

In some embodiments, the memory structure further includes a write bit line disposed on the first doped layer.

In some embodiments, the memory structure further includes a read bit line coupled to the fifth doped layer.

In some embodiments, the fourth doped layer is disposed under the columnar channel, the fifth doped layer is disposed on the columnar channel, and the fourth doped layer and the fifth doped layer have the second conductivity type.

In some embodiments, the memory structure further includes a read bit line disposed on the fifth doped layer.

In some embodiments, the columnar channel has a first conductivity type.

In some embodiments, the columnar channels are undoped.

In some embodiments, the doping concentration of these third doping layers is higher than the doping concentration of these second doping layers.

The present disclosure provides a memory array, including a plurality of memory structures of any of the aforementioned embodiments, a plurality of write bit lines, and a plurality of read bit lines. The write bit lines extend along a first direction, wherein the first doped layers of the memory structures arranged along the first direction are coupled to each other via the write bit lines. The read bit lines extend along a second direction, wherein the first direction is perpendicular to the second direction, and the fifth doped layers of the memory structures arranged along the second direction are coupled to each other via the read bit lines.

The present disclosure provides a method for manufacturing a memory structure, which includes the following operations. A first hole is formed to penetrate a plurality of insulating layers and a plurality of first gate layers that are alternately stacked. A first dielectric layer is formed to cover the sidewall of the first hole. A first doped layer is formed in the first hole, wherein the first doped layer has a first conductivity type. A second hole is formed to penetrate the insulating layers and the first gate layers. The first gate layers exposed from the second hole are partially removed to form a plurality of recessed portions. A plurality of second dielectric layers are formed in the recessed portions. A plurality of second doped layers are formed to cover the second dielectric layers, wherein the second doped layers have a second conductivity type different from the first conductivity type. A third dielectric layer is formed in the second hole to cover the insulating layers and the second doped layers. A columnar channel is formed in the second hole. The first dielectric layer, the first gate layers, and the second dielectric layers between the first doped layer and the second doped layers are removed to form a plurality of trenches. A plurality of third doped layers are formed in the trenches to directly contact the first doped layers and connect to the second doped layers, wherein the third doped layers have a second conductivity type.

In some embodiments, the manufacturing method further includes the following operations: after forming these third doped layers in these trenches, forming a plurality of fourth dielectric layers next to these third doped layers; and forming a plurality of second gate layers next to these fourth dielectric layers.

In some embodiments, the manufacturing method further includes the following operations: before forming the second hole through the insulating layers and the first gate layers, forming a fourth doping layer in the substrate, and forming the insulating layers and the first gate layers on the substrate, wherein the second hole exposes the fourth doping layer; and doping the top portion of the columnar channel to form a fifth doping layer.

In some embodiments, the manufacturing method further includes the following operations: forming a write bit line on the first doped layer; and forming a read bit line on the fifth doped layer.

In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type.

In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type.

The present disclosure provides a method for operating a memory structure, which includes the following operations. A memory structure of any of the aforementioned embodiments is received, wherein the gate layers, the third doped layers, the fourth doped layers, the fifth doped layers and the columnar channels form a plurality of read transistors. When the read transistors are P-type transistors and the first conductivity type is N-type, a write operation is performed, and the write operation includes: applying a reverse bias to the first of the tunnel diodes so that one of the third doped layers corresponding to the first has a high potential; or applying a forward bias to the second of the tunnel diodes so that one of the third doped layers corresponding to the second has a low potential. When these read transistors are N-type transistors and the first conductivity type is P-type, a write operation is performed, and the write operation includes: applying a reverse bias to a third of these tunnel diodes so that one of the third doped layers corresponding to the third has a low potential; or applying a forward bias to a fourth of these tunnel diodes so that one of the third doped layers corresponding to the fourth has a high potential.

In some embodiments, these read transistors are P-type transistors, and the operation method further includes the following operations. Apply 0V to the selection gates of these gate layers corresponding to the third doping layer with high potential or low potential. Apply a plurality of negative voltages to a plurality of unselected gates in these gate layers. Apply a positive voltage to the fourth doping layer or the fifth doping layer.

In some embodiments, these read transistors are N-type transistors, and the operation method further includes the following operations. Apply 0V to the selection gates of these gate layers corresponding to the third doping layer with high potential or low potential. Apply a plurality of positive voltages to a plurality of unselected gates in these gate layers. Apply a positive voltage to the fourth doping layer or the fifth doping layer.

100:Memory structure

110: Substrate

120: Gate layer

130: Insulation layer

400:Memory array

500: Manufacturing method

512, 514, 516, 518, 520, 522, 524, 526, 528, 530, 532, 534, 536, 538, 540, 542, 544: Operation

600:Memory structure

700, 800: Circuit

1B-1B’: Section line

A-A’, B-B’: section line

CC: Columnar Channel

CI:Circuit

D1: First doping layer

D2: Second doping layer

D3: The third doping layer

D4: The fourth doping layer

D5: The fifth doping layer

DL1: First dielectric layer

DL2: Second dielectric layer

DL3: The third dielectric layer

DL4: Fourth dielectric layer

G1: First gate layer

G2: Second gate layer

GSL ₁ , GSL ₂ : Global Selection Line

H1: First hole

H2: Second hole

M ₁ , M ₂ , MC ₁₁ , MC ₁₂ , MC ₁₃ , MC ₁₄ , MC ₁₅ , MC ₁₆ , MC ₂₁ , MC ₂₂ , MC 23 , MC ₂₄ , MC ₂₅ , MC ₂₆ : memory unit

P1: Part 1

P2: Part 2

PB: Page Buffer

PG1, PG2: Page

RP: Depression

SN ₁ , SN ₂ : Storage nodes

SSL ₁ , SSL ₂ : String selection line

STI: Isolation Structure

SW: Sidewall

t ₁₁ , t ₁₂ , t ₁₃ , t ₁₄ , t ₁₅ , t ₂₁ , t ₂₂ , t ₂₃ , t ₂₄ , t ₃₁ , t ₃₂ , t ₃₃ , t ₃₄ , t ₃₅ : time

T: Groove

TD, TD ₁ , TD ₂ : Tunnel diode

RT, RT _p , RT _n : read transistor

WG ₁ , WG ₂ , WG ₃ , WG ₄ , WG ₅ , WG ₆ : Write character line

WBL, WBL ₁ , WBL ₂ : Write bit line

RBL, RBL ₁ , RBL ₂ : Read bit line

RSL, RSL ₁ , RSL ₂ : Read source line

V _CC1 , V _CC2 : Supply voltage

X: Second direction

Y: First direction

By reading the detailed description of the following implementation method and referring to the attached drawings, you can more fully understand the content of this disclosure.

Figure 1A is a three-dimensional schematic diagram of a memory structure according to various implementations of the present disclosure.

Figure 1B is a schematic cross-sectional view along the section line 1B-1B’ of Figure 1A.

Figure 2 is a schematic cross-sectional view along the section line A-A’ of Figure 1B.

Figure 3 is a schematic cross-sectional view along the section line B-B’ of Figure 1B.

FIG. 4 is a three-dimensional schematic diagram of a memory array according to various implementations of the present disclosure.

Figures 5A and 5B are flow charts of methods for manufacturing memory structures according to various implementations of the present disclosure.

Figures 6A to 6I are cross-sectional schematic diagrams of intermediate stages of manufacturing memory structures according to various implementations of the present disclosure.

Figures 7 and 8 are schematic diagrams of equivalent circuits of memory structures according to various implementations of the present disclosure.

Figures 9, 11 and 13 are circuit diagrams of memory arrays according to various implementations of the present disclosure.

Figures 10, 12, and 14 are timing diagrams of control signals according to various implementations of the present disclosure.

The following multiple implementations are described and disclosed in detail with the attached figures. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details are not intended to limit the content of this disclosure. In other words, in some implementations of the content of this disclosure, these practical details are not necessary. In addition, to simplify the drawings, some known structures and components will be shown in schematic form in the drawings.

In this article, it is understandable to use the terms first, second, third, etc. to describe various elements, components, regions, layers, and/or blocks. However, these elements, components, regions, layers, and/or blocks should not be limited by these terms. These terms are limited to identifying a single element, component, region, layer, and/or block. Therefore, a first element, component, region, layer, and/or block in the following text may also be referred to as a second element, component, region, layer, and/or block without departing from the original meaning of the present disclosure.

In addition, it should be understood that when element A is referred to as being "connected to" or "coupled to" element B, element A may be directly connected to element B or indirectly connected to element B (for example, an intermediate element C (and/or other elements) may be disposed between element A and element B).

The present disclosure provides a memory structure, which is a three-dimensional (3D) dynamic random access memory (DRAM) structure. The memory structure includes a plurality of memory cells, each memory cell includes a tunnel diode and a read transistor to form a 1D1T DRAM structure. The memory structure of the present disclosure has a high density of memory cells, so it is beneficial to miniaturize the size of the memory structure. In addition, the process of manufacturing the memory structure is simple, so the manufacturing cost can be reduced, thereby replacing the traditional 1T1C DRAM structure. Furthermore, a plurality of memory structures can form a memory array, which has a high density of memory cells, thus facilitating the miniaturization of the memory array.

FIG. 1A is a schematic three-dimensional diagram of a memory structure 100 according to various embodiments of the present disclosure. FIG. 1B is a schematic cross-sectional diagram along section line 1B-1B' of FIG. 1A. FIG. 2 is a schematic cross-sectional diagram along section line A-A' of FIG. 1B. FIG. 3 is a schematic cross-sectional diagram along section line B-B' of FIG. 1B. As shown in FIGS. 1A to 3, the memory structure 100 includes a substrate 110, an isolation structure STI, a plurality of gate layers 120, a plurality of insulating layers 130, a first doping layer D1, a plurality of second doping layers D2, a plurality of third doping layers D3, a fourth doping layer D4, a fifth doping layer D5, a columnar channel CC, a first dielectric layer DL1, a plurality of second dielectric layers DL2, a third dielectric layer DL3, and a plurality of fourth dielectric layers DL4.

In some embodiments, the substrate 110 is a semiconductor substrate. In some embodiments, the substrate 110 includes any suitable semiconductor material and/or semiconductor material used to form a semiconductor structure. The semiconductor material includes, for example, one or more materials, such as crystalline silicon, silicon oxide, strained silicon, germanium silicon, doped or undoped polysilicon, doped or undoped silicon wafer, germanium, gallium arsenide, other suitable semiconductor materials or combinations thereof. In some embodiments, the substrate 110 is a silicon substrate. In some embodiments, the gate layer 120 includes a metal conductive material, a non-metal conductive material or a combination thereof, such as a metal nitride. The material of the gate layer 120 includes, for example, tungsten nitride, tungsten, copper, aluminum, gold, silver, other suitable metals, metal alloys, polysilicon or a combination thereof. In some embodiments, the insulating layer 130 includes oxide, nitride or a combination thereof, such as silicon dioxide, silicon nitride or a combination thereof. In some embodiments, the isolation structure STI is a shallow trench isolation (STI). In some embodiments, the memory structure 100 further includes a complementary metal-oxide-semiconductor (CMOS) element (not shown) disposed in the substrate 110 to be electrically connected to the first doping layer D1 or the fourth doping layer D4.

Please refer to FIG. 1A and FIG. 1B simultaneously. The gate layer 120 and the insulating layer 130 are alternately stacked. The number of the gate layer 120 and the insulating layer 130 can be adjusted arbitrarily and is not limited thereto. The first doped layer D1 penetrates the gate layer 120 and the insulating layer 130 and has a first conductivity type. As shown in FIG. 1B , the first doped layer D1 includes a first portion P1 and a second portion P2 connected to each other, wherein the first portion P1 penetrates the gate layer 120 and the insulating layer 130, and the second portion P2 is located in the substrate 110. The second doped layers D2 are directly in contact with the first doped layers D1 and have a second conductivity type different from the first conductivity type. The first doped layers D1 and the second doped layers D2 form a plurality of tunnel diodes TD, wherein the second doped layers D2 and the insulating layers 130 are alternately stacked, and the tunnel diodes TD serve as access selectors. As shown in FIG. 1B , the tunnel diodes TD are connected to each other in the vertical direction, so the memory structure 100 can have a high density of tunnel diodes TD, which is conducive to size miniaturization. In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type, so the first doped layer D1 is a cathode and the second doped layer D2 is an anode. In other embodiments, the first conductivity type is P-type and the second conductivity type is N-type, so the first doped layer D1 is an anode and the second doped layer D2 is a cathode. The columnar channel CC penetrates the gate layer 120 and the insulating layer 130. As shown in FIG. 1B and FIG. 2, the third doping layer D3 surrounds the columnar channel CC and is connected to the second doping layer D2, wherein the third doping layer D3 has a second conductivity type. In some embodiments, the third doping layer D3 directly contacts the second doping layer D2. As shown in FIG. 2, each gate layer 120 includes a first gate layer G1 and a second gate layer G2. The first gate layer G1 surrounds the first doping layer D1, the third doping layer D3 and the columnar channel CC. The second gate layer G2 is located on both sides of the second doping layer D2.

Please continue to refer to FIG. 1B and FIG. 2, the fourth doped layer D4 and the fifth doped layer D5 are each coupled to the columnar channel CC. In some embodiments, as shown in FIG. 1B, the fourth doped layer D4 is disposed under the columnar channel CC, and the fifth doped layer D5 is disposed on the columnar channel CC, but the configuration is not limited thereto, and the fourth doped layer D4 and the fifth doped layer D5 have the second conductivity type. In some embodiments, the fourth doped layer D4 is a source, and the fifth doped layer D5 is a drain. In other embodiments, the fourth doped layer D4 is a drain, and the fifth doped layer D5 is a source. The gate layer 120, the third doping layer D3, the fourth doping layer D4, the fifth doping layer D5 and the columnar channel CC form a plurality of read transistors RT. The read transistor RT can be a P-type transistor or an N-type transistor. As shown in FIG. 1B , these read transistors RT are connected to each other in the vertical direction, so the memory structure 100 can have a high density of read transistors RT, which is conducive to size miniaturization. As shown in FIG. 2 , the columnar channel CC of the read transistor RT is surrounded by the third doped layer D3 and the gate layer 120, and the third doped layer D3 and the gate layer 120 serve as the gate of the read transistor RT. The third doped layer D3 is annular. A write operation can be performed, and a reverse bias or a forward bias is applied to one of the tunnel diodes TD so that the corresponding third doped layer D3 surrounding the columnar channel CC has a high potential or a low potential. Thereby, data 1 or data 0 is written into the read transistor RT. The third doped layer D3 can store charges and is chargeable or dischargeable. The potential of the third doped layer D3 can be controlled by charging or discharging the third doped layer D3. The third doped layer D3 can also be called a storage node (SN), and the storage node determines the threshold voltage of the read transistor RT. The operation method of the memory structure 100 will be further explained using a circuit diagram later.

As shown in FIG. 1B to FIG. 3 , the first dielectric layer DL1 is disposed between the first doped layer D1 and the gate layer 120 and between the first doped layer D1 and the insulating layer 130, so that the gate layer 120 is electrically isolated from the first doped layer D1. The second dielectric layer DL2 is disposed between the third doped layer D3 and the gate layer 120, so that the gate layer 120 is electrically isolated from the third doped layer D3. The third dielectric layer DL3 is disposed between the columnar channel CC and the third doped layer D3 and between the columnar channel CC and the insulating layer 130, so that the columnar channel CC and the third doped layer D3 are electrically isolated. The third dielectric layer DL3 is annular. The fourth dielectric layer DL4 is respectively disposed between the second doped layer D2 and the gate layer 120, so that the gate layer 120 and the second doped layer D2 are electrically isolated. Please refer to FIG. 1A and FIG. 1B again. In some embodiments, the third dielectric layer DL3 is disposed between the fifth doped layer D5 and one of these insulating layers 130 . In some embodiments, the first dielectric layer DL1, the second dielectric layer DL2, the third dielectric layer DL3, and the fourth dielectric layer DL4 each include a gate oxide. In some embodiments, the first dielectric layer DL1, the second dielectric layer DL2, the third dielectric layer DL3, and the fourth dielectric layer DL4 each include silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, zirconium oxide, titanium oxide, tantalum oxide, other suitable high-k dielectric materials, or combinations thereof.

Please refer to FIG. 1B and FIG. 2 again. The first doping layer D1 has a first conductivity type, and the second doping layer D2, the third doping layer D3, the fourth doping layer D4, and the fifth doping layer D5 have a second conductivity type, wherein the first conductivity type is different from the second conductivity type. In some embodiments, the materials of the first doping layer D1, the second doping layer D2, the third doping layer D3, the fourth doping layer D4, and the fifth doping layer D5 each include silicon, such as crystalline silicon, polycrystalline silicon, or germanium silicon, but not limited thereto. In some embodiments, the first conductivity type is N-type, and the second conductivity type is P-type. The read transistor RT including the fourth doping layer D4 and the fifth doping layer D5 is a P-type transistor, such as a P-type metal-oxide-semiconductor field-effect transistor (PMOSFET). In some embodiments, the doping concentration of the third doping layer D3 is higher than the doping concentration of the second doping layer D2. In some embodiments, the first doping layer D1 is an N+ doping region, the second doping layer D2 is a P- doping region, the third doping layer D3 is a P+ doping region, and the fourth doping layer D4 and the fifth doping layer D5 are P+ doping regions. In some embodiments, the columnar channel CC has a first conductivity type, and the columnar channel CC is, for example, an N-doped region. In other embodiments, the columnar channel CC is undoped.

Please refer to FIG. 1B and FIG. 2 again. The first doping layer D1 has a first conductivity type, and the second doping layer D2, the third doping layer D3, the fourth doping layer D4, and the fifth doping layer D5 have a second conductivity type, wherein the first conductivity type is different from the second conductivity type. In some embodiments, the first conductivity type is a P type, and the second conductivity type is an N type. The read transistor RT including the fourth doping layer D4 and the fifth doping layer D5 is an N type transistor, such as an N type metal-oxide-semiconductor field-effect transistor (NMOSFET). In some embodiments, the doping concentration of the third doping layer D3 is higher than the doping concentration of the second doping layer D2. In some embodiments, the first doping layer D1 is a P+ doping region, the second doping layer D2 is an N- doping region, the third doping layer D3 is an N+ doping region, and the fourth doping layer D4 and the fifth doping layer D5 are N+ doping regions. In some embodiments, the columnar channel CC has a first conductivity type, and the columnar channel CC is, for example, a P- doping region. In other embodiments, the columnar channel CC is undoped.

In some embodiments, the material of the columnar channel CC includes silicon, germanium, polysilicon, semiconductor oxide (eg, indium oxide (In ₂ O ₃ ), indium gallium zinc oxide (IGZO), indium tin oxide (ITO)) or other suitable III-V materials.

Please refer to FIG. 1A again, a plurality of memory structures 100 can form a memory array. The present disclosure provides a memory array, including a plurality of memory structures 100, a plurality of write bit lines, and a plurality of read bit lines. The write bit lines extend along a first direction, wherein the first doping layers D1 of the memory structures 100 arranged along the first direction are mutually coupled through these write bit lines. The read bit lines extend along a second direction, wherein the first direction is perpendicular to the second direction, and the fifth doping layers D5 of the memory structures 100 arranged along the second direction are mutually coupled through these read bit lines. FIG. 4 is a three-dimensional schematic diagram of a memory array 400 according to various embodiments of the present disclosure. The memory array 400 includes 8 memory structures 100 as shown in FIG. 1A , but the present disclosure is not limited thereto. The number of memory structures 100 can be arbitrarily adjusted to, for example, 2, 4, 6, 8, 10, 12, 14, 16, 18, or 20 according to design requirements. The memory array 400 includes a plurality of memory structures 100 in a first direction Y, and includes a plurality of write bit lines WBL extending along the first direction Y. The memory array 400 includes a plurality of memory structures 100 in a second direction X, and includes a plurality of read bit lines RBL extending along the second direction X. The first direction Y is perpendicular to the second direction X. In the memory array 400, a plurality of gate layers 120 and a plurality of insulating layers are alternately stacked. In the second direction X, the gate layers 120 of adjacent memory structures 100 are separated by insulating layers, but for the sake of clarity, the insulating layers are not shown. In addition, for the sake of clarity, the position of the components in the columnar structure is moved upward to clearly illustrate the relative positions of the first doping layer D1, the second doping layer D2, the third doping layer D3, the fifth doping layer D5, the first dielectric layer DL1, the second dielectric layer DL2, the third dielectric layer DL3, and the fourth dielectric layer DL4. The memory structure 100 is coupled to each other through the read bit lines RBL and the write bit lines WBL to form a memory array 400. As shown in FIG. 4 , the first doped layers D1 of the memory structure 100 arranged along the first direction Y are coupled to each other through the write bit lines WBL, and the fifth doped layers D5 of the memory structure 100 arranged along the second direction X are coupled to each other through the read bit lines RBL. In the memory array 400, data can be written into multiple memory structures 100 via the write bit line WBL, and data in multiple memory structures 100 can be read via the read bit line RBL. Therefore, the memory array 400 can greatly improve the writing speed and the reading speed.

The present disclosure provides a method for manufacturing a memory structure, see FIG. 2 and FIG. 5A to FIG. 6I. FIG. 5A and FIG. 5B are flow charts of a method 500 for manufacturing a memory structure according to various embodiments of the present disclosure. The manufacturing method 500 includes operations 512, 514, 516, 518, 520, 522, 524, 526, 528, 530, 532, 534, 536, 538, 540, 542, and 544. FIG. 6A to FIG. 6I are cross-sectional schematic diagrams of intermediate stages of manufacturing a memory structure according to various embodiments of the present disclosure. The above operations 512 to 544 will be described later with reference to Figures 6A to 6I and Figure 2. The manufacturing method disclosed in the present invention has a simple process, thus reducing the manufacturing cost.

Although a series of operations or steps are used below to illustrate the methods disclosed herein, the order in which these operations or steps are shown should not be interpreted as a limitation of the present disclosure. For example, certain operations or steps may be performed in a different order and/or simultaneously with other steps. In addition, not all operations, steps, and/or features shown must be performed to implement the present disclosure. In addition, each operation or step described herein may include a number of sub-steps or actions.

In operation 512, as shown in FIG. 6A, a first portion P1 of the first doped layer D1 and a fourth doped layer D4 are formed in the substrate 110. The first portion P1 of the first doped layer D1 and the fourth doped layer D4 are electrically isolated by an isolation structure STI embedded in the substrate 110. In some embodiments, the first portion P1 of the first doped layer D1 and the fourth doped layer D4 are each formed by doping a portion of the substrate 110. In operation 514, as shown in FIG. 6A, a plurality of insulating layers 130 and a plurality of first gate layers G1 are alternately stacked on the substrate 110. In operation 516, as shown in FIG. 6A, a first hole H1 is formed through the insulating layer 130 and the first gate layer G1 to expose the first portion P1 of the first doped layer D1. In some embodiments, the first hole H1 is formed by an etching process.

In operation 518, as shown in FIG. 6B, a first dielectric layer DL1 is formed to cover the sidewall SW of the first hole H1. In operation 520, as shown in FIG. 6B, a second portion P2 of the first doped layer D1 is formed in the first hole H1, wherein the first doped layer D1 has a first conductivity type. In some embodiments, the second portion P2 of the first doped layer D1 is formed by a deposition process. In some embodiments, the first doped layer D1 has a first conductivity type, and the fourth doped layer D4 has a second conductivity type, and the first conductivity type is different from the second conductivity type. In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type is P-type and the second conductivity type is N-type.

In operation 522, as shown in FIG. 6C, a second hole H2 is formed to penetrate the insulating layer 130 and the first gate layer G1. The second hole H2 exposes the fourth doped layer D4. In some embodiments, the second hole H2 is formed by an etching process. In operation 524, as shown in FIG. 6D, the first gate layer G1 exposed from the second hole H2 is partially removed to form a plurality of recessed portions RP. After operation 524, the sidewall of the second hole H2 has a plurality of recessed portions RP. In some embodiments, the partial removal of the first gate layer G1 is performed by a wet etching process.

In operation 526, as shown in FIG. 6E, a plurality of second dielectric layers DL2 are formed in the recessed portion RP to cover the partially removed first gate layer G1. Specifically, each of the second dielectric layers DL2 is formed in the recessed portion RP and does not fill the recessed portion RP. In operation 528, as shown in FIG. 6F, a plurality of third doped layers D3 are formed to cover the second dielectric layer DL2, wherein the third doped layers D3 have a second conductivity type different from the first conductivity type. Specifically, each of the third doped layers D3 is formed in the recessed portion RP and fills the recessed portion RP. In operation 530, as shown in FIG. 6F, a third dielectric layer DL3 is formed in the second hole H2, covering the insulating layer 130 and the third doping layer D3. The third dielectric layer DL3 does not fill up the second hole H2. In operation 532, as shown in FIG. 6F, a columnar channel CC is formed in the second hole H2. The columnar channel CC fills up the second hole H2.

In operation 534, as shown in FIG. 6G, the first dielectric layer DL1, the first gate layer G1, and the second dielectric layer DL2 between the first doping layer D1 and the third doping layer D3 are removed to form a plurality of trenches T. Specifically, multiple portions of the first dielectric layer DL1, multiple portions of the first gate layer G1, and multiple portions of the second dielectric layer DL2 are removed to form the trenches T. In operation 536, as shown in FIG. 6H, a plurality of second doping layers D2 are formed in the trenches T to directly contact the first doping layer D1 and to connect to the third doping layer D3, wherein the second doping layer D2 has a second conductivity type. The cross section along the section line A-A' is shown in FIG. 2. In some embodiments, the second doping layer D2 is formed by a deposition process. In some embodiments, as shown in FIGS. 6F to 6H, operations 528, 530, 532, 534, and 536 are performed in sequence. After forming the columnar channel CC in the second hole H2, the second doping layer D2 is formed to connect to the first doping layer D1 and the third doping layer D3. In other embodiments, after forming the second doping layer D2 to connect to the first doping layer D1 and the third doping layer D3, the columnar channel CC is formed in the second hole H2. In operation 538, as shown in FIG. 2, a plurality of fourth dielectric layers DL4 are formed next to the second doped layer D2. In operation 540, as shown in FIG. 2, a plurality of second gate layers G2 are formed next to the fourth dielectric layer DL4. In operation 542, as shown in FIG. 6H, the top portion of the columnar channel CC is doped to form a fifth doped layer D5.

In operation 544, as shown in FIG. 6I, a write bit line WBL is formed on the first doped layer D1 and a read bit line RBL is formed on the fifth doped layer D5. The difference between the memory structure 600 of FIG. 6I and the memory structure 100 of FIG. 1B is that the memory structure 600 further includes a write bit line WBL disposed on the first doped layer D1 and a read bit line RBL disposed on the fifth doped layer D5, wherein the write bit line WBL is coupled to the first doped layer D1 and the read bit line RBL is coupled to the fifth doped layer D5.

Please refer to FIG. 6I and FIG. 7 at the same time. FIG. 7 is an equivalent circuit diagram of a memory structure 600 according to various embodiments of the present disclosure. Circuit 700 includes memory cells _MC11 , _MC12 , _MC13 , _MC14 , _MC15 , _MC16 , write bit lines WBL, read bit lines RBL, read source lines RSL, and a plurality of write word lines _WG1 , _WG2 , _WG3 , _WG4 , _WG5 , _WG6 . Circuit 700 may also be referred to as a string circuit. In some embodiments, in the memory structure 600, the first conductivity type is N type, the second conductivity type is P type, the first doped layer D1 is an N+ doped region, the second doped layer D2 is a P- doped region, the first doped layer D1 and the second doped layer D2 form a plurality of tunnel diodes TD ₁ as shown in FIG. 7 , wherein the first doped layer D1 is a cathode, and the second doped layer D2 is an anode. Furthermore, the third doped layer D3 is a P+ doped region, and the fourth doped layer D4 and the fifth doped layer D5 are P+ doped regions. The gate layer 120, the third doping layer D3, the fourth doping layer D4, the fifth doping layer D5 and the columnar channel CC form a plurality of read transistors _RTp , i.e., a plurality of P-type transistors, as shown in FIG7. The plurality of third doping layers D3 in FIG6I respectively correspond to the plurality of storage nodes _SN1 in FIG7. The cathodes of these tunnel diodes _TD1 are commonly connected to the write bit line WBL, and the anodes of these tunnel diodes _TD1 are respectively connected to the storage node _SN1 .

Please continue to refer to FIG. 6I and FIG. 7. The present disclosure provides an operation method of a memory cell MC _11. The memory cell MC ₁₁ includes a tunnel diode TD ₁ and a read transistor RT _p . The tunnel diode TD ₁ is coupled to the write bit line WBL, one of the gate layers 120 is coupled to the write word line WG ₁ , one of the third doped layers D3 serves as a storage node SN ₁ of the read transistor RT _p , and the read transistor RT _p is coupled to the read source line RSL and the read bit line RBL. The storage node SN ₁ forms a capacitor with the adjacent gate layer 120 .

When data 0 is to be written, a reverse bias is applied to the tunnel diode TD ₁ , more specifically, the voltage applied to the write bit line WBL is higher than the voltage applied to the write word line WG ₁ . As a result, electron tunneling occurs in the tunnel diode TD ₁ , so that the storage node SN ₁ has a high potential, and the storage node SN ₁ determines the threshold voltage of the read transistor RT _p . Therefore, during the read operation, no current flows through the read transistor RT _p . When data 1 is to be written, a forward bias is applied to the tunnel diode TD ₁ , more specifically, the voltage applied to the write bit line WBL is lower than the voltage applied to the write word line WG ₁ . As a result, the storage node SN ₁ has a low potential, and the storage node SN ₁ determines the threshold voltage of the read transistor RT _p . Therefore, during the read operation, a current is measured flowing through the read transistor RT _p . In addition, please refer to the memory cell MC ₁₁ to understand the structure and operation of the memory cells MC ₁₂ , MC ₁₃ , MC ₁₄ , MC ₁₅ , and MC ₁₆ , which will not be described in detail. Memory cells MC ₁₁ , MC ₁₂ , MC ₁₃ , MC ₁₄ , MC ₁₅ , and MC ₁₆ can store data 1 or data 0, respectively.

Please continue to refer to FIG. 6I and FIG. 7. The present disclosure provides an operating method of a memory structure 600. A write operation is performed, the write operation comprising: applying a reverse bias to a first one of these tunnel diodes TD ₁ so that one of the third doping layers D3 (or storage node SN ₁ ) corresponding to the first one has a high potential, thereby writing data 0 into the corresponding read transistor RT _p . Alternatively, a write operation is performed, the write operation comprising: applying a forward bias to a second one of these tunnel diodes TD ₁ so that one of the third doping layers D3 (or storage node SN ₁ ) corresponding to the second one has a low potential, thereby writing data 1 into the corresponding read transistor RT _p . In some embodiments, the operating method further comprises the following operations. 0V is applied to the selection gates of the gate layers 120 corresponding to the third doping layer D3 having a high potential or a low potential. A plurality of negative voltages are applied to the plurality of unselected gates in the gate layers 120 to turn on the read transistors _RTp corresponding to the unselected gates. A positive voltage is applied to the fourth doping layer D4 or the fifth doping layer D5 to read the data 0 or the data 1 in the read transistors _RTp corresponding to the selection gates.

Please refer to FIG. 6I and FIG. 8 at the same time. FIG. 8 is an equivalent circuit diagram of a memory structure 600 according to various embodiments of the present disclosure. Circuit 800 includes memory cells MC ₂₁ , MC ₂₂ , MC ₂₃ , MC ₂₄ , MC ₂₅ , MC ₂₆ , a write bit line WBL, a read bit line RBL, a read source line RSL, and a plurality of write word lines WG ₁ , WG ₂ , WG ₃ , WG ₄ , WG ₅ , WG ₆ . Circuit 800 may also be referred to as a serial circuit. In some embodiments, in the memory structure 600, the first conductivity type is P type, the second conductivity type is N type, the first doped layer D1 is a P+ doped region, the second doped layer D2 is an N- doped region, the first doped layer D1 and the second doped layer D2 form a plurality of tunnel diodes TD ₂ as shown in FIG. 8 , wherein the first doped layer D1 is an anode, and the second doped layer D2 is a cathode. Furthermore, the third doped layer D3 is an N+ doped region, and the fourth doped layer D4 and the fifth doped layer D5 are N+ doped regions. The gate layer 120, the third doping layer D3, the fourth doping layer D4, the fifth doping layer D5 and the columnar channel CC form a plurality of read transistors _RTn , i.e., a plurality of N-type transistors, as shown in FIG8. The plurality of third doping layers D3 in FIG6I respectively correspond to the plurality of storage nodes _SN2 in FIG8. The anodes of these tunnel diodes _TD2 are commonly connected to the write bit line WBL, and the cathodes of these tunnel diodes _TD2 are respectively connected to the storage node _SN2 .

Please continue to refer to FIG. 6I and FIG. 8. The present disclosure provides an operation method of a memory cell MC _21. The memory cell MC ₂₁ includes a tunnel diode TD ₂ and a read transistor RT _n . The tunnel diode TD ₂ is coupled to the write bit line WBL, one of the gate layers 120 is coupled to the write word line WG ₁ , one of the third doped layers D3 serves as a storage node SN ₂ of the read transistor RT _n , and the read transistor RT _n is coupled to the read source line RSL and the read bit line RBL. The storage node SN ₂ forms a capacitor with the adjacent gate layer 120.

When data 1 is to be written, a forward bias is applied to the tunnel diode TD ₂ , more specifically, the voltage applied to the write bit line WBL is higher than the voltage applied to the write word line WG ₁ . As a result, the storage node SN ₂ has a high potential, and the storage node SN ₂ determines the threshold voltage of the read transistor RT _n . Therefore, during the read operation, a current is measured flowing through the read transistor RT _n . When data 0 is to be written, a reverse bias is applied to the tunnel diode TD ₂ , more specifically, the voltage applied to the write bit line WBL is lower than the voltage applied to the write word line WG ₁ . Thereby, electron tunneling occurs in the tunnel diode TD ₂ , so that the storage node SN ₂ has a low potential, and the storage node SN ₂ determines the threshold voltage of the read transistor RT _n . Therefore, during the read operation, no current flows through the read transistor RT _n . In addition, please refer to the memory cell MC ₂₁ to understand the structure and operation of the memory cells MC ₂₂ , MC ₂₃ , MC ₂₄ , MC ₂₅ , and MC ₂₆ , which will not be repeated. The memory cells MC ₂₁ , MC ₂₂ , MC ₂₃ , MC ₂₄ , MC ₂₅ , and MC ₂₆ can store data 1 or data 0 respectively.

Please continue to refer to FIG. 6I and FIG. 8. The present disclosure provides an operating method of a memory structure 600. A write operation is performed, the write operation comprising: applying a reverse bias to a first one of these tunnel diodes TD ₂ so that one of the third doping layers D3 (or storage nodes SN ₂ ) corresponding to the first one has a low potential, thereby writing data 0 into the corresponding read transistor RT _n . Alternatively, a write operation is performed, the write operation comprising: applying a forward bias to a second one of these tunnel diodes TD ₂ so that one of the third doping layers D3 (or storage nodes SN ₂ ) corresponding to the second one has a high potential, thereby writing data 1 into the corresponding read transistor RT _n . In some embodiments, the operating method further comprises the following operations. 0V is applied to the selection gates of the gate layers 120 corresponding to the third doping layer D3 having a high potential or a low potential. A plurality of positive voltages are applied to a plurality of unselected gates in the gate layers 120 to turn on the read transistors _RTn corresponding to the unselected gates. A positive voltage is applied to the fourth doping layer D4 or the fifth doping layer D5 to read the data 0 or the data 1 in the read transistors _RTn corresponding to the selection gates.

Please refer to FIG. 1A, FIG. 1B and FIG. 4 again. In some embodiments, the memory array 400 further includes a plurality of read source lines (not shown) extending along the first direction Y, and the fourth doped layers D4 of the memory structures 100 arranged along the first direction Y are coupled to each other through these read source lines. In some embodiments, the read source lines are commonly connected to a page buffer (not shown). In some embodiments, the write bit lines WBL are respectively connected to string select lines (SSL) (not shown) having transistors to control whether the voltage of the write bit lines WBL is applied to the memory structure 100. In some embodiments, in the memory array 400, the first doped layer D1 is respectively connected to a global select line (GSL) (not shown) having a transistor to control the voltage applied to the first doped layer D1.

Next, how to write, read or clear data in the memory array is further described with reference to FIGS. 9 to 14. FIG. 9 is a circuit diagram of a memory array according to various embodiments of the present disclosure. As shown in FIG. 9, the circuit CI includes page PG1, page PG2, write word lines _WG1 , _WG2 , _WG3 , write bit lines _WBL1 , _WBL2 , read source lines _RSL1 , _RSL2 , string select lines _SSL1 , _SSL2 , and global select lines _GSL1 , _GSL2 , and page buffer PB. Page PG1 and page PG2 each include 6 memory cells, and each memory cell includes a tunnel diode and a P-type read transistor. The page buffer PB may be further coupled to a sense amplifier (SA) (not shown). The write word lines WG ₁ , WG ₂ , and WG ₃ are coupled to the P-type read transistors in page PG1 and page PG2, respectively. In page PG1 and page PG2, during the read operation, the read bit lines RBL ₁ and RBL ₂ may be applied with voltage or not applied with voltage, thereby determining which page of data is read. In page PG1 and page PG2, the string select lines SSL ₁ , SSL ₂ and the overall select lines GSL ₁ , GSL ₂ are respectively used to control the switches of transistors, which serve as switches for selecting the serial circuits. Transistors on different strings share the same string select line and the same overall select line. The serial circuits in page PG1 and page PG2 are connected to the source or drain of the transistors of the string select line and the overall select line, respectively. The supply voltages _VCC1 and _VCC2 are used to provide voltage to the cathode of the tunnel diode, respectively. The read source lines _RSL1 and _RSL2 are coupled to the serial circuits of different pages, respectively, and are coupled to the page buffer PB, which can read the data of the entire page at one time. The number of pages, write bit lines, read source lines, string select lines, overall select lines, and memory cells is not limited to the number shown in FIG. 9, and the number can be adjusted arbitrarily according to design requirements.

The following describes how to perform a write operation in the circuit CI of FIG. 9, where page PG1 is the page selected for writing and page PG2 is the page not selected for writing. For example, data 0 can be written into the memory cell _M1 of page PG1 and data ₁ can be written into the memory cell M2 by the operating voltage in Table 1 below. In more detail, the voltage of the string select line SSL ₁ is 3.6V, so the transistor can be turned on, so that the write bit line WBL ₁ applies 3V to the cathode of the tunnel diode in the memory cell, and the write bit line WBL ₂ applies -1V to the cathode of the tunnel diode in the memory cell. The voltage of the write word line WG ₁ is 0V, and the voltage of the write word lines WG ₂ and WG ₃ is -0.5V or 1V. Therefore, the tunnel diode of the memory cell M ₁ is reverse biased so that the storage node has a high potential, thereby writing data 0 to the memory cell M ₁ . The tunnel diode of the memory cell M ₂ is forward biased so that the storage node has a low potential, thereby writing data 1 to the memory cell M ₂ . In page PG1, the bias applied to the tunnel diodes of the memory cells other than the memory cells M ₁ and M ₂ is not enough to make the storage nodes have a high potential or a low potential. Page PG2 is a page that is not selected for writing, so the voltage of string selection line SSL ₂ is 0 V. Please refer to Table 2 below, the supply voltage V _CC2 is 1.5 V, the voltage of write word line WG ₁ is 0 V, and the voltage of write word lines WG ₂ and WG ₃ is -0.5 V or 1 V. Therefore, in page PG2, the reverse bias applied to the tunnel diode of the memory cell is not enough to make the storage node have a high potential.

Please refer to FIG. 9 and FIG. 10 simultaneously. FIG. 10 is a timing diagram of control signals according to various embodiments of the present disclosure. The voltage of the write word line WG ₁ is maintained at 0V. The voltage of the unselected write word lines WG ₂ and WG ₃ is maintained at 1V or -0.5V. The voltage of the unselected string select line SSL ₂ is maintained at 0V. The voltage of the unselected global select line GSL ₂ is maintained at 3.6V. At time t ₁₁ , the voltage of the write bit line WBL ₁ becomes 3V, and the voltage of the write bit line WBL ₂ becomes -1V. At time _t12 , the voltage of the string selection line _SSL1 becomes 3.6V, whereby the voltage of the write bit line _WBL1 , 3V, is applied to the cathode of the tunnel diode of the memory cell _M1 , thereby writing data 0 to the memory cell _M1 , and the voltage of the write bit line _WBL2, -1V, is applied to the cathode of the tunnel diode of the memory cell _M2 , thereby writing data 1 to the memory cell _M2 . At time _t13 , the voltage of the string selection line _SSL1 becomes 0V. At time _t14 , the voltage of the write bit line _WBL1 becomes 0V. At time _t15 , the voltage of the global selection line _GSL1 becomes 3.6V.

FIG. 11 is a circuit diagram of a memory array according to various embodiments of the present disclosure. The following describes how to perform a read operation in the circuit CI of FIG. 11, where page PG1 is the page selected for reading and page PG2 is the page not selected for reading. For example, if the memory cell _M1 of page PG1 stores data 0 and the memory cell _M2 stores data 1, the data of the memory cells _M1 and _M2 can be read by the operating voltages in Table 3 below. In more detail, the supply voltage V _CC1 is 1.5V, 0V is applied to the write word line WG ₁ , the threshold voltage of the P-type read transistors in the memory cells M ₁ and M ₂ is determined by the storage node, and -0.5V is applied to the write word lines WG ₂ and WG ₃ to turn on the corresponding P-type read transistors. For simplicity, some write word lines coupled to the P-type read transistors of different pages are not shown in FIG. 11 . In addition, the voltage of the read bit line RBL ₁ is 0.5V, and the read source lines RSL ₁ and RSL ₂ are respectively coupled to the serial circuits of the pages PG1 and PG2 to read the current. The serial circuit containing the memory cell _M1 cannot be measured with current, which means that the memory cell _M1 stores data 0. The serial circuit containing the memory cell _M2 can be measured with current, which means that the memory cell _M2 stores data 1. Page PG2 is a page that is not selected for reading, so the voltage of the read bit line RBL ₂ is 0V. In addition, a reverse bias is applied to the tunnel diode of the memory cell in page PG2 to prevent current from leaking from the storage node. Please refer to the following Table 4. The supply voltage V _CC2 is 1.5V, the voltage of the write word line WG ₁ is 0V, and the voltage of the write word lines WG ₂ and WG ₃ is -0.5V. It can be seen that the tunnel diodes of the memory cells in page PG2 are all reverse biased.

Please refer to FIG. 11 and FIG. 12 at the same time. FIG. 12 is a timing diagram of control signals according to various embodiments of the present disclosure. The voltage of the unselected write word lines WG ₂ and WG ₃ is maintained at -0.5V. At time t ₂₁ , the voltage of the write word line WG ₁ becomes 0V. At time t ₂₂ , the voltage of the read bit line RBL ₁ becomes 0.5V. At time t ₂₃ , the voltage of the read bit line RBL ₁ becomes 0V. At time t ₂₄ , the voltage of the write word line WG ₁ becomes -0.5V. Thus, during the period from time t ₂₂ to time t ₂₃ , the current can be measured by reading the source line RSL ₂ , indicating that the memory cell M ₂ stores data 1. On the other hand, no current is measured by reading the source line RSL ₁ , indicating that the memory cell M ₁ stores data 0.

FIG. 13 is a circuit diagram of a memory array according to various embodiments of the present disclosure. The following describes how to perform an erase operation in the circuit CI of FIG. 13, wherein page PG1 is a page selected for erase and page PG2 is a page not selected for erase. For example, the data in the memory cell of page PG1 can be erased by the operating voltage of Table 5 below. The voltage of the string select line SSL ₁ is 3.6V, so the transistor can be turned on, and the write bit lines WBL ₁ and WBL ₂ apply 3V to the cathode of the tunnel diode in the memory cell. The voltages of the write word lines WG ₁ , WG ₂ , and WG ₃ are all 0V, so the tunnel diodes of the memory cells are all reverse biased to make the storage nodes have a high potential, thereby writing data 0 to the memory cells of page PG1. On the other hand, please refer to the following Table 6. In page PG2, the voltage of the string select line SSL ₂ is 0V, so the memory cells of page PG2 will not be affected by the voltage of the write bit lines WBL ₁ and WBL ₂ . The supply voltage V _CC2 is 1.5V, and the voltages of the write word lines WG ₁ , WG ₂ , and WG ₃ are all 0V. Therefore, in page PG2 , the reverse bias applied to the tunnel diode of the memory cell is not sufficient to make the storage node have a high potential.

Please refer to FIG. 13 and FIG. 14 at the same time. FIG. 14 is a timing diagram of control signals according to various implementations of the present disclosure. The voltage of the write word lines WG ₁ , WG ₂ , and WG ₃ is maintained at 0V. The voltage of the global selection line GSL ₂ is maintained at 3.6V. At time t ₃₁ , the voltage of the write bit lines WBL ₁ , WBL ₂ becomes 3V. At time t ₃₂ , the voltage of the string selection line SSL ₁ becomes 3.6V, whereby the voltage of 3V of the write bit lines WBL ₁ , WBL ₂ is applied to the cathode of the tunnel diode of the memory cell of page PG1 to apply a reverse bias to the tunnel diode, thereby making the storage node have a high potential. In other words, data 0 is written to the memory cell. At time t ₃₃ , the voltage of the string select line SSL ₁ becomes 0V. At time t ₃₄ , the voltage of the write bit lines WBL ₁ and WBL ₂ becomes 0V. At time t ₃₅ , the voltage of the global select line GSL ₁ becomes 3.6V.

In summary, the present disclosure provides a memory structure, a manufacturing method and an operating method thereof, and a memory array. In the memory structure and the memory array, each memory cell includes a tunnel diode and a read transistor to form a 1D1T DRAM structure. The read transistors are connected to each other in the vertical direction, so that the density of the memory cell can be increased, which is beneficial to the miniaturization of the memory structure and the memory array. In addition, the manufacturing method of the present disclosure has a simple process, so the manufacturing cost can be reduced.

Although the present disclosure has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

It is obvious to a person of ordinary skill in the art that various modifications and variations can be made to the structure of this disclosure without departing from the scope or spirit of this disclosure. In view of the foregoing, this disclosure is intended to cover modifications and variations of this disclosure that fall within the scope of the attached patent applications.

600:Memory structure

110: Substrate

120: Gate layer

130: Insulation layer

CC: Columnar Channel

D1: First doping layer

D2: Second doping layer

D3: The third doping layer

D4: The fourth doping layer

D5: The fifth doping layer

DL1: First dielectric layer

DL2: Second dielectric layer

DL3: The third dielectric layer

G1: First gate layer

P1: Part 1

P2: Part 2

RBL: Read Bit Line

STI: Isolation Structure

WBL: Write Bit Line

Claims (20)

A memory structure includes: A plurality of insulating layers and a plurality of gate layers stacked alternately; A first doped layer, penetrating the insulating layers and the gate layers, and having a first conductivity type; A plurality of second doped layers, each directly contacting the first doped layer, and having a second conductivity type different from the first conductivity type, wherein the first doped layer and the second doped layers form a plurality of tunnel diodes, and the second doped layers and the insulating layers are stacked alternately; A columnar channel, penetrating the insulating layers and the gate layers; A plurality of third doped layers, each surrounding the columnar channel, wherein the third doped layers are each connected to the second doped layers, and the third doped layers have the second conductivity type; A fourth doped layer and a fifth doped layer, coupled to the columnar channel; A first dielectric layer, disposed between the first doped layer and the gate layers; A plurality of second dielectric layers, each disposed between the third doped layers and the gate layers; A third dielectric layer is disposed between the columnar channel and the third doped layers; and a plurality of fourth dielectric layers are each disposed between the second doped layers and the gate layers. The memory structure as described in claim 1, wherein the first conductivity type is N type and the second conductivity type is P type. The memory structure as described in claim 1, wherein the first conductivity type is P type and the second conductivity type is N type. The memory structure as described in claim 1 further includes a write bit line arranged on the first doped layer. The memory structure as described in claim 1 further includes a read bit line coupled to the fifth doped layer. The memory structure as described in claim 1, wherein the fourth doped layer is disposed under the columnar channel, the fifth doped layer is disposed on the columnar channel, and the fourth doped layer and the fifth doped layer have the second conductivity type. The memory structure as described in claim 6 further includes a read bit line disposed on the fifth doped layer. A memory structure as described in claim 6, wherein the columnar channel has the first conductivity type. A memory structure as described in claim 1, wherein the columnar channel is undoped. A memory structure as described in any one of claim 1 to claim 9, wherein the doping concentration of the third doping layers is higher than the doping concentration of the second doping layers. A memory array, comprising: A plurality of memory structures as described in any one of claim 1 to claim 9; A plurality of write bit lines extending along a first direction, wherein the first doped layers of the memory structures arranged along the first direction are coupled to each other via the write bit lines; and A plurality of read bit lines extending along a second direction, wherein the first direction is perpendicular to the second direction, and the fifth doped layers of the memory structures arranged along the second direction are coupled to each other via the read bit lines. A method for manufacturing a memory structure, comprising: forming a first hole penetrating a plurality of alternately stacked insulating layers and a plurality of first gate layers; forming a first dielectric layer covering a side wall of the first hole; forming a first doped layer in the first hole, wherein the first doped layer has a first conductivity type; forming a second hole penetrating the insulating layers and the first gate layers; partially removing the first gate layers exposed from the second hole to form a plurality of recesses; forming a plurality of second dielectric layers in the recesses; Forming a plurality of second doped layers to cover the second dielectric layers, wherein the second doped layers have a second conductivity type different from the first conductivity type; Forming a third dielectric layer in the second hole to cover the insulating layers and the second doped layers; Forming a columnar channel in the second hole; Removing the first dielectric layer, the first gate layers and the second dielectric layers between the first doped layer and the second doped layers to form a plurality of trenches; and A plurality of third doped layers are formed in the trenches to directly contact the first doped layer and connect to the second doped layers, wherein the third doped layers have the second conductivity type. The manufacturing method as described in claim 12 further includes: After forming the third doping layers in the trenches, forming a plurality of fourth dielectric layers next to the third doping layers; and forming a plurality of second gate layers next to the fourth dielectric layers. The manufacturing method as described in claim 12 further includes: Before forming the second hole through the insulating layers and the first gate layers, forming a fourth doping layer in a substrate, and forming the insulating layers and the first gate layers on the substrate, wherein the second hole exposes the fourth doping layer; and Doping a top portion of the columnar channel to form a fifth doping layer. The manufacturing method as described in claim 14 further includes: forming a write bit line on the first doped layer; and forming a read bit line on the fifth doped layer. A manufacturing method as described in claim 12, wherein the first conductivity type is N-type and the second conductivity type is P-type. A manufacturing method as described in claim 12, wherein the first conductivity type is P type and the second conductivity type is N type. A method for operating a memory structure, comprising: Receiving a memory structure as described in any one of claim 1 to claim 9, wherein the gate layers, the third doping layers, the fourth doping layer, the fifth doping layer and the columnar channel form a plurality of read transistors; and Performing a write operation, the write operation comprising: When the read transistors are P-type transistors and the first conductivity type is N-type, A reverse bias is applied to a first one of the tunnel diodes so that one of the third doped layers corresponding to the first one has a high potential; or a forward bias is applied to a second one of the tunnel diodes so that one of the third doped layers corresponding to the second one has a low potential; When the read transistors are N-type transistors and the first conductivity type is P-type, a reverse bias is applied to a third one of the tunnel diodes so that one of the third doped layers corresponding to the third one has a low potential; or a forward bias is applied to a fourth one of the tunnel diodes so that one of the third doped layers corresponding to the fourth one has a high potential. The operating method as described in claim 18, wherein the read transistors are P-type transistors, and the operating method further includes: Applying 0V to a selection gate of the gate layers corresponding to the third doped layer having the high potential or the low potential; Applying a plurality of negative voltages to a plurality of unselected gates in the gate layers; and Applying a positive voltage to the fourth doped layer or the fifth doped layer. The operating method as described in claim 18, wherein the read transistors are N-type transistors, and the operating method further includes: Applying 0V to a selection gate of the gate layers corresponding to the third doped layer having the high potential or the low potential; Applying a plurality of positive voltages to a plurality of unselected gates in the gate layers; and Applying a positive voltage to the fourth doped layer or the fifth doped layer.

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