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US20020148112A1 - Encapsulation method for ball grid array semiconductor package - Google Patents

Encapsulation method for ball grid array semiconductor package Download PDF

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Publication number
US20020148112A1
US20020148112A1 US10/171,976 US17197602A US2002148112A1 US 20020148112 A1 US20020148112 A1 US 20020148112A1 US 17197602 A US17197602 A US 17197602A US 2002148112 A1 US2002148112 A1 US 2002148112A1
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United States
Prior art keywords
adhesive tape
encapsulation method
adhesive
mold
liquid epoxy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/171,976
Inventor
Seong-Jae Heo
Chi-Jung Song
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
LG Semicon Co Ltd
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Filing date
Publication date
Application filed by LG Semicon Co Ltd filed Critical LG Semicon Co Ltd
Priority to US10/171,976 priority Critical patent/US20020148112A1/en
Publication of US20020148112A1 publication Critical patent/US20020148112A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49158—Manufacturing circuit on or in base with molding of insulated base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
    • Y10T29/49171—Assembling electrical component directly to terminal or elongated conductor with encapsulating
    • Y10T29/49172—Assembling electrical component directly to terminal or elongated conductor with encapsulating by molding of insulating material

Definitions

  • the present invention is directed to a ball grid array (BGA) package process used in package processes for a semiconductor device and in particular to an encapsulation method for a BGA semiconductor package which can prevent a flash from occurring during a molding process of the BGA semiconductor package.
  • BGA ball grid array
  • a ball grid array (BGA) semiconductor package has been widely used because it can be used to form several pins in a limited area. Further, the BGA semiconductor package includes short external terminals, thereby preventing bending by an external shock and easily transferring an electric signal.
  • FIG. 1 is a plan view illustrating a printed circuit board before carrying out a conventional encapsulation process for the BGA semiconductor package.
  • FIG. 2 is a cross sectional view illustrating the printed circuit board for explaining the encapsulation process for the BGA semiconductor package.
  • reference numerals 1 to 7 respectively indicate a dispenser 1 for injecting a liquid epoxy, a semiconductor chip 2 , a wire 3 , a dam 4 for preventing a flash from occurring, a printed circuit board 5 , a frame 6 and a liquid epoxy spread 7 within the dam.
  • Three units are configured in a single set in FIGS. 1 and 2.
  • the chip 2 is bonded on the frame 6 with an adhesive by a die attach process.
  • the bonded chip 2 is electrically connected to the board 5 by using the wire 3 .
  • the dam 4 of a certain height is provided to prevent the liquid epoxy discharged from the dispenser 1 from being spread.
  • a height of the dam is set approximately a few tens of ⁇ m.
  • the package process is performed on a plurality of units composing a single set.
  • the afore mentioned encapsulation process must be performed three times. That is, the dispenser 1 is positioned on a first unit, and when the liquid epoxy 7 is completely spread, the dispenser 1 is transferred to a second unit. Accordingly, it takes a longer time to carry out the encapsulation process on the three units than on a single unit by three times.
  • a method of covering an upper portion of the package may be employed where a molding is performed with a mold and the liquid epoxy is injected through the mold.
  • this method also requires a precise process, and thus it is difficult to manage the process.
  • the present invention is directed to a system that substantially obviates one or more of the problems experienced due to the above and other limitations and disadvantages of the related art.
  • BGA ball grid array
  • the present invention includes an encapsulation method for a BGA semiconductor package, including: adhering an one side adhesive tape with a cavity of a certain size at its center portion to an upper portion of a printed circuit board after performing a wire bonding; carrying out a molding by using a mold; and removing the one side adhesive tape when the molding is completed.
  • FIG. 1 is a plan view illustrating a semiconductor package for carrying out an encapsulation process on a conventional ball grid array(BGA) semiconductor package;
  • FIG. 2 is a cross sectional view illustrating the semiconductor package showing the encapsulation process of the conventional BGA semiconductor package
  • FIG. 3 is a cross sectional view illustrating a semiconductor package for explaining an encapsulation method for a BGA semiconductor package according to a preferred embodiment of the present invention
  • FIG. 4A is a plan view illustrating the semiconductor package in FIG. 3;
  • FIG. 4B is a plan view illustrating an one side adhesive tape in FIG. 3;
  • FIG. 5 is a plan view illustrating the semiconductor package after performing the encapsulation process for the BGA semiconductor package according to the preferred embodiment of the present invention.
  • FIG. 6 is a plan view illustrating the semiconductor package from which the one side adhesive tape is removed according to the preferred embodiment of the present invention.
  • FIG. 3 is a cross sectional view illustrating a semiconductor package for explaining an encapsulation method for a ball grid array (BGA) semiconductor package according to a first embodiment of the present invention.
  • BGA ball grid array
  • FIG. 3 the wire bonding is completely carried out on the semiconductor package.
  • a semiconductor chip 2 , a wire 3 , a printed circuit board 5 and a frame 6 are shown in FIG. 3.
  • a one side adhesive tape 11 is adhered to an upper portion of the printed circuit board 5 .
  • the entire package including the one side adhesive tape 11 is surrounded by a mold 8 .
  • a groove 9 of a certain size is formed at an upper portion of the mold 8 .
  • FIG. 4A is a plan view illustrating the semiconductor package in FIG. 3 wherein the wire bonding is completed.
  • FIG. 4B is a plan view illustrating the one side adhesive tape 11 in FIG. 3 which is identical in size to the semiconductor substrate in FIG. 4A and has a cavity 12 of a certain size at its center portion.
  • the size of the cavity 12 may be set identically to an area surrounded by the dam used for the conventional art, and may be slightly larger or smaller than a size of the groove 9 of the mold 8 .
  • the thickness of the one side adhesive tape 12 is approximately 20 ⁇ m, and an adhesive is spread at one side thereof.
  • wire bonding processes are performed in accordance with methods well known to those of ordinary skill, such as the methods described with respect to the background art.
  • the one side adhesive tape 11 is adhered to the upper portion of the printed circuit board 5 . It can be easily adhered to the package because the adhesive is spread at its lower portion.
  • the entire package including the one side adhesive tape 11 is sealed up with the mold 8 .
  • the mold has a through hole (not shown) through which the liquid epoxy is injected.
  • a space 10 of a certain size is formed between the mold 8 and semiconductor package by the groove 9 formed by the mold 8 .
  • FIG. 5 is a plan view illustrating the semiconductor package when the mold 8 is removed. As shown therein, the injected liquid epoxy 13 is spread on the printed circuit board 5 including the cavity 12 of the one side adhesive tape 11 .
  • the area of the spread liquid epoxy 13 is slightly greater than that of the cavity 12 of the one side adhesive tape 11 .
  • the area of the cavity 12 is slightly smaller than the area of the groove 9 of the mold 8 .
  • the cavity 12 may be identical in size to the groove 9 .
  • the spread liquid epoxy 13 is shown to be identical in size to the cavity 12 .
  • FIG. 6 is a cross sectional view illustrating the semiconductor package when the encapsulation process is completed.
  • a mold temperature is approximately 200?C. At this temperature, the adhesive of the one side adhesive tape 11 remarkably loses an adhesive property. As a result, the one side adhesive tape 11 can be easily removed after carrying out the molding.
  • the present invention enables the encapsulation process to be performed on the plurality of units at a time, thereby reducing an entire manufacturing time. Reduction of the manufacturing time results in mass production. Also, the dam employed in the conventional art is not used, which results in simplification of the process and reduction of the package manufacturing cost.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

An encapsulation method for a ball grid array (BGA) semiconductor package, includes: adhering one sided adhesive tape to an upper portion of the semiconductor package after performing a wire bonding; carrying out a molding by using a mold having a groove of a certain size inside; and removing the one side adhesive tape after completing the molding, whereby a flash is prevented from occurring during the BGA encapsulation process.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention is directed to a ball grid array (BGA) package process used in package processes for a semiconductor device and in particular to an encapsulation method for a BGA semiconductor package which can prevent a flash from occurring during a molding process of the BGA semiconductor package. [0002]
  • 2. Description of the Background Art [0003]
  • A ball grid array (BGA) semiconductor package has been widely used because it can be used to form several pins in a limited area. Further, the BGA semiconductor package includes short external terminals, thereby preventing bending by an external shock and easily transferring an electric signal. [0004]
  • FIG. 1 is a plan view illustrating a printed circuit board before carrying out a conventional encapsulation process for the BGA semiconductor package. FIG. 2 is a cross sectional view illustrating the printed circuit board for explaining the encapsulation process for the BGA semiconductor package. As depicted in FIG. 2, [0005] reference numerals 1 to 7 respectively indicate a dispenser 1 for injecting a liquid epoxy, a semiconductor chip 2, a wire 3, a dam 4 for preventing a flash from occurring, a printed circuit board 5, a frame 6 and a liquid epoxy spread 7 within the dam. Three units are configured in a single set in FIGS. 1 and 2.
  • A conventional encapsulation method for the BGA semiconductor package will now be described with reference to FIGS. 1 and 2. [0006]
  • The [0007] chip 2 is bonded on the frame 6 with an adhesive by a die attach process. The bonded chip 2 is electrically connected to the board 5 by using the wire 3.
  • In order to protect the [0008] wire 3, an encapsulation process spreading the liquid epoxy is carried out. Here, the dam 4 of a certain height is provided to prevent the liquid epoxy discharged from the dispenser 1 from being spread. When the liquid epoxy 7 is injected by the dispenser 1, the chip 1 and wire 3 are sealed up by the liquid epoxy 7. Here, a height of the dam is set approximately a few tens of μm.
  • In general, the package process is performed on a plurality of units composing a single set. When it is presumed that three units compose a set, as shown in FIG. 2, the afore mentioned encapsulation process must be performed three times. That is, the [0009] dispenser 1 is positioned on a first unit, and when the liquid epoxy 7 is completely spread, the dispenser 1 is transferred to a second unit. Accordingly, it takes a longer time to carry out the encapsulation process on the three units than on a single unit by three times.
  • By contrast, processes other than the encapsulation process are simultaneously performed on the units composing a single set. Therefore, if the encapsulation process takes a longer time, it results in a time increase of the entire manufacturing process. [0010]
  • In addition, an overflow of the liquid epoxy over the dam will cause a flash. Thus, to prevent the flash from occuring the process must be precisely performed. [0011]
  • There is still another advantage in that the dispenser and encapsulation instruments for using the dispenser are high priced. [0012]
  • In order to prevent the flash from occurring, a method of covering an upper portion of the package may be employed where a molding is performed with a mold and the liquid epoxy is injected through the mold. However, this method also requires a precise process, and thus it is difficult to manage the process. [0013]
    • SUMMARY OF THE INVENTION
  • The present invention is directed to a system that substantially obviates one or more of the problems experienced due to the above and other limitations and disadvantages of the related art. [0014]
  • It is thus an object of the present invention to provide an encapsulation method for a ball grid array (BGA) semiconductor package capable of preventing a flash from occurring during an encapsulation process. [0015]
  • It is another object of the present invention to provide an encapsulation method for a BGA semiconductor package which can simultaneously carry out an encapsulation process on a set consisting of a plurality of units. [0016]
  • It is still another object of the present invention to provide an encapsulation method for a BGA semiconductor package which can prevent a flash from occurring without using a dam. [0017]
  • Other and further objects, features and advantages of the present invention will be set forth in the description that follows, and in part will become apparent from the detailed description, or may be learned by practice of the invention. [0018]
  • To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes an encapsulation method for a BGA semiconductor package, including: adhering an one side adhesive tape with a cavity of a certain size at its center portion to an upper portion of a printed circuit board after performing a wire bonding; carrying out a molding by using a mold; and removing the one side adhesive tape when the molding is completed. [0019]
  • It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. Thus, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of example only. Various changes and modifications that are within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. In fact, other objects, features and characteristics of the present invention; methods, operation, and functions of the related elements of the structure; combinations of parts; and economies of manufacture will surely become apparent from the following detailed description of the preferred embodiments and accompanying drawings, all of which form a part of this specification, wherein like reference numerals designate corresponding parts in various figures.[0020]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention will become better understood with reference to the accompanying drawings which are given only by way of illustration and thus are not limitative of the present invention, wherein: [0021]
  • FIG. 1 is a plan view illustrating a semiconductor package for carrying out an encapsulation process on a conventional ball grid array(BGA) semiconductor package; [0022]
  • FIG. 2 is a cross sectional view illustrating the semiconductor package showing the encapsulation process of the conventional BGA semiconductor package; [0023]
  • FIG. 3 is a cross sectional view illustrating a semiconductor package for explaining an encapsulation method for a BGA semiconductor package according to a preferred embodiment of the present invention; [0024]
  • FIG. 4A is a plan view illustrating the semiconductor package in FIG. 3; [0025]
  • FIG. 4B is a plan view illustrating an one side adhesive tape in FIG. 3; [0026]
  • FIG. 5 is a plan view illustrating the semiconductor package after performing the encapsulation process for the BGA semiconductor package according to the preferred embodiment of the present invention; and [0027]
  • FIG. 6 is a plan view illustrating the semiconductor package from which the one side adhesive tape is removed according to the preferred embodiment of the present invention.[0028]
    • DETAILED DESCRIPTION OF THE INVENTION
  • A molding of a semiconductor package according to a preferred embodiment of the present invention will now be described in detail. [0029]
  • FIG. 3 is a cross sectional view illustrating a semiconductor package for explaining an encapsulation method for a ball grid array (BGA) semiconductor package according to a first embodiment of the present invention. As depicted in FIG. 3, the wire bonding is completely carried out on the semiconductor package. A [0030] semiconductor chip 2, a wire 3, a printed circuit board 5 and a frame 6 are shown in FIG. 3. A one side adhesive tape 11 is adhered to an upper portion of the printed circuit board 5. The entire package including the one side adhesive tape 11 is surrounded by a mold 8.
  • A [0031] groove 9 of a certain size is formed at an upper portion of the mold 8.
  • FIG. 4A is a plan view illustrating the semiconductor package in FIG. 3 wherein the wire bonding is completed. FIG. 4B is a plan view illustrating the one side [0032] adhesive tape 11 in FIG. 3 which is identical in size to the semiconductor substrate in FIG. 4A and has a cavity 12 of a certain size at its center portion. The size of the cavity 12 may be set identically to an area surrounded by the dam used for the conventional art, and may be slightly larger or smaller than a size of the groove 9 of the mold 8. The thickness of the one side adhesive tape 12 is approximately 20 μm, and an adhesive is spread at one side thereof.
  • The wire bonding processes are performed in accordance with methods well known to those of ordinary skill, such as the methods described with respect to the background art. [0033]
  • After the wire bonding is completely performed, the one side [0034] adhesive tape 11 is adhered to the upper portion of the printed circuit board 5. It can be easily adhered to the package because the adhesive is spread at its lower portion.
  • When the one side [0035] adhesive tape 11 is adhered, a portion that corresponds to the cavity at the upper portion of the package is exposed, and the other portions of the package are covered. The exposed portion is to be sealed up by a liquid epoxy. Certain portions of the chip 2, wire 3 and printed circuit board 5 are exposed.
  • Then, the entire package including the one side [0036] adhesive tape 11 is sealed up with the mold 8. The mold has a through hole (not shown) through which the liquid epoxy is injected.
  • A [0037] space 10 of a certain size is formed between the mold 8 and semiconductor package by the groove 9 formed by the mold 8.
  • When injected through the through hole, the liquid epoxy is filled in the [0038] space 10, thereby sealing up the portion of the chip 2, wire 3 and printed circuit board 5. Then, the mold 8 is removed.
  • FIG. 5 is a plan view illustrating the semiconductor package when the [0039] mold 8 is removed. As shown therein, the injected liquid epoxy 13 is spread on the printed circuit board 5 including the cavity 12 of the one side adhesive tape 11.
  • As illustrated in FIG. 5, the area of the [0040] spread liquid epoxy 13 is slightly greater than that of the cavity 12 of the one side adhesive tape 11. In this case, the area of the cavity 12 is slightly smaller than the area of the groove 9 of the mold 8. On the other hand, the cavity 12 may be identical in size to the groove 9. Here, the spread liquid epoxy 13 is shown to be identical in size to the cavity 12.
  • When the one side [0041] adhesive tape 11 is removed from the printed circuit board 5, the liquid epoxy 13 spread at the external portion of cavity 12 of the adhesive tape 11, namely the flash, is completely removed, thus finishing the encapsulation process.
  • FIG. 6 is a cross sectional view illustrating the semiconductor package when the encapsulation process is completed. [0042]
  • On the other hand, when the molding is being performed, a mold temperature is approximately 200?C. At this temperature, the adhesive of the one side [0043] adhesive tape 11 remarkably loses an adhesive property. As a result, the one side adhesive tape 11 can be easily removed after carrying out the molding.
  • As discussed earlier, the present invention enables the encapsulation process to be performed on the plurality of units at a time, thereby reducing an entire manufacturing time. Reduction of the manufacturing time results in mass production. Also, the dam employed in the conventional art is not used, which results in simplification of the process and reduction of the package manufacturing cost. [0044]
  • While there have been illustrated and described what are at present considered to be preferred embodiments of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made, and equivalents may be substituted for elements thereof without departing from the true scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teaching of the present invention without departing from the central scope thereof. Therefor, it is intended that the present invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out the present invention, but that the present invention includes all embodiments falling within the scope of the appended claims. [0045]
  • The foregoing description and the drawings are regarded as including a variety of individually inventive concepts, some of which may lie partially or wholly outside the scope of some or all of the following claims. The fact that the applicant has chosen at the time of filing of the present application to restrict the claimed scope of protection in accordance with the following claims is not to be taken as a disclaimer of alternative inventive concepts that are included in the contents of the application and could be defined by claims differing in scope from the following claims, which different claims may be adopted subsequently during prosecution, for example, for the purposes of a continuation or divisional application. [0046]

Claims (19)

What is claimed is:
1. An encapsulation method for a ball grid array (BGA) semiconductor package, comprising:
adhering adhesive tape to an upper portion of a printed circuit board on which wiring exists, thereby defining a cavity of a predetermined size between adjacent edges of pieces of the adhesive tape;
positioning a mold on the printed circuit board to which the adhesive tape is adhered;
injecting a liquid epoxy through a through hole of the mold to cover the upper portion of the printed circuit board which is exposed through the cavity with the liquid epoxy; and
removing the mold and the adhesive tape.
2. The encapsulation method of claim 1, wherein the adhesive tape has adhesive on only one side.
3. The encapsulation method of claim 1, wherein a width of the cavity defined by the adhesive tape is sufficiently large to be sealed up by the liquid epoxy.
4. The encapsulation method of claim 1, wherein a width of the cavity defined by the adhesive tape is smaller than a width of a groove formed at an upper portion of the mold.
5. The encapsulation method of claim 1, wherein a thickness of the adhesive tape is approximately 20 μm.
6. The encapsulation method of claim 1, wherein an adhesive is spread at a portion of the adhesive tape facing the printed circuit board.
7. The encapsulation method of claim 6, wherein the adhesive loses its adhesive property as the molding is performed.
8. An encapsulation method for a ball grid array semiconductor package, comprising:
adhering adhesive tape to an upper portion of a printed circuit board on which wiring exists, thereby defining a cavity of a predetermined size between adjacent edges of pieces of the adhesive tape;
surrounding the entire package including the adhesive tape with a mold;
injecting a liquid epoxy through a through hole of the mold to cover the upper portion of the printed circuit board which is exposed through the cavity with the liquid epoxy; and
removing the mold and the adhesive tape.
9. The encapsulation method of claim 8, wherein the adhesive tape has adhesive on only one side.
10. The encapsulation method of claim 8, wherein a width of the cavity defined by the one side adhesive tape is sufficiently large to be sealed up by the liquid epoxy.
11. The encapsulation method of claim 8, wherein a width of the cavity defined by the adhesive tape is smaller than that of a groove formed at an upper portion of the mold.
12. The encapsulation method of claim 8, wherein a thickness of the adhesive tape is approximately 20 μm.
13. The encapsulation method of claim 8, wherein an adhesive is spread at a portion of the adhesive tape facing the printed circuit board.
14. The encapsulation method of claim 13, wherein the adhesive loses its adhesive property as the molding is performed.
15. An encapsulation method for a ball grid array semiconductor package, comprising:
placing a mask on surface portions of a printed circuit board of a semiconductor device, areas between adjacent portions of the mask defining areas of the semiconductor device that will be exposed to liquid epoxy;
applying liquid epoxy to areas of the semiconductor device that are exposed by the mask; and
removing the mask to expose surface portions of the semiconductor device not covered by the liquid epoxy.
16. The method of claim 15, wherein the mask is an adhesive tape.
17. The method of claim 16, wherein the adhesive tape has adhesive on only one side, the adhesive side being placed on the surface portions of the semiconductor device.
18. The method of claim 15, wherein applying the liquid epoxy further comprises:
positioning a mold over surface portions of the semiconductor device, the mold having grooves that are positioned over the areas of the semiconductor device defined by the mask and exposed to the liquid epoxy; and
injecting the liquid epoxy through at least one hole in the groove of the mold.
19. The method of claim 16, wherein the adhesive tape loses its adhesive property when predetermined thermal conditions are experienced.
US10/171,976 1999-01-11 2002-06-17 Encapsulation method for ball grid array semiconductor package Abandoned US20020148112A1 (en)

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KR1019990000406A KR20000050486A (en) 1999-01-11 1999-01-11 Encapsulation method of bga transfer molding in semiconductor
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US10/171,976 US20020148112A1 (en) 1999-01-11 2002-06-17 Encapsulation method for ball grid array semiconductor package

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US7307870B2 (en) * 2004-01-28 2007-12-11 Zettacore, Inc. Molecular memory devices and methods
US7324385B2 (en) * 2004-01-28 2008-01-29 Zettacore, Inc. Molecular memory
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US7695756B2 (en) * 2004-04-29 2010-04-13 Zettacore, Inc. Systems, tools and methods for production of molecular memory
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US8907133B2 (en) 2008-07-14 2014-12-09 Esionic Es, Inc. Electrolyte compositions and electrochemical double layer capacitors formed there from
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