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US20030178664A1 - Method of making non volatile memory with a protective metal line - Google Patents

Method of making non volatile memory with a protective metal line Download PDF

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Publication number
US20030178664A1
US20030178664A1 US10/128,716 US12871602A US2003178664A1 US 20030178664 A1 US20030178664 A1 US 20030178664A1 US 12871602 A US12871602 A US 12871602A US 2003178664 A1 US2003178664 A1 US 2003178664A1
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line
substrate
word
volatile memory
layer
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US10/128,716
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US6620694B1 (en
Inventor
Tung-Cheng Kuo
Chien-Hung Liu
Shyi-Shuh Pan
Shou-Wei Huang
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Macronix International Co Ltd
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Macronix International Co Ltd
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Assigned to MACRONIX INTERNATIONAL CO., LTD. reassignment MACRONIX INTERNATIONAL CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HUANG, SHOU-WEI, KUO, TUNG-CHENG, LIU, CHIEN-HUNG, PAN, SHYI-SHUH
Priority to US10/616,083 priority Critical patent/US6794701B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators

Definitions

  • the present invention relates to a structure of a semiconductor device and the fabrication thereof. More particularly, the present invention relates to a structure of a non-volatile memory (NVM) and the fabrication thereof.
  • NVM non-volatile memory
  • a diode is formed in the substrate to electrically connect with the word-line in the prior art.
  • the charges accumulated on the word-line reach a certain amount to produce a voltage higher than the breakdown voltage of the diode, the charges are released in a breakdown manner.
  • the programming effect cannot be completely eliminated by this method since there may still be some charges injected into the charge trapping layer even if the voltage produced by the charges accumulated on the word-line is lower than the breakdown voltage of the diode.
  • the input voltage of the non-volatile memory will be lowered by the diode to adversely decrease the operating speed of the memory device.
  • this invention provides a non-volatile memory and the fabrication thereof to prevent the charge trapping layer of a non-volatile memory from being damaged in a plasma process.
  • This invention also provides a non-volatile memory and the fabrication thereof to prevent the non-volatile memory from being programmed in a plasma process, so that the threshold voltages (V T ) of the memory cells are not raised and the V T distribution is not broadened.
  • This invention also provides a non-volatile memory and the fabrication thereof to avoid the input voltage of the memory device from being lowered, so that the operating speed of the memory device is not decreased.
  • the non-volatile memory of this invention comprises a word-line on a substrate, a charge trapping layer between the word-line and the substrate, and a contact electrically connecting with the word-line over the substrate.
  • a protective metal line electrically connecting with the word-line and with a grounding doped region in the substrate via two contacts, respectively.
  • the protective metal line has a resistance higher than that of the word-line.
  • a non-volatile cell is formed on a substrate and then a grounding doped region is formed in the substrate.
  • Two contacts are then formed over the substrate to electrically connect with the word-line and the grounding doped region, respectively.
  • a protective metal line is formed over the substrate to electrically connect with the grounding doped region and with the word-line via the two contacts, respectively.
  • the protective metal line has a resistance higher than that of the word-line so that the protective metal line can be blown by applying a large current when the manufacturing process is completed.
  • this invention uses a protective metal line with a high resistance to conduct the charges produced in a plasma process into the substrate, the charge trapping layer of the non-volatile memory is not damaged and the memory cells are not programmed at random. Moreover, since the protective metal line has a high resistance, it can be easily blown by applying a large current to disconnect the word-line from the grounding doped region when the manufacturing process is completed. Consequently, the input voltage of the memory device is not lowered and the operating speed of the memory device is not decreased.
  • FIG. 1A ⁇ 1 C illustrate a process flow of fabricating a non-volatile memory according to a preferred embodiment of this invention in a cross-sectional view
  • FIG. 2 illustrate a top view of the non-volatile memory shown in FIG. 1C.
  • a non-volatile memory cell 102 is formed on a substrate 100 , wherein the non-volatile memory cell 102 includes a charge trapping layer 104 and a word-line 106 thereon.
  • the charge trapping layer 104 comprises, for example, a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer, while the non-volatile memory having such a composite layer is called the nitride read-only memory (NROM).
  • the word-line 106 may be a composite conductive layer comprising a polysilicon line 105 a and a metal silicide line 105 b thereon, wherein the metal silicide line 105 b comprises, for example, silicon tungsten (WSi x ).
  • the non-volatile memory cell 102 may be fabricated by forming sequentially a charge trapping layer, a polysilicon layer, and a metal silicide layer on the substrate 100 , patterning the three layers to form the word-line 106 and then forming a source/drain (not shown) in the substrate 100 . Thereafter, a grounding doped region 108 is formed in the substrate 100 by ion implantation.
  • a dielectric layer 110 is formed over the substrate 100 and then two contacts 112 and 114 are formed in the dielectric layer 110 electrically connecting with the word-line 106 and the grounding doped region 108 , respectively.
  • the dielectric layer 110 comprises, for example, borophosphosilicate glass (BPSG).
  • a metal interconnect 116 a and a protective metal line 116 b connecting with the metal interconnect 116 a are formed over the substrate 100 , wherein the protective metal line 116 b has a resistance higher than that of the word-line 106 .
  • the metal interconnect 116 a is electrically connected to the word-line 106 via the contact 112 and the protective metal line 116 b is electrically connected with the grounding doped region 108 via the contact 114 .
  • the protective metal line 116 b is, for example, narrower than the word-line 106 in order to have a high resistance.
  • the protective metal line 116 b can be formed by, for example, forming a metal layer over the substrate 100 and then patterning the metal layer. Since the protective metal line 116 b has a high resistance, it can be easily blown by applying a large current to form a gap 118 disconnecting the word-line 106 from the grounding doped region 108 when the manufacturing process is completed.
  • FIG. 2 illustrate a top view of the non-volatile memory shown in FIG. 1C.
  • the word-line 106 is disposed on the substrate 100 , the grounding doped region 108 is formed in the substrate 100 , and the charge trapping layer 104 is located between the word-line 106 and the substrate 100 .
  • the contact 112 and the contact 114 are located in the dielectric layer 110 electrically connecting with the word-line 106 and the grounding doped region 108 , respectively.
  • the protective metal line 116 b electrically connects the word-line 106 and the grounding doped region 108 via the contacts 112 and 114 .
  • the protective metal line 116 b is narrower than the word-line 106 in order to have a high resistance, however, the protective metal line can be alternatively thinner than the word-line 106 for the same purpose.
  • a large current is applied to blow the protective metal line 116 b to disconnect the word-line 106 from the grounding doped region 108 .
  • this invention uses a protective metal line to connect the substrate and the word-line, the charges produced in a plasma process can be conducted into the substrate. It is noted that the charges are produced in a small amount despite that the plasma environment has a relative high voltage level, so that the current formed from the charges is small and the protective metal line will not be blown. Therefore, the charge trapping layer of the non-volatile memory is not damaged and the memory cells are not programmed at random.
  • the protective metal line has a high resistance, it can be easily blown by applying a large current to disconnect the word-line from the substrate when the manufacturing process is completed. Consequently, the input voltage of the memory device is not lowered and the operating speed of the memory device is not decreased.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

A non-volatile memory and the fabrication thereof are described. The non-volatile memory comprises a word-line on a substrate, a charge trapping layer between the word-line and the substrate, and a contact electrically connecting with the word-line over the substrate. In addition, there is a protective metal line electrically connecting with the word-line and with a grounding doped region in the substrate via different contacts, respectively. The protective metal line has a resistance higher than that of the word-line.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application claims the priority benefit of Taiwan application serial no. 91105280, filed Mar. 20, 2002. [0001]
    • BACKGROUND OF THE INVENTION
  • 1. Field of Invention [0002]
  • The present invention relates to a structure of a semiconductor device and the fabrication thereof. More particularly, the present invention relates to a structure of a non-volatile memory (NVM) and the fabrication thereof. [0003]
  • 2. Description of Related Art [0004]
  • Plasma techniques are frequently used in a manufacturing process of a non-volatile memory having a charge trapping layer for data storage. However, when a transient charge unbalance occurs in the plasma, some charges will move along the metal portions on the wafer. Such an effect is called the antenna effect. Consequently, some charges are injected into the charge trapping layers of the non-volatile memory to unevenly raise the threshold voltages (V[0005] T) of the memory cells, i.e., to produce a programming effect. Therefore, the VT distribution of the non-volatile memory is much broadened, being usually from 0.3V to 0.9V.
  • In order to prevent the programming effect caused by the antenna effect, a diode is formed in the substrate to electrically connect with the word-line in the prior art. When the charges accumulated on the word-line reach a certain amount to produce a voltage higher than the breakdown voltage of the diode, the charges are released in a breakdown manner. However, the programming effect cannot be completely eliminated by this method since there may still be some charges injected into the charge trapping layer even if the voltage produced by the charges accumulated on the word-line is lower than the breakdown voltage of the diode. Moreover, by using this method, the input voltage of the non-volatile memory will be lowered by the diode to adversely decrease the operating speed of the memory device. [0006]
    • SUMMARY OF THE INVENTION
  • Accordingly, this invention provides a non-volatile memory and the fabrication thereof to prevent the charge trapping layer of a non-volatile memory from being damaged in a plasma process. [0007]
  • This invention also provides a non-volatile memory and the fabrication thereof to prevent the non-volatile memory from being programmed in a plasma process, so that the threshold voltages (V[0008] T) of the memory cells are not raised and the VT distribution is not broadened.
  • This invention also provides a non-volatile memory and the fabrication thereof to avoid the input voltage of the memory device from being lowered, so that the operating speed of the memory device is not decreased. [0009]
  • The non-volatile memory of this invention comprises a word-line on a substrate, a charge trapping layer between the word-line and the substrate, and a contact electrically connecting with the word-line over the substrate. In addition, there is a protective metal line electrically connecting with the word-line and with a grounding doped region in the substrate via two contacts, respectively. The protective metal line has a resistance higher than that of the word-line. [0010]
  • In the method of fabricating a non-volatile memory of this invention, a non-volatile cell is formed on a substrate and then a grounding doped region is formed in the substrate. Two contacts are then formed over the substrate to electrically connect with the word-line and the grounding doped region, respectively. A protective metal line is formed over the substrate to electrically connect with the grounding doped region and with the word-line via the two contacts, respectively. The protective metal line has a resistance higher than that of the word-line so that the protective metal line can be blown by applying a large current when the manufacturing process is completed. [0011]
  • Because this invention uses a protective metal line with a high resistance to conduct the charges produced in a plasma process into the substrate, the charge trapping layer of the non-volatile memory is not damaged and the memory cells are not programmed at random. Moreover, since the protective metal line has a high resistance, it can be easily blown by applying a large current to disconnect the word-line from the grounding doped region when the manufacturing process is completed. Consequently, the input voltage of the memory device is not lowered and the operating speed of the memory device is not decreased. [0012]
  • It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.[0013]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings, [0014]
  • FIG. 1A˜[0015] 1C illustrate a process flow of fabricating a non-volatile memory according to a preferred embodiment of this invention in a cross-sectional view; and
  • FIG. 2 illustrate a top view of the non-volatile memory shown in FIG. 1C.[0016]
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Refer to FIG. 1A, a [0017] non-volatile memory cell 102 is formed on a substrate 100, wherein the non-volatile memory cell 102 includes a charge trapping layer 104 and a word-line 106 thereon. The charge trapping layer 104 comprises, for example, a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer, while the non-volatile memory having such a composite layer is called the nitride read-only memory (NROM). The word-line 106 may be a composite conductive layer comprising a polysilicon line 105 a and a metal silicide line 105 b thereon, wherein the metal silicide line 105 b comprises, for example, silicon tungsten (WSix). The non-volatile memory cell 102 may be fabricated by forming sequentially a charge trapping layer, a polysilicon layer, and a metal silicide layer on the substrate 100, patterning the three layers to form the word-line 106 and then forming a source/drain (not shown) in the substrate 100. Thereafter, a grounding doped region 108 is formed in the substrate 100 by ion implantation.
  • Refer to FIG. 1B, a [0018] dielectric layer 110 is formed over the substrate 100 and then two contacts 112 and 114 are formed in the dielectric layer 110 electrically connecting with the word-line 106 and the grounding doped region 108, respectively. The dielectric layer 110 comprises, for example, borophosphosilicate glass (BPSG).
  • Refer to FIG. 1C, a [0019] metal interconnect 116 a and a protective metal line 116 b connecting with the metal interconnect 116 a are formed over the substrate 100, wherein the protective metal line 116 b has a resistance higher than that of the word-line 106. The metal interconnect 116 a is electrically connected to the word-line 106 via the contact 112 and the protective metal line 116 b is electrically connected with the grounding doped region 108 via the contact 114. The protective metal line 116 b is, for example, narrower than the word-line 106 in order to have a high resistance. The protective metal line 116 b can be formed by, for example, forming a metal layer over the substrate 100 and then patterning the metal layer. Since the protective metal line 116 b has a high resistance, it can be easily blown by applying a large current to form a gap 118 disconnecting the word-line 106 from the grounding doped region 108 when the manufacturing process is completed.
  • Refer to FIG. 2 and FIG. 1C to further understand the structure of the non-volatile memory according to the preferred embodiment of this invention, wherein FIG. 2 illustrate a top view of the non-volatile memory shown in FIG. 1C. [0020]
  • As that shown in FIG. 2 and FIG. 1C, the word-[0021] line 106 is disposed on the substrate 100, the grounding doped region 108 is formed in the substrate 100, and the charge trapping layer 104 is located between the word-line 106 and the substrate 100. The contact 112 and the contact 114 are located in the dielectric layer 110 electrically connecting with the word-line 106 and the grounding doped region 108, respectively. In addition, the protective metal line 116 b electrically connects the word-line 106 and the grounding doped region 108 via the contacts 112 and 114. The protective metal line 116 b shown in FIG. 2 is narrower than the word-line 106 in order to have a high resistance, however, the protective metal line can be alternatively thinner than the word-line 106 for the same purpose. When the manufacturing process is completed, a large current is applied to blow the protective metal line 116 b to disconnect the word-line 106 from the grounding doped region 108.
  • Since this invention uses a protective metal line to connect the substrate and the word-line, the charges produced in a plasma process can be conducted into the substrate. It is noted that the charges are produced in a small amount despite that the plasma environment has a relative high voltage level, so that the current formed from the charges is small and the protective metal line will not be blown. Therefore, the charge trapping layer of the non-volatile memory is not damaged and the memory cells are not programmed at random. [0022]
  • Moreover, since the protective metal line has a high resistance, it can be easily blown by applying a large current to disconnect the word-line from the substrate when the manufacturing process is completed. Consequently, the input voltage of the memory device is not lowered and the operating speed of the memory device is not decreased. [0023]
  • It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents. [0024]

Claims (14)

What is claimed is:
1. A non-volatile memory, comprising:
a substrate;
a word-line on the substrate;
a charge trapping layer between the substrate and the word-line;
a contact disposed over the substrate electrically connecting with the word-line; and
a protective metal line electrically connecting with the contact and with a grounding doped region in the substrate, wherein the protective metal line has a first resistance higher than a second resistance of the word-line.
2. The non-volatile memory of claim 1, wherein the protective metal line has a first width smaller than a second width of the word-line.
3. The non-volatile memory of claim 1, wherein the protective metal line has a first thickness smaller than a second thickness of the word-line.
4. The non-volatile memory of claim 1, wherein the protective metal line is electrically connected with the grounding doped region via another contact.
5. The non-volatile memory of claim 1, wherein the charge trapping layer comprises a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer.
6. The non-volatile memory of claim 1, wherein the word-line comprises:
a polysilicon line on the charge trapping layer; and
a metal silicide line on the polysilicon line.
7. The non-volatile memory of claim 6, wherein the metal silicide line comprises tungsten silicide (WSix).
8. A method for fabricating a non-volatile memory, comprising the steps of:
forming a non-volatile memory cell on a substrate;
forming a grounding doped region in the substrate;
forming a first contact on the substrate electrically connecting with the grounding doped region;
forming a second contact on the substrate electrically connecting with a word-line of the non-volatile memory cell;
forming a protective metal line having a first resistance higher than a second resistance of the word-line over the substrate, wherein the protective metal line is electrically connected with the grounding doped region via the first contact and is electrically connected with the word-line via the second contact; and
applying a large current to blow the protective metal line.
9. The method of claim 8, wherein forming the protective metal line comprises:
forming a metal layer over the substrate; and
patterning the metal layer to form the protective metal line.
10. The method of claim 8, wherein forming the non-volatile memory cell comprises:
forming a charge trapping layer on the substrate;
forming a polysilicon layer on the charge trapping layer;
forming a metal silicide layer on the polysilicon layer; and
patterning the metal silicide layer, the polysilicon layer and the charge trapping layer to form the word-line.
11. The method of claim 10, wherein the charge trapping layer comprises a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer.
12. The method of claim 10, wherein the metal silicide layer comprises tungsten silicide (WSix).
13. The method of claim 8, further comprising forming a dielectric layer over the substrate after the grounding doped region is formed in the substrate.
14. The method of claim 13, wherein the dielectric layer comprises borophosphosilicate glass.
US10/128,716 2002-03-20 2002-04-23 Method of making non volatile memory with a protective metal line Expired - Lifetime US6620694B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6869844B1 (en) * 2003-11-05 2005-03-22 Advanced Micro Device, Inc. Method and structure for protecting NROM devices from induced charge damage during device fabrication
US20070096216A1 (en) * 2005-10-18 2007-05-03 Walther Lutz Manufacturing semiconductor circuit, corresponding semiconductor circuit, and associated design process

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Publication number Priority date Publication date Assignee Title
TW527723B (en) * 2002-03-20 2003-04-11 Macronix Int Co Ltd Non-volatile memory and fabrication thereof
JP4364226B2 (en) * 2006-09-21 2009-11-11 株式会社東芝 Semiconductor integrated circuit
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US9490249B2 (en) 2014-04-30 2016-11-08 Macronix International Co., Ltd. Antenna effect discharge circuit and manufacturing method
CN113035882A (en) * 2021-03-10 2021-06-25 山东大学 Universal preparation method of non-volatile semiconductor memory

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US5543344A (en) * 1994-10-05 1996-08-06 United Microelectronics Corp. Method of making programmable read-only memory
US6337502B1 (en) * 1999-06-18 2002-01-08 Saifun Semicinductors Ltd. Method and circuit for minimizing the charging effect during manufacture of semiconductor devices
US6277691B1 (en) * 2000-04-04 2001-08-21 Chartered Semiconductor Manufacturing Ltd. Method to fabricate a robust and reliable memory device
TW507369B (en) * 2001-10-29 2002-10-21 Macronix Int Co Ltd Silicon nitride read only memory structure for preventing antenna effect
US6417053B1 (en) * 2001-11-20 2002-07-09 Macronix International Co., Ltd. Fabrication method for a silicon nitride read-only memory
TW527723B (en) * 2002-03-20 2003-04-11 Macronix Int Co Ltd Non-volatile memory and fabrication thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6869844B1 (en) * 2003-11-05 2005-03-22 Advanced Micro Device, Inc. Method and structure for protecting NROM devices from induced charge damage during device fabrication
US20070096216A1 (en) * 2005-10-18 2007-05-03 Walther Lutz Manufacturing semiconductor circuit, corresponding semiconductor circuit, and associated design process
DE102005049793B3 (en) * 2005-10-18 2007-07-05 Infineon Technologies Ag Method for producing a semiconductor circuit, correspondingly produced semiconductor circuit and associated design method
US7675173B2 (en) 2005-10-18 2010-03-09 Infineon Technologies Ag Manufacturing semiconductor circuit, corresponding semiconductor circuit, and associated design process

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US6620694B1 (en) 2003-09-16
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US20040105321A1 (en) 2004-06-03

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