[go: up one dir, main page]

US20070138641A1 - Semiconductor device and method for fabricating the same - Google Patents

Semiconductor device and method for fabricating the same Download PDF

Info

Publication number
US20070138641A1
US20070138641A1 US11/705,511 US70551107A US2007138641A1 US 20070138641 A1 US20070138641 A1 US 20070138641A1 US 70551107 A US70551107 A US 70551107A US 2007138641 A1 US2007138641 A1 US 2007138641A1
Authority
US
United States
Prior art keywords
layer
inter
pad
opening
insulation layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/705,511
Inventor
Seung-Ho Pyi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Priority to US11/705,511 priority Critical patent/US20070138641A1/en
Publication of US20070138641A1 publication Critical patent/US20070138641A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Definitions

  • the present invention relates to a semiconductor device and a method for fabricating the same; and more particularly, to a semiconductor device with a contact for connecting an interconnection line to a bit line and a method for fabricating the same.
  • a contact formation with use of a metal is an essential technology for fabricating a semiconductor device with a multi-layered structure.
  • This metal contact becomes the basis for a vertical interconnection line between a top conductive layer and a bottom conductive layer.
  • a large scale of integration has led to a high increase in device density that allows several millions of transistors to exist per unit cell area measured in cm 2 .
  • the semiconductor device has been increasingly scaled down, the size of the unit cell becomes smaller and as a result, the size of the contact for connecting an interconnection line that supplies power with a node that receives power becomes smaller as well.
  • An expected value of a response rate with respect to a required signal is also increased as much as the scale of the device integration. Therefore, it is required to have a contact resistance of the down-sized contact that is less than a critical value. For this reason, the importance of a metal contact formation process has been greatly highlighted.
  • DRAM dynamic random access memory
  • the size of a contact for use in a metal interconnection line for providing a power to a bit line has been proportionally smaller.
  • the size of a bit line pad for transmitting a power to the bit line is adversely affected when adjacent bit lines are connected with each other.
  • FIG. 1 is a cross-sectional view showing a conventional contact for use in a metal interconnection line formed on a down-sized bit line pad.
  • a number of bit lines 1 A and 1 B are formed on a substrate SUB.
  • a spacing distance between the bit lines 1 A and 1 B is very small.
  • a bit line pad 2 is formed in a limited area with small size.
  • a reference denotation A because of this down-sized bit line pad 2 , the size of a contact 4 is also limited.
  • an inter-layer insulation layer 3 is thickly formed, and this thickened inter-layer insulation layer 3 makes a depth of the contact 4 increase. For these reasons, there may be a problem that the contact 4 for use in the metal interconnection line is formed on the bit line pad 2 with difficulty.
  • an object of the present invention to provide a semiconductor device with an improved contact margin between a metal interconnection line and a bit line even in demands of scaling-down and high integration and a method for fabricating the same.
  • a semiconductor device including: a bit line structure being formed on a substrate and having a number of bit lines and a pad; a first inter-layer insulation layer being formed on the bit line structure and the substrate and having a first opening exposing the pad; a conductive layer being formed on the first inter-layer insulation layer and being patterned to be a middle pad filled into the first opening and a plate electrode of a capacitor; a second inter-layer insulation layer being formed on the first inter-layer insulation layer and the patterned conductive layer and having a second opening exposing the middle pad; and a metal layer being filled into the second opening to thereby form an interconnection line contacted to the pad.
  • a method for fabricating a semiconductor device including the steps of: forming a bit line structure including bit lines and a pad on a substrate; forming a first inter-layer insulation layer having a first opening exposing the pad on the bit line structure and the substrate; forming a conductive layer on the first inter-layer insulation layer; patterning the conductive layer to thereby obtain a middle pad filled into the first opening and a plate electrode of a capacitor; forming a second inter-layer insulation layer having a second opening exposing the middle pad on the patterned conductive layer and the first inter-layer insulation layer; and filling a metal layer into the second opening to thereby obtain an interconnection line to which the pad is contacted.
  • FIG. 1 is a cross-sectional view showing a conventional bit line pad on which a contact for use in a metal interconnection line is formed;
  • FIG. 2 is a cross-sectional view showing a semiconductor device in accordance with a preferred embodiment of the present invention.
  • FIGS. 3A to 3 F are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with the preferred embodiment of the present invention.
  • FIG. 2 is a cross-sectional view showing a semiconductor device fabricated in accordance with the present invention.
  • bit lines 11 A and 11 B are formed on a substrate 10 on which a pad 12 to which an interconnection line is contacted is formed.
  • a first inter-layer insulation layer 13 is formed on the substrate 10 .
  • the first inter-layer insulation layer 13 has a first opening 14 A exposing the pad 12 .
  • a conductive layer for forming a middle pad 16 filled in to the first opening 14 A of the first inter-layer insulation layer 13 is patterned on the first inter-layer insulation layer 13 .
  • the conductive layer is based on a metal, and thus, the middle pad 16 and the plate electrode 20 exhibit conductivities.
  • the middle pad 16 is filled into the first opening 14 A and simultaneously extends towards an upper part of the first inter-layer insulation layer 13 .
  • the middle pad 16 is formed in a peripheral region of a dynamic random access memory (DRAM) device, while the plate electrode 20 is formed in a cell region of the DRAM device.
  • DRAM dynamic random access memory
  • the second inter-layer insulation layer 17 has a second opening 14 B exposing the middle pad 16 .
  • the size of the second opening 14 B is larger than that of the first opening 14 A.
  • a metal layer 18 for use in an interconnection line is filled into the second opening 14 B of the second inter-layer insulation layer 17 .
  • FIGS. 3A to 3 F are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with the preferred embodiment of the present invention.
  • the same reference numerals are used for the same configuration elements described in FIG. 2 .
  • bit lines 11 A and 11 B are formed on a substrate 10 on which a pad 12 is formed, and a first inter-layer insulation layer 13 is formed thereon.
  • the pad 12 is a bit line pad.
  • the first inter-layer insulation layer 13 is selectively etched to thereby form a first opening 14 A exposing the pad 12 .
  • a thin conductive layer is formed on the first inter-layer insulation layer 13 and is then patterned to form a middle pad 16 filling the first opening 14 A of the first inter-layer insulation layer 13 as simultaneously as to form a plate electrode 20 of a capacitor.
  • the conductive layer is made of a metal.
  • a second inter-layer insulation layer 17 is formed on the first inter-layer insulation layer 13 , the middle pad 16 and the plate electrode 20 .
  • the middle pad 16 is formed in a peripheral region of a dynamic random access memory (DRAM) device, while the plate electrode 20 is formed in a cell region of the DRAM device.
  • DRAM dynamic random access memory
  • the second inter-layer insulation layer 17 is selectively etched to form a second opening 14 B which connects the middle pad 16 with a metal interconnection line which will be formed subsequently.
  • the second opening 14 B is formed as large as the design rule of a semiconductor device allows.
  • a metal layer is formed on the second inter-layer insulation layer 17 by filling the second opening 14 B and then, patterned to form a metal interconnection line 18 .
  • the middle pad based on the same material employed for forming the plate electrode of the capacitor is formed on the pad, and then, the metal interconnection line is contacted to the middle pad.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

The present invention relates to a semiconductor device with an improved contact margin between an interconnection line and a bit line and a method for fabricating the same. The semiconductor device includes: a bit line structure formed on a substrate and having a number of bit lines and a pad; a first inter-layer insulation layer formed on the bit line structure and the substrate and having a first opening exposing the pad; a conductive layer formed on the first inter-layer insulation layer and patterned to be a middle pad filled into the first opening and a plate electrode of a capacitor; a second inter-layer insulation layer formed on the first inter-layer insulation layer and the patterned conductive layer and having a second opening exposing the middle pad; and a metal layer filled into the second opening to form an interconnection line contacted to the pad.

Description

    FIELD OF THE INVENTION
  • The present invention relates to a semiconductor device and a method for fabricating the same; and more particularly, to a semiconductor device with a contact for connecting an interconnection line to a bit line and a method for fabricating the same.
    • DESCRIPTION OF RELATED ARTS
  • A contact formation with use of a metal is an essential technology for fabricating a semiconductor device with a multi-layered structure. This metal contact becomes the basis for a vertical interconnection line between a top conductive layer and a bottom conductive layer. Meanwhile, a large scale of integration has led to a high increase in device density that allows several millions of transistors to exist per unit cell area measured in cm2. As the semiconductor device has been increasingly scaled down, the size of the unit cell becomes smaller and as a result, the size of the contact for connecting an interconnection line that supplies power with a node that receives power becomes smaller as well. An expected value of a response rate with respect to a required signal is also increased as much as the scale of the device integration. Therefore, it is required to have a contact resistance of the down-sized contact that is less than a critical value. For this reason, the importance of a metal contact formation process has been greatly highlighted.
  • As the size of a dynamic random access memory (DRAM) device has been smaller, the size of a contact for use in a metal interconnection line for providing a power to a bit line has been proportionally smaller. In addition to the down-scaled contact for use in the metal interconnection line, the size of a bit line pad for transmitting a power to the bit line is adversely affected when adjacent bit lines are connected with each other. Hence, it is difficult to increase the size of the bit line pad, thereby resulting in another difficulty in increasing the size of a contact node with respect to the metal interconnection line.
  • FIG. 1 is a cross-sectional view showing a conventional contact for use in a metal interconnection line formed on a down-sized bit line pad. A number of bit lines 1A and 1B are formed on a substrate SUB. At this time, a spacing distance between the bit lines 1A and 1B is very small. As a result of this fine spacing distance between the bit lines 1A and 1B, a bit line pad 2 is formed in a limited area with small size. As shown a reference denotation A, because of this down-sized bit line pad 2, the size of a contact 4 is also limited. Also, as the scale of device integration increases, it is necessary to increase the height of a capacitor in order to obtain an intended level of capacitance per cell that is equal to or greater than the capacitance of a previous semiconductor device. Therefore, an inter-layer insulation layer 3 is thickly formed, and this thickened inter-layer insulation layer 3 makes a depth of the contact 4 increase. For these reasons, there may be a problem that the contact 4 for use in the metal interconnection line is formed on the bit line pad 2 with difficulty.
    • SUMMARY OF THE INVENTION
  • It is, therefore, an object of the present invention to provide a semiconductor device with an improved contact margin between a metal interconnection line and a bit line even in demands of scaling-down and high integration and a method for fabricating the same.
  • In accordance with an aspect of the present invention, there is provided a semiconductor device, including: a bit line structure being formed on a substrate and having a number of bit lines and a pad; a first inter-layer insulation layer being formed on the bit line structure and the substrate and having a first opening exposing the pad; a conductive layer being formed on the first inter-layer insulation layer and being patterned to be a middle pad filled into the first opening and a plate electrode of a capacitor; a second inter-layer insulation layer being formed on the first inter-layer insulation layer and the patterned conductive layer and having a second opening exposing the middle pad; and a metal layer being filled into the second opening to thereby form an interconnection line contacted to the pad.
  • In accordance with another aspect of the present invention, there is provided a method for fabricating a semiconductor device, including the steps of: forming a bit line structure including bit lines and a pad on a substrate; forming a first inter-layer insulation layer having a first opening exposing the pad on the bit line structure and the substrate; forming a conductive layer on the first inter-layer insulation layer; patterning the conductive layer to thereby obtain a middle pad filled into the first opening and a plate electrode of a capacitor; forming a second inter-layer insulation layer having a second opening exposing the middle pad on the patterned conductive layer and the first inter-layer insulation layer; and filling a metal layer into the second opening to thereby obtain an interconnection line to which the pad is contacted.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other objects and features of the present invention will become better understood with respect to the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:
  • FIG. 1 is a cross-sectional view showing a conventional bit line pad on which a contact for use in a metal interconnection line is formed;
  • FIG. 2 is a cross-sectional view showing a semiconductor device in accordance with a preferred embodiment of the present invention; and
  • FIGS. 3A to 3F are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with the preferred embodiment of the present invention.
    • DETAILED DESCRIPTION OF THE INVENTION
  • Hereinafter, a semiconductor device and a method for fabricating the same in accordance with a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.
  • FIG. 2 is a cross-sectional view showing a semiconductor device fabricated in accordance with the present invention.
  • As shown, a number of bit lines 11A and 11B are formed on a substrate 10 on which a pad 12 to which an interconnection line is contacted is formed. A first inter-layer insulation layer 13 is formed on the substrate 10. At this time, the first inter-layer insulation layer 13 has a first opening 14A exposing the pad 12.
  • A conductive layer for forming a middle pad 16 filled in to the first opening 14A of the first inter-layer insulation layer 13 is patterned on the first inter-layer insulation layer 13. Herein, the conductive layer is based on a metal, and thus, the middle pad 16 and the plate electrode 20 exhibit conductivities. Also, the middle pad 16 is filled into the first opening 14A and simultaneously extends towards an upper part of the first inter-layer insulation layer 13. The middle pad 16 is formed in a peripheral region of a dynamic random access memory (DRAM) device, while the plate electrode 20 is formed in a cell region of the DRAM device.
  • Next, there is formed a second inter-layer insulation layer 17 on the above resulting substrate structure. At this time, the second inter-layer insulation layer 17 has a second opening 14B exposing the middle pad 16. The size of the second opening 14B is larger than that of the first opening 14A.
  • A metal layer 18 for use in an interconnection line is filled into the second opening 14B of the second inter-layer insulation layer 17.
  • FIGS. 3A to 3F are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with the preferred embodiment of the present invention. Herein, the same reference numerals are used for the same configuration elements described in FIG. 2.
  • Referring to FIG. 3A, a number of bit lines 11A and 11B are formed on a substrate 10 on which a pad 12 is formed, and a first inter-layer insulation layer 13 is formed thereon. Herein, the pad 12 is a bit line pad.
  • Referring to FIG. 3B, the first inter-layer insulation layer 13 is selectively etched to thereby form a first opening 14A exposing the pad 12.
  • Referring to FIG. 3C, a thin conductive layer is formed on the first inter-layer insulation layer 13 and is then patterned to form a middle pad 16 filling the first opening 14A of the first inter-layer insulation layer 13 as simultaneously as to form a plate electrode 20 of a capacitor. Herein, the conductive layer is made of a metal.
  • Referring to FIG. 3D, a second inter-layer insulation layer 17 is formed on the first inter-layer insulation layer 13, the middle pad 16 and the plate electrode 20. Herein, the middle pad 16 is formed in a peripheral region of a dynamic random access memory (DRAM) device, while the plate electrode 20 is formed in a cell region of the DRAM device.
  • With reference to FIG. 3E, the second inter-layer insulation layer 17 is selectively etched to form a second opening 14B which connects the middle pad 16 with a metal interconnection line which will be formed subsequently. At this time, the second opening 14B is formed as large as the design rule of a semiconductor device allows.
  • Afterwards, as shown in FIG. 3F, a metal layer is formed on the second inter-layer insulation layer 17 by filling the second opening 14B and then, patterned to form a metal interconnection line 18.
  • In accordance with the preferred embodiment of the present invention, the middle pad based on the same material employed for forming the plate electrode of the capacitor is formed on the pad, and then, the metal interconnection line is contacted to the middle pad. As a result of this specific structure, it is possible to form a wide contact between the metal interconnection line and the selected bit line, thereby further resulting in a decrease in a contact resistance and an improvement on stability of a metal interconnection line formation process.
  • The present application contains subject matter related to the Korean patent application No. KR 2004-0054712, filed in the Korean Patent Office on Jul. 14, 2004, the entire contents of which being incorporated herein by reference.
  • While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims (6)

1. A semiconductor device, comprising:
a bit line structure being formed on a substrate and having a number of bit lines and a pad;
a first inter-layer insulation layer being formed on the bit line structure and having a first opening exposing the pad;
a conductive layer being formed on the first inter-layer insulation layer and being patterned to be a middle pad filled into the first opening;
a second inter-layer insulation layer being formed on the first inter-layer insulation layer and the patterned conductive layer and having a second opening exposing the middle pad; and
a metal layer being filled into the second opening to thereby form an interconnection line contacted to the pad.
2. The semiconductor device of claim 1, wherein the conductive layer is made of a metal.
3. The semiconductor device of claim 1, wherein the middle pad is formed by being filled into the first opening of the first inter-layer as simultaneously as by extending an upper part of the first inter-layer insulation layer.
4. The semiconductor device of claim 3, wherein the second opening of the second inter-layer insulation layer is larger than the first opening of the first inter-layer insulation layer.
5. The semiconductor device of claim 1, wherein the middle pad is formed in a peripheral region of a dynamic random access memory (DRAM) device.
6-9. (canceled)
US11/705,511 2004-07-14 2007-02-13 Semiconductor device and method for fabricating the same Abandoned US20070138641A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/705,511 US20070138641A1 (en) 2004-07-14 2007-02-13 Semiconductor device and method for fabricating the same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR1020040054712A KR100599431B1 (en) 2004-07-14 2004-07-14 Semiconductor device and method for fabricating the same
KR10-2004-0054712 2004-07-14
US11/023,348 US7189597B2 (en) 2004-07-14 2004-12-29 Semiconductor device and method for fabricating the same
US11/705,511 US20070138641A1 (en) 2004-07-14 2007-02-13 Semiconductor device and method for fabricating the same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11/023,348 Division US7189597B2 (en) 2004-07-14 2004-12-29 Semiconductor device and method for fabricating the same

Publications (1)

Publication Number Publication Date
US20070138641A1 true US20070138641A1 (en) 2007-06-21

Family

ID=35600012

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/023,348 Expired - Fee Related US7189597B2 (en) 2004-07-14 2004-12-29 Semiconductor device and method for fabricating the same
US11/705,511 Abandoned US20070138641A1 (en) 2004-07-14 2007-02-13 Semiconductor device and method for fabricating the same

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US11/023,348 Expired - Fee Related US7189597B2 (en) 2004-07-14 2004-12-29 Semiconductor device and method for fabricating the same

Country Status (2)

Country Link
US (2) US7189597B2 (en)
KR (1) KR100599431B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090194878A1 (en) * 2008-01-31 2009-08-06 Hynix Semiconductor Inc. Semiconductor device and method for manufacturing the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010050311A (en) * 2008-08-22 2010-03-04 Elpida Memory Inc Semiconductor device, and method of manufacturing the same

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5929469A (en) * 1996-12-25 1999-07-27 Kabushiki Kaisha Toshiba Contact holes of a different pitch in an application specific integrated circuit
US6329281B1 (en) * 1999-12-03 2001-12-11 Agere Systems Guardian Corp. Methods for fabricating a multilevel interconnection for an integrated circuit device utilizing a selective overlayer
US6424041B1 (en) * 2000-08-18 2002-07-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6573135B2 (en) * 2001-11-03 2003-06-03 Hynix Semiconductor Inc. Simultaneous formation of bottom electrodes and their respective openings of capacitors in both a memory cell region and logic region
US6844600B2 (en) * 1998-09-03 2005-01-18 Micron Technology, Inc. ESD/EOS protection structure for integrated circuit devices
US20050085070A1 (en) * 2003-10-20 2005-04-21 Hynix Semiconductor Inc. Method for forming metal interconnection line in semiconductor device
US6962771B1 (en) * 2000-10-13 2005-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Dual damascene process

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970054004A (en) 1995-12-14 1997-07-31 김주용 Bit line formation method of semiconductor device
KR19980066718A (en) 1997-01-28 1998-10-15 김광호 Method for forming contact pad of semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5929469A (en) * 1996-12-25 1999-07-27 Kabushiki Kaisha Toshiba Contact holes of a different pitch in an application specific integrated circuit
US6844600B2 (en) * 1998-09-03 2005-01-18 Micron Technology, Inc. ESD/EOS protection structure for integrated circuit devices
US6329281B1 (en) * 1999-12-03 2001-12-11 Agere Systems Guardian Corp. Methods for fabricating a multilevel interconnection for an integrated circuit device utilizing a selective overlayer
US6424041B1 (en) * 2000-08-18 2002-07-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6962771B1 (en) * 2000-10-13 2005-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Dual damascene process
US6573135B2 (en) * 2001-11-03 2003-06-03 Hynix Semiconductor Inc. Simultaneous formation of bottom electrodes and their respective openings of capacitors in both a memory cell region and logic region
US20050085070A1 (en) * 2003-10-20 2005-04-21 Hynix Semiconductor Inc. Method for forming metal interconnection line in semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090194878A1 (en) * 2008-01-31 2009-08-06 Hynix Semiconductor Inc. Semiconductor device and method for manufacturing the same

Also Published As

Publication number Publication date
KR20060005761A (en) 2006-01-18
US20060014372A1 (en) 2006-01-19
KR100599431B1 (en) 2006-07-14
US7189597B2 (en) 2007-03-13

Similar Documents

Publication Publication Date Title
EP2215658B1 (en) Semiconductor constructions and methods of forming capacitors
US5414655A (en) Semiconductor memory device having a stack-type capacitor
JP3577197B2 (en) Method for manufacturing semiconductor device
US8247304B2 (en) Method of manufacturing semiconductor device having capacitor under bit line structure
TW548840B (en) Semiconductor memory device
JPH07142597A (en) Semiconductor memory device and manufacturing method thereof
CN111108619A (en) Capacitor, integrated assembly including capacitor, and method of forming integrated assembly
CN113314669B (en) Double-sided capacitor structure and method of forming the same
US6680539B2 (en) Semiconductor device, semiconductor device pattern designing method, and semiconductor device pattern designing apparatus
US20070138641A1 (en) Semiconductor device and method for fabricating the same
TW508799B (en) Methods of forming wiring layers on integrated circuits including regions of high and low topography, and integrated circuits formed thereby
US20120025347A1 (en) Method of forming a MIM capacitor
US6501113B2 (en) Semiconductor device with capacitor using high dielectric constant film or ferroelectric film
US8470667B2 (en) Semiconductor device including reservoir capacitor and method of manufacturing the same
EP4195253A1 (en) Semiconductor structure forming method and semiconductor structure
US6229172B1 (en) Semiconductor device and manufacturing method thereof
US8766368B2 (en) Semiconductor devices having double-layered metal contacts and methods of fabricating the same
US5888865A (en) Method for manufacturing dram capacitor
US8685852B2 (en) Method of forming metal line of semiconductor device
US6297121B1 (en) Fabrication method for capacitors in integrated circuits with a self-aligned contact structure
KR100591174B1 (en) Metal-insulator-metal capacitors for semiconductor devices and methods of manufacturing the same
US20090108317A1 (en) Semiconductor device and method of fabricating the same
JP2005093714A (en) Semiconductor device and manufacturing method thereof
KR20050030986A (en) Method for forming capacitor for use in semiconductor device
JP2004103622A (en) Semiconductor device

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION