US20190068444A1

US20190068444A1 - Technologies for providing efficient transfer of results from accelerator devices in a disaggregated architecture

Info

Publication number: US20190068444A1
Application number: US15/859,363
Authority: US
Inventors: Joe Grecco; Sujoy Sen; Francesc Guim Bernat; Susanne M. Balle; Evan Custodio; Paul Dormitzer; Henry Mitchel
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2017-08-30
Filing date: 2017-12-30
Publication date: 2019-02-28
Also published as: EP3676708A4; CN109428889B; US20190065260A1; US20190069433A1; US11416309B2; US20190067848A1; US11030017B2; US20200257566A1; CN109428841A; US20190065261A1; WO2019045929A1; CN109426630A; US20190068693A1; CN109426646A; CN109426646B; US20190068698A1; DE112018004798T5; EP3676708A1; US11422867B2; US20190068521A1

Abstract

Technologies for providing efficient transfer of results from remote accelerator devices include a compute sled. The compute sled is to send a request to utilize an accelerator device on an accelerator sled. The request includes a data object to be processed by the accelerator device to increase the speed of execution of a workload associated with the data object. The compute sled is also to receive a modification map from the accelerator sled indicative of a modification to the data object. Further, the compute sled is to determine the modification to the data object based on the modification map and apply the modification to the data object in a memory device of the compute sled.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims the benefit of Indian Provisional Patent Application No. 201741030632, filed Aug. 30, 2017 and U.S. Provisional Patent Application No. 62/584,401, filed Nov. 10, 2017.

BACKGROUND

In some data centers, a compute device may send a data object (e.g., a data set to be operated on) to an accelerator device (e.g., device or circuitry capable of performing a function on a data set faster than a general purpose processor could), such as a field-programmable gate array (FPGA), through a network. After operating on the data object, the accelerator device may send a processed version of the data object back to the compute device through the network. While offloading the processing of certain data sets associated with a workload (e.g., an application) from a general purpose compute device to an accelerator device may generally provide a speed increase, the delays resulting from sending relatively large data objects through the network may diminish the speed increase that would otherwise be obtained from utilizing the accelerator device.

BRIEF DESCRIPTION OF THE DRAWINGS

The concepts described herein are illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.

FIG. 1 is a simplified diagram of at least one embodiment of a data center for executing workloads with disaggregated resources;

FIG. 2 is a simplified diagram of at least one embodiment of a pod of the data center of FIG. 1;

FIG. 3 is a perspective view of at least one embodiment of a rack that may be included in the pod of FIG. 2;

FIG. 4 is a side plan elevation view of the rack of FIG. 3;

FIG. 5 is a perspective view of the rack of FIG. 3 having a sled mounted therein;

FIG. 6 is a is a simplified block diagram of at least one embodiment of a top side of the sled of FIG. 5;

FIG. 7 is a simplified block diagram of at least one embodiment of a bottom side of the sled of FIG. 6;

FIG. 8 is a simplified block diagram of at least one embodiment of a compute sled usable in the data center of FIG. 1;

FIG. 9 is a top perspective view of at least one embodiment of the compute sled of FIG. 8;

FIG. 10 is a simplified block diagram of at least one embodiment of an accelerator sled usable in the data center of FIG. 1;

FIG. 11 is a top perspective view of at least one embodiment of the accelerator sled of FIG. 10;

FIG. 12 is a simplified block diagram of at least one embodiment of a storage sled usable in the data center of FIG. 1;

FIG. 13 is a top perspective view of at least one embodiment of the storage sled of FIG. 12;

FIG. 14 is a simplified block diagram of at least one embodiment of a memory sled usable in the data center of FIG. 1; and

FIG. 15 is a simplified block diagram of a system that may be established within the data center of FIG. 1 to execute workloads with managed nodes composed of disaggregated resources;

FIG. 16 is a simplified block diagram of at least one embodiment of a system for providing efficient transfer of results from accelerator devices;

FIG. 17 is a simplified block diagram of at least one embodiment of a compute sled of the system of FIG. 16;

FIG. 18 is a simplified block diagram of at least one embodiment of an accelerator sled of the system of FIG. 16;

FIG. 19 is a simplified block diagram of at least one embodiment of an environment that may be established by the compute sled of FIGS. 16 and 17;

FIG. 20 is a simplified block diagram of at least one embodiment of an environment that may be established by the accelerator sled of FIGS. 16 and 18;

FIGS. 21-23 are a simplified flow diagram of at least one embodiment of a method for providing efficient transfer of results from accelerator devices that may be performed by the compute sled of FIGS. 16 and 17; and

FIGS. 24-25 are a simplified flow diagram of at least one embodiment of a method for providing efficient transfer of results from remote accelerator devices that may be performed by the accelerator sled of FIGS. 16 and 18.

DETAILED DESCRIPTION OF THE DRAWINGS

While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described herein in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the present disclosure and the appended claims.
References in the specification to “one embodiment,” “an embodiment,” “an illustrative embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Additionally, it should be appreciated that items included in a list in the form of “at least one A, B, and C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of “at least one of A, B, or C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).
The disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device).
In the drawings, some structural or method features may be shown in specific arrangements and/or orderings. However, it should be appreciated that such specific arrangements and/or orderings may not be required. Rather, in some embodiments, such features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of a structural or method feature in a particular figure is not meant to imply that such feature is required in all embodiments and, in some embodiments, may not be included or may be combined with other features.
Referring now to FIG. 1, a data center 100 in which disaggregated resources may cooperatively execute one or more workloads (e.g., applications on behalf of customers) includes multiple pods 110, 120, 130, 140, each of which includes one or more rows of racks. As described in more detail herein, each rack houses multiple sleds, which each may be embodied as a compute device, such as a server, that is primarily equipped with a particular type of resource (e.g., memory devices, data storage devices, accelerator devices, general purpose processors). In the illustrative embodiment, the sleds in each pod 110, 120, 130, 140 are connected to multiple pod switches (e.g., switches that route data communications to and from sleds within the pod). The pod switches, in turn, connect with spine switches 150 that switch communications among pods (e.g., the pods 110, 120, 130, 140) in the data center 100. In some embodiments, the sleds may be connected with a fabric using Intel Omni-Path technology. As described in more detail herein, resources within sleds in the data center 100 may be allocated to a group (referred to herein as a “managed node”) containing resources from one or more other sleds to be collectively utilized in the execution of a workload. The workload can execute as if the resources belonging to the managed node were located on the same sled. The resources in a managed node may even belong to sleds belonging to different racks, and even to different pods 110, 120, 130, 140. Some resources of a single sled may be allocated to one managed node while other resources of the same sled are allocated to a different managed node (e.g., one processor assigned to one managed node and another processor of the same sled assigned to a different managed node). By disaggregating resources to sleds comprised predominantly of a single type of resource (e.g., compute sleds comprising primarily compute resources, memory sleds containing primarily memory resources), and selectively allocating and deallocating the disaggregated resources to form a managed node assigned to execute a workload, the data center 100 provides more efficient resource usage over typical data centers comprised of hyperconverged servers containing compute, memory, storage and perhaps additional resources). As such, the data center 100 may provide greater performance (e.g., throughput, operations per second, latency, etc.) than a typical data center that has the same number of resources.
Referring now to FIG. 2, the pod 110, in the illustrative embodiment, includes a set of rows 200, 210, 220, 230 of racks 240. Each rack 240 may house multiple sleds (e.g., sixteen sleds) and provide power and data connections to the housed sleds, as described in more detail herein. In the illustrative embodiment, the racks in each row 200, 210, 220, 230 are connected to multiple pod switches 250, 260. The pod switch 250 includes a set of ports 252 to which the sleds of the racks of the pod 110 are connected and another set of ports 254 that connect the pod 110 to the spine switches 150 to provide connectivity to other pods in the data center 100. Similarly, the pod switch 260 includes a set of ports 262 to which the sleds of the racks of the pod 110 are connected and a set of ports 264 that connect the pod 110 to the spine switches 150. As such, the use of the pair of switches 250, 260 provides an amount of redundancy to the pod 110. For example, if either of the switches 250, 260 fails, the sleds in the pod 110 may still maintain data communication with the remainder of the data center 100 (e.g., sleds of other pods) through the other switch 250, 260. Furthermore, in the illustrative embodiment, the switches 150, 250, 260 may be embodied as dual-mode optical switches, capable of routing both Ethernet protocol communications carrying Internet Protocol (IP) packets and communications according to a second, high-performance link-layer protocol (e.g., Intel's Omni-Path Architecture's, Infiniband) via optical signaling media of an optical fabric.
It should be appreciated that each of the other pods 120, 130, 140 (as well as any additional pods of the data center 100) may be similarly structured as, and have components similar to, the pod 110 shown in and described in regard to FIG. 2 (e.g., each pod may have rows of racks housing multiple sleds as described above). Additionally, while two pod switches 250, 260 are shown, it should be understood that in other embodiments, each pod 110, 120, 130, 140 may be connected to different number of pod switches (e.g., providing even more failover capacity).
Referring now to FIGS. 3-5, each illustrative rack 240 of the data center 100 includes two elongated support posts 302, 304, which are arranged vertically. For example, the elongated support posts 302, 304 may extend upwardly from a floor of the data center 100 when deployed. The rack 240 also includes one or more horizontal pairs 310 of elongated support arms 312 (identified in FIG. 3 via a dashed ellipse) configured to support a sled of the data center 100 as discussed below. One elongated support arm 312 of the pair of elongated support arms 312 extends outwardly from the elongated support post 302 and the other elongated support arm 312 extends outwardly from the elongated support post 304.
In the illustrative embodiments, each sled of the data center 100 is embodied as a chassis-less sled. That is, each sled has a chassis-less circuit board substrate on which physical resources (e.g., processors, memory, accelerators, storage, etc.) are mounted as discussed in more detail below. As such, the rack 240 is configured to receive the chassis-less sleds. For example, each pair 310 of elongated support arms 312 defines a sled slot 320 of the rack 240, which is configured to receive a corresponding chassis-less sled. To do so, each illustrative elongated support arm 312 includes a circuit board guide 330 configured to receive the chassis-less circuit board substrate of the sled. Each circuit board guide 330 is secured to, or otherwise mounted to, a top side 332 of the corresponding elongated support arm 312. For example, in the illustrative embodiment, each circuit board guide 330 is mounted at a distal end of the corresponding elongated support arm 312 relative to the corresponding elongated support post 302, 304. For clarity of the Figures, not every circuit board guide 330 may be referenced in each Figure.
Each circuit board guide 330 includes an inner wall that defines a circuit board slot 380 configured to receive the chassis-less circuit board substrate of a sled 400 when the sled 400 is received in the corresponding sled slot 320 of the rack 240. To do so, as shown in FIG. 4, a user (or robot) aligns the chassis-less circuit board substrate of an illustrative chassis-less sled 400 to a sled slot 320. The user, or robot, may then slide the chassis-less circuit board substrate forward into the sled slot 320 such that each side edge 414 of the chassis-less circuit board substrate is received in a corresponding circuit board slot 380 of the circuit board guides 330 of the pair 310 of elongated support arms 312 that define the corresponding sled slot 320 as shown in FIG. 4. By having robotically accessible and robotically manipulable sleds comprising disaggregated resources, each type of resource can be upgraded independently of each other and at their own optimized refresh rate. Furthermore, the sleds are configured to blindly mate with power and data communication cables in each rack 240, enhancing their ability to be quickly removed, upgraded, reinstalled, and/or replaced. As such, in some embodiments, the data center 100 may operate (e.g., execute workloads, undergo maintenance and/or upgrades, etc.) without human involvement on the data center floor. In other embodiments, a human may facilitate one or more maintenance or upgrade operations in the data center 100.
It should be appreciated that each circuit board guide 330 is dual sided. That is, each circuit board guide 330 includes an inner wall that defines a circuit board slot 380 on each side of the circuit board guide 330. In this way, each circuit board guide 330 can support a chassis-less circuit board substrate on either side. As such, a single additional elongated support post may be added to the rack 240 to turn the rack 240 into a two-rack solution that can hold twice as many sled slots 320 as shown in FIG. 3. The illustrative rack 240 includes seven pairs 310 of elongated support arms 312 that define a corresponding seven sled slots 320, each configured to receive and support a corresponding sled 400 as discussed above. Of course, in other embodiments, the rack 240 may include additional or fewer pairs 310 of elongated support arms 312 (i.e., additional or fewer sled slots 320). It should be appreciated that because the sled 400 is chassis-less, the sled 400 may have an overall height that is different than typical servers. As such, in some embodiments, the height of each sled slot 320 may be shorter than the height of a typical server (e.g., shorter than a single rank unit, “1U”). That is, the vertical distance between each pair 310 of elongated support arms 312 may be less than a standard rack unit “1U.” Additionally, due to the relative decrease in height of the sled slots 320, the overall height of the rack 240 in some embodiments may be shorter than the height of traditional rack enclosures. For example, in some embodiments, each of the elongated support posts 302, 304 may have a length of six feet or less. Again, in other embodiments, the rack 240 may have different dimensions. Further, it should be appreciated that the rack 240 does not include any walls, enclosures, or the like. Rather, the rack 240 is an enclosure-less rack that is opened to the local environment. Of course, in some cases, an end plate may be attached to one of the elongated support posts 302, 304 in those situations in which the rack 240 forms an end-of-row rack in the data center 100.
In some embodiments, various interconnects may be routed upwardly or downwardly through the elongated support posts 302, 304. To facilitate such routing, each elongated support post 302, 304 includes an inner wall that defines an inner chamber in which the interconnect may be located. The interconnects routed through the elongated support posts 302, 304 may be embodied as any type of interconnects including, but not limited to, data or communication interconnects to provide communication connections to each sled slot 320, power interconnects to provide power to each sled slot 320, and/or other types of interconnects.
The rack 240, in the illustrative embodiment, includes a support platform on which a corresponding optical data connector (not shown) is mounted. Each optical data connector is associated with a corresponding sled slot 320 and is configured to mate with an optical data connector of a corresponding sled 400 when the sled 400 is received in the corresponding sled slot 320. In some embodiments, optical connections between components (e.g., sleds, racks, and switches) in the data center 100 are made with a blind mate optical connection. For example, a door on each cable may prevent dust from contaminating the fiber inside the cable. In the process of connecting to a blind mate optical connector mechanism, the door is pushed open when the end of the cable enters the connector mechanism. Subsequently, the optical fiber inside the cable enters a gel within the connector mechanism and the optical fiber of one cable comes into contact with the optical fiber of another cable within the gel inside the connector mechanism.
The illustrative rack 240 also includes a fan array 370 coupled to the cross-support arms of the rack 240. The fan array 370 includes one or more rows of cooling fans 372, which are aligned in a horizontal line between the elongated support posts 302, 304. In the illustrative embodiment, the fan array 370 includes a row of cooling fans 372 for each sled slot 320 of the rack 240. As discussed above, each sled 400 does not include any on-board cooling system in the illustrative embodiment and, as such, the fan array 370 provides cooling for each sled 400 received in the rack 240. Each rack 240, in the illustrative embodiment, also includes a power supply associated with each sled slot 320. Each power supply is secured to one of the elongated support arms 312 of the pair 310 of elongated support arms 312 that define the corresponding sled slot 320. For example, the rack 240 may include a power supply coupled or secured to each elongated support arm 312 extending from the elongated support post 302. Each power supply includes a power connector configured to mate with a power connector of the sled 400 when the sled 400 is received in the corresponding sled slot 320. In the illustrative embodiment, the sled 400 does not include any on-board power supply and, as such, the power supplies provided in the rack 240 supply power to corresponding sleds 400 when mounted to the rack 240.
Referring now to FIG. 6, the sled 400, in the illustrative embodiment, is configured to be mounted in a corresponding rack 240 of the data center 100 as discussed above. In some embodiments, each sled 400 may be optimized or otherwise configured for performing particular tasks, such as compute tasks, acceleration tasks, data storage tasks, etc. For example, the sled 400 may be embodied as a compute sled 800 as discussed below in regard to FIGS. 8-9, an accelerator sled 1000 as discussed below in regard to FIGS. 10-11, a storage sled 1200 as discussed below in regard to FIGS. 12-13, or as a sled optimized or otherwise configured to perform other specialized tasks, such as a memory sled 1400, discussed below in regard to FIG. 14.
As discussed above, the illustrative sled 400 includes a chassis-less circuit board substrate 602, which supports various physical resources (e.g., electrical components) mounted thereon. It should be appreciated that the circuit board substrate 602 is “chassis-less” in that the sled 400 does not include a housing or enclosure. Rather, the chassis-less circuit board substrate 602 is open to the local environment. The chassis-less circuit board substrate 602 may be formed from any material capable of supporting the various electrical components mounted thereon. For example, in an illustrative embodiment, the chassis-less circuit board substrate 602 is formed from an FR-4 glass-reinforced epoxy laminate material. Of course, other materials may be used to form the chassis-less circuit board substrate 602 in other embodiments.
As discussed in more detail below, the chassis-less circuit board substrate 602 includes multiple features that improve the thermal cooling characteristics of the various electrical components mounted on the chassis-less circuit board substrate 602. As discussed, the chassis-less circuit board substrate 602 does not include a housing or enclosure, which may improve the airflow over the electrical components of the sled 400 by reducing those structures that may inhibit air flow. For example, because the chassis-less circuit board substrate 602 is not positioned in an individual housing or enclosure, there is no backplane (e.g., a backplate of the chassis) to the chassis-less circuit board substrate 602, which could inhibit air flow across the electrical components. Additionally, the chassis-less circuit board substrate 602 has a geometric shape configured to reduce the length of the airflow path across the electrical components mounted to the chassis-less circuit board substrate 602. For example, the illustrative chassis-less circuit board substrate 602 has a width 604 that is greater than a depth 606 of the chassis-less circuit board substrate 602. In one particular embodiment, for example, the chassis-less circuit board substrate 602 has a width of about 21 inches and a depth of about 9 inches, compared to a typical server that has a width of about 17 inches and a depth of about 39 inches. As such, an airflow path 608 that extends from a front edge 610 of the chassis-less circuit board substrate 602 toward a rear edge 612 has a shorter distance relative to typical servers, which may improve the thermal cooling characteristics of the sled 400. Furthermore, although not illustrated in FIG. 6, the various physical resources mounted to the chassis-less circuit board substrate 602 are mounted in corresponding locations such that no two substantively heat-producing electrical components shadow each other as discussed in more detail below. That is, no two electrical components, which produce appreciable heat during operation (i.e., greater than a nominal heat sufficient enough to adversely impact the cooling of another electrical component), are mounted to the chassis-less circuit board substrate 602 linearly in-line with each other along the direction of the airflow path 608 (i.e., along a direction extending from the front edge 610 toward the rear edge 612 of the chassis-less circuit board substrate 602).
As discussed above, the illustrative sled 400 includes one or more physical resources 620 mounted to a top side 650 of the chassis-less circuit board substrate 602. Although two physical resources 620 are shown in FIG. 6, it should be appreciated that the sled 400 may include one, two, or more physical resources 620 in other embodiments. The physical resources 620 may be embodied as any type of processor, controller, or other compute circuit capable of performing various tasks such as compute functions and/or controlling the functions of the sled 400 depending on, for example, the type or intended functionality of the sled 400. For example, as discussed in more detail below, the physical resources 620 may be embodied as high-performance processors in embodiments in which the sled 400 is embodied as a compute sled, as accelerator co-processors or circuits in embodiments in which the sled 400 is embodied as an accelerator sled, storage controllers in embodiments in which the sled 400 is embodied as a storage sled, or a set of memory devices in embodiments in which the sled 400 is embodied as a memory sled.
The sled 400 also includes one or more additional physical resources 630 mounted to the top side 650 of the chassis-less circuit board substrate 602. In the illustrative embodiment, the additional physical resources include a network interface controller (NIC) as discussed in more detail below. Of course, depending on the type and functionality of the sled 400, the physical resources 630 may include additional or other electrical components, circuits, and/or devices in other embodiments.
The physical resources 620 are communicatively coupled to the physical resources 630 via an input/output (I/O) subsystem 622. The I/O subsystem 622 may be embodied as circuitry and/or components to facilitate input/output operations with the physical resources 620, the physical resources 630, and/or other components of the sled 400. For example, the I/O subsystem 622 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In the illustrative embodiment, the I/O subsystem 622 is embodied as, or otherwise includes, a double data rate 4 (DDR4) data bus or a DDR5 data bus.
In some embodiments, the sled 400 may also include a resource-to-resource interconnect 624. The resource-to-resource interconnect 624 may be embodied as any type of communication interconnect capable of facilitating resource-to-resource communications. In the illustrative embodiment, the resource-to-resource interconnect 624 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the resource-to-resource interconnect 624 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to resource-to-resource communications.
The sled 400 also includes a power connector 640 configured to mate with a corresponding power connector of the rack 240 when the sled 400 is mounted in the corresponding rack 240. The sled 400 receives power from a power supply of the rack 240 via the power connector 640 to supply power to the various electrical components of the sled 400. That is, the sled 400 does not include any local power supply (i.e., an on-board power supply) to provide power to the electrical components of the sled 400. The exclusion of a local or on-board power supply facilitates the reduction in the overall footprint of the chassis-less circuit board substrate 602, which may increase the thermal cooling characteristics of the various electrical components mounted on the chassis-less circuit board substrate 602 as discussed above. In some embodiments, power is provided to the processors 820 through vias directly under the processors 820 (e.g., through the bottom side 750 of the chassis-less circuit board substrate 602), providing an increased thermal budget, additional current and/or voltage, and better voltage control over typical boards.
In some embodiments, the sled 400 may also include mounting features 642 configured to mate with a mounting arm, or other structure, of a robot to facilitate the placement of the sled 600 in a rack 240 by the robot. The mounting features 642 may be embodied as any type of physical structures that allow the robot to grasp the sled 400 without damaging the chassis-less circuit board substrate 602 or the electrical components mounted thereto. For example, in some embodiments, the mounting features 642 may be embodied as non-conductive pads attached to the chassis-less circuit board substrate 602. In other embodiments, the mounting features may be embodied as brackets, braces, or other similar structures attached to the chassis-less circuit board substrate 602. The particular number, shape, size, and/or make-up of the mounting feature 642 may depend on the design of the robot configured to manage the sled 400.
Referring now to FIG. 7, in addition to the physical resources 630 mounted on the top side 650 of the chassis-less circuit board substrate 602, the sled 400 also includes one or more memory devices 720 mounted to a bottom side 750 of the chassis-less circuit board substrate 602. That is, the chassis-less circuit board substrate 602 is embodied as a double-sided circuit board. The physical resources 620 are communicatively coupled to the memory devices 720 via the I/O subsystem 622. For example, the physical resources 620 and the memory devices 720 may be communicatively coupled by one or more vias extending through the chassis-less circuit board substrate 602. Each physical resource 620 may be communicatively coupled to a different set of one or more memory devices 720 in some embodiments. Alternatively, in other embodiments, each physical resource 620 may be communicatively coupled to each memory devices 720.
The memory devices 720 may be embodied as any type of memory device capable of storing data for the physical resources 620 during operation of the sled 400, such as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.
In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include next-generation nonvolatile devices, such as Intel 3D XPoint™ memory or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product. In some embodiments, the memory device may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance.
Referring now to FIG. 8, in some embodiments, the sled 400 may be embodied as a compute sled 800. The compute sled 800 is optimized, or otherwise configured, to perform compute tasks. Of course, as discussed above, the compute sled 800 may rely on other sleds, such as acceleration sleds and/or storage sleds, to perform such compute tasks. The compute sled 800 includes various physical resources (e.g., electrical components) similar to the physical resources of the sled 400, which have been identified in FIG. 8 using the same reference numbers. The description of such components provided above in regard to FIGS. 6 and 7 applies to the corresponding components of the compute sled 800 and is not repeated herein for clarity of the description of the compute sled 800.
In the illustrative compute sled 800, the physical resources 620 are embodied as processors 820. Although only two processors 820 are shown in FIG. 8, it should be appreciated that the compute sled 800 may include additional processors 820 in other embodiments. Illustratively, the processors 820 are embodied as high-performance processors 820 and may be configured to operate at a relatively high power rating. Although the processors 820 generate additional heat operating at power ratings greater than typical processors (which operate at around 155-230 W), the enhanced thermal cooling characteristics of the chassis-less circuit board substrate 602 discussed above facilitate the higher power operation. For example, in the illustrative embodiment, the processors 820 are configured to operate at a power rating of at least 250 W. In some embodiments, the processors 820 may be configured to operate at a power rating of at least 350 W.
In some embodiments, the compute sled 800 may also include a processor-to-processor interconnect 842. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the processor-to-processor interconnect 842 may be embodied as any type of communication interconnect capable of facilitating processor-to-processor interconnect 842 communications. In the illustrative embodiment, the processor-to-processor interconnect 842 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the processor-to-processor interconnect 842 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.
The compute sled 800 also includes a communication circuit 830. The illustrative communication circuit 830 includes a network interface controller (NIC) 832, which may also be referred to as a host fabric interface (HFI). The NIC 832 may be embodied as, or otherwise include, any type of integrated circuit, discrete circuits, controller chips, chipsets, add-in-boards, daughtercards, network interface cards, other devices that may be used by the compute sled 800 to connect with another compute device (e.g., with other sleds 400). In some embodiments, the NIC 832 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, the NIC 832 may include a local processor (not shown) and/or a local memory (not shown) that are both local to the NIC 832. In such embodiments, the local processor of the NIC 832 may be capable of performing one or more of the functions of the processors 820. Additionally or alternatively, in such embodiments, the local memory of the NIC 832 may be integrated into one or more components of the compute sled at the board level, socket level, chip level, and/or other levels.
The communication circuit 830 is communicatively coupled to an optical data connector 834. The optical data connector 834 is configured to mate with a corresponding optical data connector of the rack 240 when the compute sled 800 is mounted in the rack 240. Illustratively, the optical data connector 834 includes a plurality of optical fibers which lead from a mating surface of the optical data connector 834 to an optical transceiver 836. The optical transceiver 836 is configured to convert incoming optical signals from the rack-side optical data connector to electrical signals and to convert electrical signals to outgoing optical signals to the rack-side optical data connector. Although shown as forming part of the optical data connector 834 in the illustrative embodiment, the optical transceiver 836 may form a portion of the communication circuit 830 in other embodiments.
In some embodiments, the compute sled 800 may also include an expansion connector 840. In such embodiments, the expansion connector 840 is configured to mate with a corresponding connector of an expansion chassis-less circuit board substrate to provide additional physical resources to the compute sled 800. The additional physical resources may be used, for example, by the processors 820 during operation of the compute sled 800. The expansion chassis-less circuit board substrate may be substantially similar to the chassis-less circuit board substrate 602 discussed above and may include various electrical components mounted thereto. The particular electrical components mounted to the expansion chassis-less circuit board substrate may depend on the intended functionality of the expansion chassis-less circuit board substrate. For example, the expansion chassis-less circuit board substrate may provide additional compute resources, memory resources, and/or storage resources. As such, the additional physical resources of the expansion chassis-less circuit board substrate may include, but is not limited to, processors, memory devices, storage devices, and/or accelerator circuits including, for example, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), machine learning circuits, or other specialized processors, controllers, devices, and/or circuits.
Referring now to FIG. 9, an illustrative embodiment of the compute sled 800 is shown. As shown, the processors 820, communication circuit 830, and optical data connector 834 are mounted to the top side 650 of the chassis-less circuit board substrate 602. Any suitable attachment or mounting technology may be used to mount the physical resources of the compute sled 800 to the chassis-less circuit board substrate 602. For example, the various physical resources may be mounted in corresponding sockets (e.g., a processor socket), holders, or brackets. In some cases, some of the electrical components may be directly mounted to the chassis-less circuit board substrate 602 via soldering or similar techniques.
As discussed above, the individual processors 820 and communication circuit 830 are mounted to the top side 650 of the chassis-less circuit board substrate 602 such that no two heat-producing, electrical components shadow each other. In the illustrative embodiment, the processors 820 and communication circuit 830 are mounted in corresponding locations on the top side 650 of the chassis-less circuit board substrate 602 such that no two of those physical resources are linearly in-line with others along the direction of the airflow path 608. It should be appreciated that, although the optical data connector 834 is in-line with the communication circuit 830, the optical data connector 834 produces no or nominal heat during operation.
The memory devices 720 of the compute sled 800 are mounted to the bottom side 750 of the of the chassis-less circuit board substrate 602 as discussed above in regard to the sled 400. Although mounted to the bottom side 750, the memory devices 720 are communicatively coupled to the processors 820 located on the top side 650 via the I/O subsystem 622. Because the chassis-less circuit board substrate 602 is embodied as a double-sided circuit board, the memory devices 720 and the processors 820 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-less circuit board substrate 602. Of course, each processor 820 may be communicatively coupled to a different set of one or more memory devices 720 in some embodiments. Alternatively, in other embodiments, each processor 820 may be communicatively coupled to each memory device 720. In some embodiments, the memory devices 720 may be mounted to one or more memory mezzanines on the bottom side of the chassis-less circuit board substrate 602 and may interconnect with a corresponding processor 820 through a ball-grid array.
Each of the processors 820 includes a heatsink 850 secured thereto. Due to the mounting of the memory devices 720 to the bottom side 750 of the chassis-less circuit board substrate 602 (as well as the vertical spacing of the sleds 400 in the corresponding rack 240), the top side 650 of the chassis-less circuit board substrate 602 includes additional “free” area or space that facilitates the use of heatsinks 850 having a larger size relative to traditional heatsinks used in typical servers. Additionally, due to the improved thermal cooling characteristics of the chassis-less circuit board substrate 602, none of the processor heatsinks 850 include cooling fans attached thereto. That is, each of the heatsinks 850 is embodied as a fan-less heatsinks.
Referring now to FIG. 10, in some embodiments, the sled 400 may be embodied as an accelerator sled 1000. The accelerator sled 1000 is optimized, or otherwise configured, to perform specialized compute tasks, such as machine learning, encryption, hashing, or other computational-intensive task. In some embodiments, for example, a compute sled 800 may offload tasks to the accelerator sled 1000 during operation. The accelerator sled 1000 includes various components similar to components of the sled 400 and/or compute sled 800, which have been identified in FIG. 10 using the same reference numbers. The description of such components provided above in regard to FIGS. 6, 7, and 8 apply to the corresponding components of the accelerator sled 1000 and is not repeated herein for clarity of the description of the accelerator sled 1000.
In the illustrative accelerator sled 1000, the physical resources 620 are embodied as accelerator circuits 1020. Although only two accelerator circuits 1020 are shown in FIG. 10, it should be appreciated that the accelerator sled 1000 may include additional accelerator circuits 1020 in other embodiments. For example, as shown in FIG. 11, the accelerator sled 1000 may include four accelerator circuits 1020 in some embodiments. The accelerator circuits 1020 may be embodied as any type of processor, co-processor, compute circuit, or other device capable of performing compute or processing operations. For example, the accelerator circuits 1020 may be embodied as, for example, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), machine learning circuits, or other specialized processors, controllers, devices, and/or circuits.
In some embodiments, the accelerator sled 1000 may also include an accelerator-to-accelerator interconnect 1042. Similar to the resource-to-resource interconnect 624 of the sled 600 discussed above, the accelerator-to-accelerator interconnect 1042 may be embodied as any type of communication interconnect capable of facilitating accelerator-to-accelerator communications. In the illustrative embodiment, the accelerator-to-accelerator interconnect 1042 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the accelerator-to-accelerator interconnect 1042 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. In some embodiments, the accelerator circuits 1020 may be daisy-chained with a primary accelerator circuit 1020 connected to the NIC 832 and memory 720 through the I/O subsystem 622 and a secondary accelerator circuit 1020 connected to the NIC 832 and memory 720 through a primary accelerator circuit 1020.
Referring now to FIG. 11, an illustrative embodiment of the accelerator sled 1000 is shown. As discussed above, the accelerator circuits 1020, communication circuit 830, and optical data connector 834 are mounted to the top side 650 of the chassis-less circuit board substrate 602. Again, the individual accelerator circuits 1020 and communication circuit 830 are mounted to the top side 650 of the chassis-less circuit board substrate 602 such that no two heat-producing, electrical components shadow each other as discussed above. The memory devices 720 of the accelerator sled 1000 are mounted to the bottom side 750 of the of the chassis-less circuit board substrate 602 as discussed above in regard to the sled 600. Although mounted to the bottom side 750, the memory devices 720 are communicatively coupled to the accelerator circuits 1020 located on the top side 650 via the I/O subsystem 622 (e.g., through vias). Further, each of the accelerator circuits 1020 may include a heatsink 1070 that is larger than a traditional heatsink used in a server. As discussed above with reference to the heatsinks 870, the heatsinks 1070 may be larger than tradition heatsinks because of the “free” area provided by the memory devices 750 being located on the bottom side 750 of the chassis-less circuit board substrate 602 rather than on the top side 650.
Referring now to FIG. 12, in some embodiments, the sled 400 may be embodied as a storage sled 1200. The storage sled 1200 is optimized, or otherwise configured, to store data in a data storage 1250 local to the storage sled 1200. For example, during operation, a compute sled 800 or an accelerator sled 1000 may store and retrieve data from the data storage 1250 of the storage sled 1200. The storage sled 1200 includes various components similar to components of the sled 400 and/or the compute sled 800, which have been identified in FIG. 12 using the same reference numbers. The description of such components provided above in regard to FIGS. 6, 7, and 8 apply to the corresponding components of the storage sled 1200 and is not repeated herein for clarity of the description of the storage sled 1200.
In the illustrative storage sled 1200, the physical resources 620 are embodied as storage controllers 1220. Although only two storage controllers 1220 are shown in FIG. 12, it should be appreciated that the storage sled 1200 may include additional storage controllers 1220 in other embodiments. The storage controllers 1220 may be embodied as any type of processor, controller, or control circuit capable of controlling the storage and retrieval of data into the data storage 1250 based on requests received via the communication circuit 830. In the illustrative embodiment, the storage controllers 1220 are embodied as relatively low-power processors or controllers. For example, in some embodiments, the storage controllers 1220 may be configured to operate at a power rating of about 75 watts.
In some embodiments, the storage sled 1200 may also include a controller-to-controller interconnect 1242. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the controller-to-controller interconnect 1242 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect 1242 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the controller-to-controller interconnect 1242 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.
Referring now to FIG. 13, an illustrative embodiment of the storage sled 1200 is shown. In the illustrative embodiment, the data storage 1250 is embodied as, or otherwise includes, a storage cage 1252 configured to house one or more solid state drives (SSDs) 1254. To do so, the storage cage 1252 includes a number of mounting slots 1256, each of which is configured to receive a corresponding solid state drive 1254. Each of the mounting slots 1256 includes a number of drive guides 1258 that cooperate to define an access opening 1260 of the corresponding mounting slot 1256. The storage cage 1252 is secured to the chassis-less circuit board substrate 602 such that the access openings face away from (i.e., toward the front of) the chassis-less circuit board substrate 602. As such, solid state drives 1254 are accessible while the storage sled 1200 is mounted in a corresponding rack 204. For example, a solid state drive 1254 may be swapped out of a rack 240 (e.g., via a robot) while the storage sled 1200 remains mounted in the corresponding rack 240.
The storage cage 1252 illustratively includes sixteen mounting slots 1256 and is capable of mounting and storing sixteen solid state drives 1254. Of course, the storage cage 1252 may be configured to store additional or fewer solid state drives 1254 in other embodiments. Additionally, in the illustrative embodiment, the solid state drivers are mounted vertically in the storage cage 1252, but may be mounted in the storage cage 1252 in a different orientation in other embodiments. Each solid state drive 1254 may be embodied as any type of data storage device capable of storing long term data. To do so, the solid state drives 1254 may include volatile and non-volatile memory devices discussed above.
As shown in FIG. 13, the storage controllers 1220, the communication circuit 830, and the optical data connector 834 are illustratively mounted to the top side 650 of the chassis-less circuit board substrate 602. Again, as discussed above, any suitable attachment or mounting technology may be used to mount the electrical components of the storage sled 1200 to the chassis-less circuit board substrate 602 including, for example, sockets (e.g., a processor socket), holders, brackets, soldered connections, and/or other mounting or securing techniques.
As discussed above, the individual storage controllers 1220 and the communication circuit 830 are mounted to the top side 650 of the chassis-less circuit board substrate 602 such that no two heat-producing, electrical components shadow each other. For example, the storage controllers 1220 and the communication circuit 830 are mounted in corresponding locations on the top side 650 of the chassis-less circuit board substrate 602 such that no two of those electrical components are linearly in-line with other along the direction of the airflow path 608.
The memory devices 720 of the storage sled 1200 are mounted to the bottom side 750 of the of the chassis-less circuit board substrate 602 as discussed above in regard to the sled 400. Although mounted to the bottom side 750, the memory devices 720 are communicatively coupled to the storage controllers 1220 located on the top side 650 via the I/O subsystem 622. Again, because the chassis-less circuit board substrate 602 is embodied as a double-sided circuit board, the memory devices 720 and the storage controllers 1220 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-less circuit board substrate 602. Each of the storage controllers 1220 includes a heatsink 1270 secured thereto. As discussed above, due to the improved thermal cooling characteristics of the chassis-less circuit board substrate 602 of the storage sled 1200, none of the heatsinks 1270 include cooling fans attached thereto. That is, each of the heatsinks 1270 is embodied as a fan-less heatsink.
Referring now to FIG. 14, in some embodiments, the sled 400 may be embodied as a memory sled 1400. The storage sled 1400 is optimized, or otherwise configured, to provide other sleds 400 (e.g., compute sleds 800, accelerator sleds 1000, etc.) with access to a pool of memory (e.g., in two or more sets 1430, 1432 of memory devices 720) local to the memory sled 1200. For example, during operation, a compute sled 800 or an accelerator sled 1000 may remotely write to and/or read from one or more of the memory sets 1430, 1432 of the memory sled 1200 using a logical address space that maps to physical addresses in the memory sets 1430, 1432. The memory sled 1400 includes various components similar to components of the sled 400 and/or the compute sled 800, which have been identified in FIG. 14 using the same reference numbers. The description of such components provided above in regard to FIGS. 6, 7, and 8 apply to the corresponding components of the memory sled 1400 and is not repeated herein for clarity of the description of the memory sled 1400.
In the illustrative memory sled 1400, the physical resources 620 are embodied as memory controllers 1420. Although only two memory controllers 1420 are shown in FIG. 14, it should be appreciated that the memory sled 1400 may include additional memory controllers 1420 in other embodiments. The memory controllers 1420 may be embodied as any type of processor, controller, or control circuit capable of controlling the writing and reading of data into the memory sets 1430, 1432 based on requests received via the communication circuit 830. In the illustrative embodiment, each storage controller 1220 is connected to a corresponding memory set 1430, 1432 to write to and read from memory devices 720 within the corresponding memory set 1430, 1432 and enforce any permissions (e.g., read, write, etc.) associated with sled 400 that has sent a request to the memory sled 1400 to perform a memory access operation (e.g., read or write).
In some embodiments, the memory sled 1400 may also include a controller-to-controller interconnect 1442. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the controller-to-controller interconnect 1442 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect 1442 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the controller-to-controller interconnect 1442 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. As such, in some embodiments, a memory controller 1420 may access, through the controller-to-controller interconnect 1442, memory that is within the memory set 1432 associated with another memory controller 1420. In some embodiments, a scalable memory controller is made of multiple smaller memory controllers, referred to herein as “chiplets”, on a memory sled (e.g., the memory sled 1400). The chiplets may be interconnected (e.g., using EMIB (Embedded Multi-Die Interconnect Bridge)). The combined chiplet memory controller may scale up to a relatively large number of memory controllers and I/O ports, (e.g., up to 16 memory channels). In some embodiments, the memory controllers 1420 may implement a memory interleave (e.g., one memory address is mapped to the memory set 1430, the next memory address is mapped to the memory set 1432, and the third address is mapped to the memory set 1430, etc.). The interleaving may be managed within the memory controllers 1420, or from CPU sockets (e.g., of the compute sled 800) across network links to the memory sets 1430, 1432, and may improve the latency associated with performing memory access operations as compared to accessing contiguous memory addresses from the same memory device.
Further, in some embodiments, the memory sled 1400 may be connected to one or more other sleds 400 (e.g., in the same rack 240 or an adjacent rack 240) through a waveguide, using the waveguide connector 1480. In the illustrative embodiment, the waveguides are 64 millimeter waveguides that provide 16 Rx (i.e., receive) lanes and 16 Rt (i.e., transmit) lanes. Each lane, in the illustrative embodiment, is either 16 Ghz or 32 Ghz. In other embodiments, the frequencies may be different. Using a waveguide may provide high throughput access to the memory pool (e.g., the memory sets 1430, 1432) to another sled (e.g., a sled 400 in the same rack 240 or an adjacent rack 240 as the memory sled 1400) without adding to the load on the optical data connector 834.
Referring now to FIG. 15, a system for executing one or more workloads (e.g., applications) may be implemented in accordance with the data center 100. In the illustrative embodiment, the system 1510 includes an orchestrator server 1520, which may be embodied as a managed node comprising a compute device (e.g., a compute sled 800) executing management software (e.g., a cloud operating environment, such as OpenStack) that is communicatively coupled to multiple sleds 400 including a large number of compute sleds 1530 (e.g., each similar to the compute sled 800), memory sleds 1540 (e.g., each similar to the memory sled 1400), accelerator sleds 1550 (e.g., each similar to the memory sled 1000), and storage sleds 1560 (e.g., each similar to the storage sled 1200). One or more of the sleds 1530, 1540, 1550, 1560 may be grouped into a managed node 1570, such as by the orchestrator server 1520, to collectively perform a workload (e.g., an application 1532 executed in a virtual machine or in a container). The managed node 1570 may be embodied as an assembly of physical resources 620, such as processors 820, memory resources 720, accelerator circuits 1020, or data storage 1250, from the same or different sleds 400. Further, the managed node may be established, defined, or “spun up” by the orchestrator server 1520 at the time a workload is to be assigned to the managed node or at any other time, and may exist regardless of whether any workloads are presently assigned to the managed node. In the illustrative embodiment, the orchestrator server 1520 may selectively allocate and/or deallocate physical resources 620 from the sleds 400 and/or add or remove one or more sleds 400 from the managed node 1570 as a function of quality of service (QoS) targets (e.g., performance targets associated with a throughput, latency, instructions per second, etc.) associated with a service level agreement for the workload (e.g., the application 1532). In doing so, the orchestrator server 1520 may receive telemetry data indicative of performance conditions (e.g., throughput, latency, instructions per second, etc.) in each sled 400 of the managed node 1570 and compare the telemetry data to the quality of service targets to determine whether the quality of service targets are being satisfied. If the so, the orchestrator server 1520 may additionally determine whether one or more physical resources may be deallocated from the managed node 1570 while still satisfying the QoS targets, thereby freeing up those physical resources for use in another managed node (e.g., to execute a different workload). Alternatively, if the QoS targets are not presently satisfied, the orchestrator server 1520 may determine to dynamically allocate additional physical resources to assist in the execution of the workload (e.g., the application 1532) while the workload is executing
Additionally, in some embodiments, the orchestrator server 1520 may identify trends in the resource utilization of the workload (e.g., the application 1532), such as by identifying phases of execution (e.g., time periods in which different operations, each having different resource utilizations characteristics, are performed) of the workload (e.g., the application 1532) and pre-emptively identifying available resources in the data center 100 and allocating them to the managed node 1570 (e.g., within a predefined time period of the associated phase beginning). In some embodiments, the orchestrator server 1520 may model performance based on various latencies and a distribution scheme to place workloads among compute sleds and other resources (e.g., accelerator sleds, memory sleds, storage sleds) in the data center 100. For example, the orchestrator server 1520 may utilize a model that accounts for the performance of resources on the sleds 400 (e.g., FPGA performance, memory access latency, etc.) and the performance (e.g., congestion, latency, bandwidth) of the path through the network to the resource (e.g., FPGA). As such, the orchestrator server 1520 may determine which resource(s) should be used with which workloads based on the total latency associated with each potential resource available in the data center 100 (e.g., the latency associated with the performance of the resource itself in addition to the latency associated with the path through the network between the compute sled executing the workload and the sled 400 on which the resource is located).
In some embodiments, the orchestrator server 1520 may generate a map of heat generation in the data center 100 using telemetry data (e.g., temperatures, fan speeds, etc.) reported from the sleds 400 and allocate resources to managed nodes as a function of the map of heat generation and predicted heat generation associated with different workloads, to maintain a target temperature and heat distribution in the data center 100. Additionally or alternatively, in some embodiments, the orchestrator server 1520 may organize received telemetry data into a hierarchical model that is indicative of a relationship between the managed nodes (e.g., a spatial relationship such as the physical locations of the resources of the managed nodes within the data center 100 and/or a functional relationship, such as groupings of the managed nodes by the customers the managed nodes provide services for, the types of functions typically performed by the managed nodes, managed nodes that typically share or exchange workloads among each other, etc.). Based on differences in the physical locations and resources in the managed nodes, a given workload may exhibit different resource utilizations (e.g., cause a different internal temperature, use a different percentage of processor or memory capacity) across the resources of different managed nodes. The orchestrator server 1520 may determine the differences based on the telemetry data stored in the hierarchical model and factor the differences into a prediction of future resource utilization of a workload if the workload is reassigned from one managed node to another managed node, to accurately balance resource utilization in the data center 100.
To reduce the computational load on the orchestrator server 1520 and the data transfer load on the network, in some embodiments, the orchestrator server 1520 may send self-test information to the sleds 400 to enable each sled 400 to locally (e.g., on the sled 400) determine whether telemetry data generated by the sled 400 satisfies one or more conditions (e.g., an available capacity that satisfies a predefined threshold, a temperature that satisfies a predefined threshold, etc.). Each sled 400 may then report back a simplified result (e.g., yes or no) to the orchestrator server 1520, which the orchestrator server 1520 may utilize in determining the allocation of resources to managed nodes.
Referring now to FIG. 16, a system 1600 for providing efficient transfer of results from accelerator devices in a disaggregated architecture may be implemented in accordance with the data center 100 described above with reference to FIGS. 1-15. Providing efficient transfer of results from an accelerator device may be embodied as or include decreasing the amount of data to be sent through a network to communicate a resulting data object after an accelerator device has operated on (e.g., performed a function, such as a mathematical domain transformation, encryption or decryption, reformatting, etc.) a data object that was provided to the accelerator device (e.g., from a compute sled). For example, a compute sled in the system 1600 may execute a workload and may send a data object to a remote accelerator sled to access an accelerator device to increase the speed of execution of the workload associated with the data object. The accelerator sled may track the changes made to the object with a modification map and send the modification map with the modified data to the compute sled, rather than sending the entire modified data object. From the modification map and the modified data, the compute sled may identify the portions where changes to the data object occurred and produce the modified version of the data object. Doing so may increase the speed of execution of the workload and free-up the network for use by other sleds in the system 1600.
In the illustrative embodiment, the system 1600 includes a pod manager 1602 in communication with a compute sled 1604 and an accelerator sled 1606. Although only one compute sled and one accelerator sled is shown, there may be any number of compute sleds and/or accelerator sleds utilized in the system 1600. One or more of the sleds 1604, 1606 may be grouped into a managed node, such as by the pod manager 1602, to collectively perform a workload, such as an application. A managed node may be embodied as an assembly of resources, such as compute resources, memory resources, storage resources, or other resources, from the same or different sleds or racks. Further, a managed node may be established, defined, or “spun up” by the pod manager 1602 at the time a workload is to be assigned to the managed node or at any other time, and may exist regardless of whether any workloads are presently assigned to the managed node. The system 1600 may be located in a data center and provide storage and compute services (e.g., cloud services) to a client device 1630 that is in communication with the system 1600 through a network 1640. The pod manager 1602 may support a cloud operating environment, such as OpenStack, and managed nodes established by the pod manager 1602 may execute one or more applications or processes (i.e., workloads), such as in virtual machines or containers, on behalf of a user of the client device 1630. In the illustrative embodiment, the compute sled 1604 utilizes a central processing unit (CPU) 1608 to execute a workload 1610 (e.g., an application) and a network interface controller (NIC) 1612 that includes a data merger logic unit 1614, which may be embodied as any device or circuitry capable of merging changes made to a data object with an original version of the data object to update the original version of the data object. In doing so, and as described in more detail herein, the data merger logic unit 1614 utilizes a modification map provided by an accelerator sled (e.g., the accelerator sled 1606) that operated on the original version of the data object. The accelerator sled 1606 includes a network interface controller (NIC) 1616 and a modification tracker logic unit 1618, which may be embodied as any device or circuitry capable of tracking or logging changes to a data object with a modification map. The accelerator sled 1606 also includes an accelerator device 1620. The accelerator device 1620 may be embodied as a field programmable gate array (FPGA) or other device or circuitry capable of accelerating the execution of a workload, such an application-specific integrated circuit (ASIC), a co-processor, etc.
In operation, the system 1600 may begin to execute a workload 1610 with the CPU 1608 of the compute sled 1604. While in operation, the compute sled 1604 may send a request to the accelerator sled 1606 to utilize the accelerator device 1620 to perform one or more accelerated functions (e.g., an encryption function or other function). The request sent to the accelerator sled 1606 may include a data object associated with the workload 1610 and data indicative of one or more accelerated functions to be executed on the data object. After receiving the data object and data indicative of the one or more functions to be executed, the accelerator sled 1606 may execute the function(s) to process the data object and keep track of the changes to the data object through the modification tracker logic unit 1618. The modification tracker logic unit 1618 records the changes using a modification map, which may be embodied as any data (e.g., a bit map) indicative of portions of the data object where the data has been modified from its original form. The accelerator sled 1606 subsequently sends the modified data and the modification map, rather than the entire modified data object, to the compute sled 1604, which, in turn, reconstructs the modified data object in memory, as discussed above.
Referring now to FIG. 17, the compute sled 1604 may be embodied as any type of compute device capable of performing the functions described herein, including sending a data object to an accelerator sled 1606 and receiving a corresponding modification map and modified data from the accelerator sled 1606. In some embodiments, the compute sled 1604 may receive any data that may support the storing of changes to an original data object sent to be processed by the accelerator sled 1606. As shown in FIG. 17, the illustrative compute sled 1604 includes a compute engine 1702, an input/output (I/O) subsystem 1704, and communication circuitry 1706. In some embodiments, the compute sled 1604 may further include one or more data storage devices 1708 and/or one or more peripheral devices 1710. Of course, in other embodiments, the compute sled 1604 may include other or additional components, such as those commonly found in a compute sled. Additionally, in some embodiments, one or more of the illustrative components may be incorporated in, or otherwise form a portion of, another component.
The compute engine 1702 may be embodied as any type of device or collection of devices capable of performing various compute functions described below. In some embodiments, the compute engine 1702 may be embodied as a single device such as an integrated circuit, an embedded system, a field-programmable gate array (FPGA), a system-on-a-chip (SOC), or other integrated system or device. Additionally, in some embodiments, the compute engine 1702 includes or is embodied as a processor 1712 and a memory 1714. The processor 1712 may be embodied as any type of processor capable of performing the functions described herein. For example, the processor 1712 may be embodied as a single or multi-core processor(s), a microcontroller, or other processor or processing/controlling circuit. In some embodiments, the processor 1712 may be embodied as, include, or be coupled to an FPGA, an application specific integrated circuit (ASIC), reconfigurable hardware or hardware circuitry, or other specialized hardware to facilitate performance of the functions described herein.
The memory 1714 may be embodied as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory or data storage capable of performing the functions described herein. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.
In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include future generation nonvolatile devices, such as a three dimensional crosspoint memory device, or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product.
In some embodiments, 3D crosspoint memory may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance. In operation, the memory 1714 may store various software and data used during operation such as applications, programs, libraries, and drivers.
The I/O subsystem 1704 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, sensor hubs, host controllers, firmware devices, communication links (i.e., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.) and/or other components and subsystems to facilitate the input/output operations. Additionally, in some embodiments, the I/O subsystem 1704 may form a portion of a system-on-a-chip (SoC) and be incorporated, along with the processor 1712, the memory 1714, and other components of the compute sled 1604, on a single integrated circuit chip.
The communication circuitry 1706 may include the network interface controller (NIC) 1612, which may also be referred to as a host fabric interface (HFI). The NIC 1612 may be embodied as one or more add-in-boards, daughter cards, network interface cards, controller chips, chipsets, or other devices that may be used by the compute sled 1604 to connect with another compute device (e.g., the accelerator sled 1606, the POD manager 1602, etc.). In some embodiments, the NIC 1612 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, the NIC 1612 may include a local processor (not shown) and/or a local memory (not shown) that are both local to the NIC 1612. In such embodiments, the local processor of the NIC 1612 may be capable of performing one or more of the functions of the compute engine 1702 described herein. Additionally or alternatively, in such embodiments, the local memory of the NIC 1612 may be integrated into one or more components of the compute sled 1604 at the board level, socket level, chip level, and/or other levels. The data merger logic unit 1614 may be embodied as a device, circuitry, or collection thereof, capable of combining changes to a data object with an earlier version of the data object stored in memory 1714.
The one or more illustrative data storage devices 1708 may be embodied as any type of devices configured for short-term or long-term storage of data such as, for example, memory devices and circuits, memory cards, hard disk drives, solid-state drives, or other data storage devices. Each data storage device 1708 may include a system partition that stores data and firmware code for the data storage device 1708. Each data storage device 1708 may also include one or more operating system partitions that store data files and executables for operating systems.
Referring now to FIG. 18, the accelerator sled 1606, may be embodied as any type of compute device capable of performing the functions described herein, including executing one or more accelerated functions on a data object and tracking changes to the data object as a result of the executed functions. As shown in FIG. 18, the illustrative accelerator sled includes a compute engine 1802, an I/O subsystem 1803, communication circuitry 1804, one or more accelerator device(s) 1620, and the modification tracker logic unit 1618. In some embodiments, the accelerator sled 1606 may additionally include one or more data storage devices 1810. Of course, in other embodiments, the accelerator sled 1606 may include other or additional components, such as those commonly found in a compute device. Additionally, in some embodiments, one or more of the illustrative components may be incorporated in, or otherwise form a portion of, another component.
The compute engine 1802 may be embodied as any type of device or collection of devices capable of performing various compute functions described below. In some embodiments, the compute engine 1802 may be embodied as a single device such as an integrated circuit, an embedded system, a field-programmable gate array (FPGA), a system-on-a-chip (SOC), or other integrated system or device. Additionally, in some embodiments, the compute engine 1802 includes or is embodied as a processor 1812 and a memory 1814. The processor 1812 may be embodied as any type of processor capable of performing the functions described herein. For example, the processor 1812 may be embodied as a single or multi-core processor(s), a microcontroller, or other processor or processing/controlling circuit. In some embodiments, the processor 1812 may be embodied as, include, or be coupled to an FPGA, an application specific integrated circuit (ASIC), reconfigurable hardware or hardware circuitry, or other specialized hardware to facilitate performance of the functions described herein.
The I/O subsystem 1803 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, sensor hubs, host controllers, firmware devices, communication links (i.e., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.) and/or other components and subsystems to facilitate the input/output operations. Additionally, in some embodiments, the I/O subsystem 1803 may form a portion of a system-on-a-chip (SoC) and be incorporated, along with the processor 1812, the memory 1814, and other components of the accelerator sled 1606, on a single integrated circuit chip.
The memory 1814 may be embodied as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory or data storage capable of performing the functions described herein, similarly to memory 1714. The communication circuitry 1804 may include the network interface controller (NIC) 1616, which may also be referred to as a host fabric interface (HFI). The NIC 1616 may be embodied as one or more add-in-boards, daughter cards, network interface cards, controller chips, chipsets, or other devices that may be used by the accelerator sled 1606 to connect with another compute device (e.g., the compute sled 1604, the POD manager 1602, etc.). In some embodiments, the NIC 1616 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, the NIC 1616 may include a local processor (not shown) and/or a local memory (not shown) that are both local to the NIC 1616. In such embodiments, the local processor of the NIC 1616 may be capable of performing one or more of the functions of the compute engine 1802 described herein. Additionally or alternatively, in such embodiments, the local memory of the NIC 1616 may be integrated into one or more components of the accelerator sled 1606 at the board level, socket level, chip level, and/or other levels.
Each accelerator device 1620 may be embodied as any type of device or collection of devices capable of accelerating the execution of one or more functions. As such, each accelerator device 1620 may be embodied as an FPGA, an application specific integrated circuit (ASIC), reconfigurable hardware or hardware circuitry, or other specialized hardware to facilitate performance of the functions described herein. The modification tracker logic unit 1618 may be embodied as circuitry, device, or collection thereof, capable of tracking changes to an object being processed by the accelerator device 1620. For example, in one embodiment, the compute sled 1604 may generate a data object (e.g., a data set) to be encrypted and send the data object with data indicative of an encryption function (e.g., a bit stream that embodies the encryption function, a reference to a bit stream available to the accelerator sled 1606 to implement the function, etc.) to the accelerator sled 1606 to encrypt the data. The modification tracker logic unit 1618 may create a modification map indicative of the portions of the data object that have been changed as a result of executing the encryption function on the data object. In some embodiments, the modification tracker logic unit 1618 is incorporated into one or more of the accelerator devices 1620. The data storage device(s) 1810 may be embodied as any type of device or devices configured for short-term or long-term storage of data such as, for example, memory devices and circuits, memory cards, hard disk drives, solid-state drives, non-volatile flash memory, or other data storage devices.
The pod manager 1602 and the client device 1630 may have components similar to those described in FIGS. 17 and 18. The description of those components of the compute sled 1604 and accelerator sled 1606 is equally applicable to the description of components of the pod manager 1602 and the client device 1630 and are not repeated herein for clarity of the description. Further, it should be appreciated that the pod manager 1602 and the client device 1630 may include other components, sub-components, and devices commonly found in a computing device, which are not discussed above in reference to the compute sled 1604 and accelerator sled 1606 and not discussed herein for clarity of the description.
As described above, the pod manager 1602, and the sleds 1604, 1606 are illustratively in communication via the network 1640, which may be embodied as any type of wired or wireless communication network, including global networks (e.g., the Internet), local area networks (LANs) or wide area networks (WANs), cellular networks (e.g., Global System for Mobile Communications (GSM), 3G, Long Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WiMAX), etc.), digital subscriber line (DSL) networks, cable networks (e.g., coaxial networks, fiber networks, etc.), or any combination thereof.
Referring now to FIG. 19, the compute sled 1604 may establish an environment 1900 during operation. The illustrative environment 1900 includes a network communicator 1902 and a modification manager 1904. Each of the components of the environment 1900 may be embodied as hardware, firmware, software, or a combination thereof. As such, in some embodiments, one or more of the components of the environment 1900 may be embodied as circuitry or a collection of electrical devices (e.g., network communicator circuitry 1902, modification manager circuitry 1904, etc.). It should be appreciated that, in such embodiments, one or more of the network communicator circuitry 1902 or modification manager circuitry 1904 may form a portion of one or more of the compute engine 1702 (e.g., processor 1712, memory 1714), I/O subsystem 1704, communication circuitry 1706, data storage device(s) 1708, and/or any other components of the compute sled 1604. In the illustrative embodiment, the environment 1900 includes an object database 1912, which may be embodied as any data established by the compute sled 1604 during the execution of one or more workloads by the compute sled 1604. In particular, the object database 1912 may contain data objects (e.g., data sets such as files, images, etc.) created by the compute sled 1604 during execution of one or more workloads. In some embodiments, the object database 1912 may contain an original data object to be sent to the accelerator sled 1606 and modified data associated with the data object (e.g., portions of the data object that have been changed by the accelerator sled 1606). Additionally, the illustrative environment 1900 includes modification map data 1914 indicative of the portions of the data object, such as a data object located in the object database 1912, that have been modified by the accelerator sled 1606 during processing of one or more functions. The modification map data 1914 may divide an object to be processed into portions based on the size of the object. For example, an object that is 1 Megabyte (MB) may be divided into portions of 1 Kilobyte (KB) data increments while an object that is 1 Gigabyte (GB) may be divided into portions of 1 MB data increments. In some embodiments, the modification map data 1514 may include the modified data received from the accelerator sled 1606.
In the illustrative environment 1900, the network communicator 1902, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to facilitate inbound and outbound network communications (e.g., network traffic, network packets, network flows, etc.) to and from the compute sled 1604, respectively. To do so, the network communicator 1902 is configured to receive and process data packets from one system or computing device (e.g., an accelerator sled 1606 and/or a pod manager 1602) and to prepare and send data packets to another computing device or system (e.g., an accelerator sled 1606 and/or a pod manager 1602). Accordingly, in some embodiments, at least a portion of the functionality of the network communicator 1902 may be performed by the communication circuitry 1706, and, in the illustrative embodiment, by the NIC 1612.
The modification manager 1904, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof, is configured to handle requests from a workload (e.g., the application 1610) to accelerate the performance of one or more functions on a data object, provide the data object to the accelerator sled 1606, identify modifications to the data object from being processed by the accelerator sled 1606, and save the changes/modifications to the data object in a memory device (e.g., the memory 1714). To do so, in the illustrative embodiment, the modification manager 1904 includes a request handler 1906, a modification identifier 1908, and a modification merger 1910. In the illustrative embodiment, the request handler 1906 is configured to obtain a request from a workload executed on the compute sled 1604 and send the request, including the corresponding data object to be operated on, and data indicative of one or more accelerated functions to be used to operate on the data object, to the accelerator sled 1606. In doing so, the request handler 1906 is configured to access the object database 1912 to obtain the data object associated with the workload that produced the request.
The modification identifier 1908, in the illustrative embodiment, is configured to receive a modification map and modified data from the accelerator sled 1606 and determine where the changes are located in the data object according to the received modification map. The modification identifier 1908 may store the received modification map and/or the modified data in the modification map data 1914. The modification map data 1914 is indicative of the portions of the data object that has changes as a result of being processed by the accelerator sled 1606, as described above. As such, the modification identifier 1908 determines the portions of the data object that have been changed and the modified data associated with each portion by using the modification map data 1914.
The modification merger 1910, in the illustrative embodiment, is configured to merge the changes received from the accelerator sled 1606 to the data object to locally reconstruct the modified version of the data object in the memory 1714 of the compute sled 1604. To do so, the modification merger 1910 communicates with the modification identifier 1908 to determine the locations of the portions of the data object that underwent changes and merge the modified data with the portions of the data object that correspond to the modified data. The modification merger 1910 may store the modified data object in the object database 1912 to be used for subsequent functions.
It should be appreciated that each of the request handler 1906, the modification identifier 1908, and the modification merger 1910 may be separately embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof. For example, the request handler 1906 may be embodied as a hardware component, while the modification identifier 1908 and the modification merger 1910 are embodied as virtualized hardware components or as some other combination of hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof.
Referring now to FIG. 20, the accelerator sled 1606 may establish an environment 2000 during operation. The illustrative environment 2000 includes a network communicator 2002 and an object manager 2004. Each of the components of the environment 2000 may be embodied as hardware, firmware, software, or a combination thereof. As such, in some embodiments, one or more of the components of the environment 2000 may be embodied as circuitry or a collection of electrical devices (e.g., network communicator circuitry 2002, object manager circuitry 2004, etc.). It should be appreciated that, in such embodiments, one or more of the network communicator circuitry 2002 or object manager circuitry 2004 may form a portion of the compute engine 1802, modification tracker logic unit 1808, accelerator device 1620, communication circuitry 1804, one or more data storage device(s) 1810, and/or any other components of the accelerator sled 1606. In the illustrative embodiment, the environment 2000 includes an object database 2012, which may be embodied as one or more data objects received from the compute sled 1604, or other sleds in the system 1600, and any modified data of the data objects resulting from processing the data object(s) with the accelerator device(s) 1620, similarly to the object database 1912 described above. Additionally, the illustrative environment 2000 includes modification map data 2014, which may be embodied as data indicative of locations within each data object that have been modified during the execution of a function on the accelerator sled 1606, similarly to the modification map data 1914 described above. In some embodiments, the modification map data 2014 may include the modified data of the modified data object. For example, the modification map data 1914 may be embodied as a bitmap with 0's indicating that no modifications have been made on the corresponding portions of the data object, and 1's indicating that modifications have been made on the corresponding portions of the data object, as well as indications of what the modified data is (e.g., as indexes into the object database where the modified data is located, or the modified data itself). In other embodiments, the modification map data 1914 may be formatted in a markup language, such as an extensible markup language (XML), or another format.
In the illustrative environment 2000, the network communicator 2002, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to facilitate inbound and outbound network communications (e.g., network traffic, network packets, network flows, etc.) to and from the accelerator sled 1606, respectively. To do so, the network communicator 2002 is configured to receive and process data packets from one system or computing device (e.g., the compute sled a 1604 and/or the pod manager 1602) and to prepare and send data packets to a computing device or system (e.g., the compute sled 1604 and/or the pod manager 1602). Accordingly, in some embodiments, at least a portion of the functionality of the network communicator 2002 may be performed by the communication circuitry 1804, and, in the illustrative embodiment, by the NIC 1616.
The object manager 2004, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof, is configured to handle requests to execute a function on the accelerator sled 1606 (e.g., with an accelerator device 1620), process a received data object (e.g., from the compute sled 1604), and identify changes made to the data object as a result of execution of the function on the received data object. To do so, in the illustrative embodiment, the object manager 2004 includes a request handler 2006, an accelerated function handler 2008, and a modification tracker 2010. In the illustrative embodiment, the request handler 2006 is configured to receive a request from the compute sled 1604 and send data back to the compute sled 1604. The request may include the data object to be processed and data indicative of one or more accelerated functions. In some embodiments, the request may include an identifier for an accelerated function stored in a database (not shown) to be used to process the data object. In addition, the request handler 2006 is further configured to store data objects in the object database 2012 and/or access the object database 2012 to send data (e.g., modifications made to a data object) to the compute sled 1604.
The accelerated function handler 2008, in the illustrative embodiment, is configured to receive an accelerated function to process the received data object and process the data object with an accelerator device 1620 to increase the speed of execution of a workload (e.g., the application 1610). For example, the accelerated function handler 2008 may receive an encryption function to process a received data object and process the data object (e.g., perform the encryption function on the data in the data object). The modification tracker 2010, in the illustrative embodiment, is configured to track the changes to a data object as a result of executing the accelerated function on the received object. In doing so, the modification tracker 2010 may write a record of the modification and their locations within a data object to a modification map (e.g., in the modification map data 2014). The request handler 2006 may subsequently send the data produced by the modification tracker 2010 to the compute sled 1604.
Referring now to FIG. 21, in use, the compute sled 1604 may execute a method 2100 for providing efficient transfer of results from a remote accelerator device (e.g., an accelerator device 1620 on the accelerator sled 1606). The method 2100 begins with block 2102 in which the compute sled 1604 determines whether to send a request to another sled (e.g., the accelerator sled 1606) to accelerate the execution of a workload (e.g., the application 1610). In the illustrative embodiment, the determination on whether to send the request may be made based on if a workload executing on the compute sled 1604 has requested to utilize an accelerator device not located on the compute sled 1604. If the compute sled 1604 determines to send the request to the accelerator sled 1606, then the method 2100 advances to block 2104, in which the compute sled 1604 sends the request to utilize an accelerator device on the accelerator sled 1606. Otherwise, the method 2100 loops back to block 2102 to again determine whether to send a request to the accelerator sled 1606 (e.g., after continuing to execute the application 1610). In block 2104, in sending the request to the accelerator sled 1606, the compute sled 1604, in the illustrative embodiment, may send a data object to be processed by the accelerator device 1620, as indicated in block 2106. In addition, in some embodiments, in block 2108, the compute sled 1604 may send data indicative of a function for the accelerator device 1620 to execute on the data object. In doing so, the compute sled 1604 may send a bit stream associated with the function to be executed (e.g., any data that includes code usable by the accelerator device 1620 to configure itself to execute a corresponding function, such as in a kernel), as indicated in block 2110. Alternatively, the compute sled 1604 may send an identifier of a bit stream to be executed, as indicated in block 2112. The identifier may be a number or other unique code associated with a bit stream that is already present in the on-board memory (e.g., the memory 1814) of the accelerator sled 1604 or may identify a bit stream that is available to be received from another compute device (e.g., from the pod manager 1602). Further, as indicated in block 2114, the compute sled 1604 may send data indicative of an encryption function to be performed on the data object. Alternatively, the compute sled 1604 may send data indicative of a compression function to be performed on the data object, as indicated in block 2116. In some embodiments, the compute sled 1604 may send data indicative of a mathematical domain transformation function (e.g., a Fourier transform, a discrete cosine transform, etc.) to be performed on the data object, as indicated in block 2118. Alternatively, the compute sled 1604 may send data indicative of a data reformatting function to be performed on the data object, as indicated in block 2120. In other embodiments, the function may be different than the types of functions described above. Further, in the illustrative embodiment, the function to be executed may change only a subset of the data object, rather than changing the entire data object. For example, the function may analyze all of the data in the data object, then change or add a header portion in the data object based on the analysis. In block 2122, the compute sled 1604 may also send modification map portion size data, which may be embodied as any data indicative of the size of portions into which the data object is to be divided, for purposes of tracking changes to the data object. For example, the portions may be of a predefined size (e.g., one kilobyte, one megabyte, etc.) or determined as a function of characteristics of the data object (e.g., a percentage of the total size of the data object).
Subsequently, in block 2124, the compute sled 1604 may receive data from the accelerator sled 1606 indicative of modifications made to the data object. In some embodiments, the compute sled 1604 may operate synchronously, pausing execution of the workload until the data is received from the accelerator sled 1606, while in other embodiments, the compute sled 1604 may operate asynchronously, by continuing execution of the workload and periodically polling the accelerator sled 1606 for the data. Regardless, in receiving the data indicative of modifications made to the data object, the compute sled 1604 may receive a modification map, as indicated in block 2126. In doing so, the compute sled 1604 may receive a bit map that includes values at different positions in the bit map, as indicated in block 2128. Each position in the bit map may correspond to a portion of the data object and each value at the position may indicate whether a modification was made, and in some embodiments, the type of modification (e.g., overwrite, insertion, deletion). Alternatively, the compute sled 1604 may receive the modification map in another format, such as mark-up language file that indicates the portions and the types of modifications using a set of tags that are parsable by the compute sled 1604, as indicated in block 2130. Additionally, in the illustrative embodiment, the compute sled 1604 receives the actual data that was modified, as indicated in block 2132. The modified data may be indexed according to the positions in the modification map where modifications are indicated (e.g., the data at a third position in the modified data corresponds to a third modification indicated in the modification map). In some embodiments, the modified data may be included in the modification map while in other embodiments, the modified data may be received as a separate data set. In embodiments in which the compute sled 1604 includes non-volatile memory (e.g., data storage device(s) 1708), the compute sled 1604 may write the received data to the non-volatile memory for use in a recovery process if the compute sled 1604 is inadvertently reset or loses power, as indicated in block 2134. Subsequently, the method 2100 advances to block 2136 of FIG. 22, in which the compute sled 1604 determines the subsequent course of action as a function of whether modification data was received from the accelerator sled 1606.
Referring now to FIG. 22, if the compute sled 1604 did not receive modification data, the method 2100 loops back to block 2124 in which the compute sled 1604 continues to await the modification data. Otherwise, the method 2100 advances to block 2138, in which the compute sled 1604 determines the size of portions of the data object represented in the modification map. In doing so, and as indicated in block 2140, the compute sled 1604 may determine the size of the portions based on the modification map portion size data sent to the accelerator sled 1606 (e.g., in block 2122). As indicated in block 2142, the compute sled 1604 may determine the size of the portions as function of the size of the data object, as described above. Alternatively, the compute sled 1604 may determine the size of the portions based on a predefined portion size (e.g., one megabyte), regardless of the size of the data object, as indicated in block 2144.
Subsequently, in block 2146, the compute sled 1604 determines the modifications that were made by the accelerator sled 1606 to the data object. In doing so, the compute sled 1604 determines the modification based on the modification map, as indicated in block 2148. In the illustrative embodiment, the compute sled 1604 correlates an index of a modified portion represented in the modification map to a portion of the data object (e.g., by multiplying the size of each portion by the index of the modified portion represented in the modification map), as indicated in block 2150. Further, the compute sled 1604, in the illustrative embodiment, identifies the modified data associated with the modification portion (e.g., by using the indexing scheme described with reference to block 2132), as indicated in block 2152. In the illustrative embodiment, the compute sled 1604 determines, in block 2154, the type of modification(s) to be made to the portion of the data object (e.g., as a function of the value at the corresponding position in the bit map). In doing so, the compute sled 1604 may determine whether a modification is an overwrite of the portion (e.g., if the value at the position is 1), as indicated in block 2156. Additionally or alternatively, the compute sled 1604 may determine, in block 2158, whether a modification is an insertion of data at the portion (e.g., if the value at the position is 2) or, in block 2160, whether a modification is a deletion of data (e.g., if the value at the position is 3). A predefined value (e.g., 0) at a position may indicate that no modification was made to the corresponding portion of the data object. Subsequently, the method 2100 advances to block 2162 of FIG. 23, in which the compute sled 1604 applies the modification to the data object in the on-board memory (e.g., the memory 1714) of the compute sled 1604.
Referring now to FIG. 23, in applying the modifications, the compute sled 1604 may overwrite one or more portions of the data object with corresponding modified data, as indicated in block 2164. Additionally or alternatively, the compute sled 1604 may perform an insertion of data at a portion of the data object and shift the remaining portions of the data object to accommodate the insertion, as indicated in block 2166. Additionally or alternatively, the compute sled 1604 may perform a deletion of a portion of the data object and shift the remaining portions of the data object as a result of the deletion, as indicated in block 2168. Further, the compute sled 1604, in the illustrative embodiment, may write the data to the non-volatile memory (e.g., the data storage device(s) 1708). Subsequently, the compute sled 1604 continues execution of the workload (e.g., the application 1610) and loops back to block 2102 of FIG. 21 to determine again whether to request acceleration of a function.
Referring now to FIG. 24, in use, the accelerator sled 1606 may execute a method 2400 for providing efficient transfer of results from an accelerator device (e.g., an accelerator device 1620) to another sled (e.g., the compute sled 1604). In the illustrative embodiment, the method 2400 begins with block 2402 in which the accelerator sled 1606 receives a request from a compute sled 1604 to perform a function on a data object. In doing so, the accelerator sled 1606 may receive a data object to be processed, as indicated in block 2404. Additionally, as indicated in block 2406, the accelerator sled 1606 may receive data indicative of a function to execute on the data object with an accelerator device 1620. Further, the accelerator sled 1604 may receive modification map portion size data (e.g., the modification map portion size data sent in block 2122 of FIG. 21), as indicated in block 2408.
In block 2410, the accelerator sled 1606 determines the subsequent course of action to perform as a function of whether a request was received in block 2402. If not, the method 2400 loops back to block 2402 to continue to await a request. Otherwise, the method 2400 advances to block 2412 in which the accelerator sled 1606 processes the data object with the function to increase the speed of execution of the workload (e.g., the application 1610). In block 2414, the accelerator sled 1606, in the illustrative embodiment, configures an accelerator device (e.g., the accelerator device 1620) with a bit stream associated with the function to be executed, as indicated in block 2414. In doing so, the accelerator sled 1606 may obtain the bit stream from a remote compute device (e.g., request and receive the bit stream from the pod manager 1602), as indicated in block 2416.
In block 2418, the accelerator sled 1606 tracks, with a modification map, modifications to the data object resulting from the execution of the function. In doing so, the accelerator sled 1606 may intercept writes to the on-board memory (e.g., the memory 1814) of the accelerator sled 1606 made by the accelerator device 1620 in the execution of the function, as indicated in block 2420. Further, as indicated in block 2422, the accelerator sled 1606, in the illustrative embodiment, correlates locations of write operations to the data object in the on-board memory to corresponding portions in the modification map. As indicated in block 2424, the accelerator sled 1606 indicates the modification in the corresponding portion in the modification map. In doing so, the accelerator sled 1606 may indicate an overwrite of data, as indicated in block 2426. Additionally or alternatively, the accelerator sled 1606 may indicate an insertion of data, as indicated in block 2428, and/or may indicate a deletion of data, as indicated in block 2430. In block 2432, the accelerator sled 1606 may format the modification map as a bit map. Alternatively, the accelerator sled 1606 may format the modification map as a mark-up language file, as indicated in block 2434. In other embodiments, the accelerator sled 1606 may produce the modification map in a different format. Regardless, in the illustrative embodiment, the method 2400 subsequently advances to block 2436 of FIG. 25, in which the accelerator sled 1606 sends the modification map to the compute sled 1604.
Referring now to FIG. 25, in sending the modification map to the compute sled 1604, the accelerator sled 1606 also sends the modified data of the data object to the compute sled 1604, as indicated in block 2438. Further, as indicated in block 2440, the accelerator sled 1606 may send data indicative of which item of modified data corresponds to which modified portion represented in the modification map, for use by the compute sled 1604 in reconstructing the modified version of the data object.

EXAMPLES

Illustrative examples of the technologies disclosed herein are provided below. An embodiment of the technologies may include any one or more, and any combination of, the examples described below.
Example 1 includes a compute sled comprising a memory device; a network interface controller coupled to the memory device, wherein the network interface controller includes a modification logic unit to send a request to utilize an accelerator device on an accelerator sled, wherein the request includes a data object to be processed by the accelerator device to increase the speed of execution of a workload associated with the data object; receive a modification map from the accelerator sled, wherein the modification map is indicative of a modification to the data object; determine the modification to the data object based on the modification map; and apply the modification to the data object in the memory device.
Example 2 includes the subject matter of Example 1, and wherein to send the request comprises to send data indicative of a function to be executed by the accelerator device on the data object.
Example 3 includes the subject matter of any of Examples 1 and 2, and wherein to send the data indicative of a function to be executed comprises to send a bit stream that defines the function to be executed.
Example 4 includes the subject matter of any of Examples 1-3, and wherein to send the data indicative of a function to be executed comprises to send an identifier of a bit stream to be used to configure the accelerator device to execute the function.
Example 5 includes the subject matter of any of Examples 1-4, and wherein to send the data indicative of a function to be executed comprises to send data indicative of one or more of an encryption function, a data compression function, a domain transformation function, or a data reformatting function.
Example 6 includes the subject matter of any of Examples 1-5, and wherein to receive a modification map comprises to receive a bit map indicative of portions of the data object that have been modified.
Example 7 includes the subject matter of any of Examples 1-6, and wherein to receive the bit map comprises to receive a bit map that is further indicative of a type of modification made to each modified portion of the data object.
Example 8 includes the subject matter of any of Examples 1-7, and wherein the modification logic unit is further to determine a size of each portion as a function of the size of the data object.
Example 9 includes the subject matter of any of Examples 1-8, and wherein to apply the modification comprises to overwrite a portion of the data object with modified data provided by the accelerator sled.
Example 10 includes the subject matter of any of Examples 1-9, and wherein to apply the modification comprises to insert, in a portion of the data object, data provided by the accelerator sled.
Example 11 includes the subject matter of any of Examples 1-10, and wherein to apply the modification comprises to delete a portion of the data object.
Example 12 includes the subject matter of any of Examples 1-11, and wherein the compute sled further comprises non-volatile memory and the modification logic unit is further to write the modification map to the non-volatile memory.
Example 13 includes the subject matter of any of Examples 1-12, and wherein to determine the modification to the data object comprises to correlate an index of a modified portion represented in the modification map to a portion of the data object.
Example 14 includes a method comprising sending, by a modification logic unit of a network interface controller of a compute sled, a request to utilize an accelerator device on an accelerator sled, wherein the request includes a data object to be processed by the accelerator device to increase the speed of execution of a workload associated with the data object; receiving, by the modification logic unit, a modification map from the accelerator sled, wherein the modification map is indicative of a modification to the data object; determining, by the modification logic unit, the modification to the data object based on the modification map; and applying, by the modification logic unit, the modification to the data object in a memory device of the compute sled.
Example 15 includes the subject matter of Example 14, and wherein sending the request comprises sending data indicative of a function to be executed by the accelerator device on the data object.
Example 16 includes the subject matter of any of Examples 14 and 15, and wherein sending the data indicative of a function to be executed comprises sending a bit stream that defines the function to be executed.
Example 17 includes the subject matter of any of Examples 14-16, and wherein sending the data indicative of a function to be executed comprises sending an identifier of a bit stream to be used to configure the accelerator device to execute the function.
Example 18 includes the subject matter of any of Examples 14-17, and wherein sending the data indicative of a function to be executed comprises sending data indicative of one or more of an encryption function, a data compression function, a domain transformation function, or a data reformatting function.
Example 19 includes the subject matter of any of Examples 14-18, and wherein receiving a modification map comprises receiving a bit map indicative of portions of the data object that have been modified.
Example 20 includes the subject matter of any of Examples 14-19, and wherein receiving the bit map comprises receiving a bit map that is further indicative of a type of modification made to each modified portion of the data object.
Example 21 includes the subject matter of any of Examples 14-20, and further including determining, by the modification logic unit, a size of each portion as a function of the size of the data object.
Example 22 includes the subject matter of any of Examples 14-21, and wherein applying the modification comprises overwriting a portion of the data object with modified data provided by the accelerator sled.
Example 23 includes the subject matter of any of Examples 14-22, and wherein applying the modification comprises inserting, in a portion of the data object, data provided by the accelerator sled.
Example 24 includes the subject matter of any of Examples 14-23, and wherein applying the modification comprises deleting a portion of the data object.
Example 25 includes the subject matter of any of Examples 14-24, and further including writing the modification map to the non-volatile memory.
Example 26 includes the subject matter of any of Examples 14-25, and wherein determining the modification to the data object comprises correlating an index of a modified portion represented in the modification map to a portion of the data object.
Example 27 includes a compute sled comprising means for performing the method of any of Examples 14-26.
Example 28 includes one or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a compute sled to perform the method of any of Examples 14-26.
Example 29 includes a compute sled comprising a memory device; a network interface controller coupled to the memory device, wherein the network interface controller includes modification manager circuitry to send a request to utilize an accelerator device on an accelerator sled, wherein the request includes a data object to be processed by the accelerator device to increase the speed of execution of a workload associated with the data object; receive a modification map from the accelerator sled, wherein the modification map is indicative of a modification to the data object; determine the modification to the data object based on the modification map; and apply the modification to the data object in the memory device.
Example 30 includes the subject matter of Example 29, and wherein to send the request comprises to send data indicative of a function to be executed by the accelerator device on the data object.
Example 31 includes the subject matter of any of Examples 29 and 30, and wherein to send the data indicative of a function to be executed comprises to send a bit stream that defines the function to be executed.
Example 32 includes the subject matter of any of Examples 29-31, and wherein to send the data indicative of a function to be executed comprises to send an identifier of a bit stream to be used to configure the accelerator device to execute the function.
Example 33 includes the subject matter of any of Examples 29-32, and wherein to send the data indicative of a function to be executed comprises to send data indicative of one or more of an encryption function, a data compression function, a domain transformation function, or a data reformatting function.
Example 34 includes the subject matter of any of Examples 29-33, and wherein to receive a modification map comprises to receive a bit map indicative of portions of the data object that have been modified.
Example 35 includes the subject matter of any of Examples 29-34, and wherein to receive the bit map comprises to receive a bit map that is further indicative of a type of modification made to each modified portion of the data object.
Example 36 includes the subject matter of any of Examples 29-35, and wherein the modification manager circuitry is further to determine a size of each portion as a function of the size of the data object.
Example 37 includes the subject matter of any of Examples 29-36, and wherein to apply the modification comprises to overwrite a portion of the data object with modified data provided by the accelerator sled.
Example 38 includes the subject matter of any of Examples 29-37, and wherein to apply the modification comprises to insert, in a portion of the data object, data provided by the accelerator sled.
Example 39 includes the subject matter of any of Examples 29-38, and wherein to apply the modification comprises to delete a portion of the data object.
Example 40 includes the subject matter of any of Examples 29-39, and wherein the compute sled further comprises non-volatile memory and the modification manager circuitry is further to write the modification map to the non-volatile memory.
Example 41 includes the subject matter of any of Examples 29-40, and wherein to determine the modification to the data object comprises to correlate an index of a modified portion represented in the modification map to a portion of the data object.
Example 42 includes a compute sled comprising circuitry for sending, with a network interface controller of a compute sled, a request to utilize an accelerator device on an accelerator sled, wherein the request includes a data object to be processed by the accelerator device to increase the speed of execution of a workload associated with the data object; circuitry for receiving a modification map from the accelerator sled, wherein the modification map is indicative of a modification to the data object; means for determining the modification to the data object based on the modification map; and means for applying the modification to the data object in a memory device of the compute sled.
Example 43 includes the subject matter of Example 42, and wherein the circuitry for sending the request comprises circuitry for sending data indicative of a function to be executed by the accelerator device on the data object.
Example 44 includes the subject matter of any of Examples 42 and 43, and wherein the circuitry for sending the data indicative of a function to be executed comprises circuitry for sending a bit stream that defines the function to be executed.
Example 45 includes the subject matter of any of Examples 42-44, and wherein the circuitry for sending the data indicative of a function to be executed comprises circuitry for sending an identifier of a bit stream to be used to configure the accelerator device to execute the function.
Example 46 includes the subject matter of any of Examples 42-45, and wherein the circuitry for sending the data indicative of a function to be executed comprises circuitry for sending data indicative of one or more of an encryption function, a data compression function, a domain transformation function, or a data reformatting function.
Example 47 includes the subject matter of any of Examples 42-46, and wherein the circuitry for receiving a modification map comprises circuitry for receiving a bit map indicative of portions of the data object that have been modified.
Example 48 includes the subject matter of any of Examples 42-47, and wherein the circuitry for receiving the bit map comprises circuitry for receiving a bit map that is further indicative of a type of modification made to each modified portion of the data object.
Example 49 includes the subject matter of any of Examples 42-48, and further including circuitry for determining a size of each portion as a function of the size of the data object.
Example 50 includes the subject matter of any of Examples 42-49, and wherein the means for applying the modification comprises circuitry for overwriting a portion of the data object with modified data provided by the accelerator sled.
Example 51 includes the subject matter of any of Examples 42-50, and wherein the means for applying the modification comprises circuitry for inserting, in a portion of the data object, data provided by the accelerator sled.
Example 52 includes the subject matter of any of Examples 42-51, and wherein the means for applying the modification comprises circuitry for deleting a portion of the data object.
Example 53 includes the subject matter of any of Examples 42-52, and further including circuitry for writing the modification map to the non-volatile memory.
Example 54 includes the subject matter of any of Examples 42-53, and wherein the means for determining the modification to the data object comprises circuitry for correlating an index of a modified portion represented in the modification map to a portion of the data object.
Example 55 includes an accelerator sled comprising an accelerator device; and a modification tracker logic unit to receive a request from a compute sled, wherein the request includes a data object; process, with the accelerator device, the data object with a function to increase the speed of execution of a workload associated with the data object; track a modification to the data object made from the execution of the function; and send, to the compute sled, a modification map indicative of a portion of the data object that was modified, wherein the modification map is usable by the compute sled to reconstruct the modified data object.
Example 56 includes the subject matter of Example 55, and wherein to receive the request comprises to receive data indicative of the function to process the data object.
Example 57 includes the subject matter of any of Examples 55 and 56, and wherein to process the data object comprises to configure the accelerator device with a bit stream that defines the function to process the data object.
Example 58 includes the subject matter of any of Examples 55-57, and wherein to configure the accelerator device comprises to obtain the bit stream from a remote compute device.
Example 59 includes the subject matter of any of Examples 55-58, and wherein the accelerator sled further comprises a memory, and wherein to track a modification to the data object comprises to intercept a write operation to the memory.
Example 60 includes the subject matter of any of Examples 55-59, and wherein the accelerator sled further comprises a memory, and wherein to track the modification to the data object comprises to correlate a location of a write operation to a portion of the modification map.
Example 61 includes the subject matter of any of Examples 55-60, and wherein to track the modification comprises to indicate the modification in a corresponding portion of the modification map.
Example 62 includes the subject matter of any of Examples 55-61, and wherein to indicate the modification comprises to indicate an overwrite of data.
Example 63 includes the subject matter of any of Examples 55-62, and wherein to indicate the modification comprises to indicate an insertion of data.
Example 64 includes the subject matter of any of Examples 55-63, and wherein to indicate the modification comprises to indicate a deletion of data.
Example 65 includes the subject matter of any of Examples 55-64, and wherein the modification tracker logic unit is further to format the modification map as a bit map.
Example 66 includes the subject matter of any of Examples 55-65, and wherein the accelerator device comprises a field-programmable gate array (FPGA) and the modification tracker logic unit is incorporated into the FPGA.
Example 67 includes a method comprising receiving, by a modification tracker logic unit of an accelerator sled, a request from a compute sled, wherein the request includes a data object; processing, with an accelerator device of the accelerator sled, the data object with a function to increase the speed of execution of a workload associated with the data object; tracking, with the modification tracker logic unit, a modification to the data object made from the execution of the function; and sending, by the accelerator sled, a modification map indicative of a portion of the data object that was modified, wherein the modification map is usable by the compute sled to reconstruct the modified data object.
Example 68 includes the subject matter of Example 67, and wherein receiving the request comprises receiving data indicative of the function to process the data object.
Example 69 includes the subject matter of any of Examples 67 and 68, and wherein processing the data object comprises configuring the accelerator device with a bit stream that defines the function to process the data object.
Example 70 includes the subject matter of any of Examples 67-69, and wherein configuring the accelerator device comprises obtaining the bit stream from a remote compute device.
Example 71 includes the subject matter of any of Examples 67-70, and wherein tracking a modification to the data object comprises intercepting a write operation to a memory of the accelerator sled.
Example 72 includes the subject matter of any of Examples 67-71, and wherein tracking the modification to the data object comprises correlating a location of a write operation to a portion of the modification map.
Example 73 includes the subject matter of any of Examples 67-72, and wherein tracking the modification comprises indicating the modification in a corresponding portion of the modification map.
Example 74 includes the subject matter of any of Examples 67-73, and wherein indicating the modification comprises indicating an overwrite of data.
Example 75 includes the subject matter of any of Examples 67-74, and wherein indicating the modification comprises indicating an insertion of data.
Example 76 includes the subject matter of any of Examples 67-75, and wherein indicating the modification comprises indicating a deletion of data.
Example 77 includes the subject matter of any of Examples 67-76, and further including formatting, by the accelerator sled, the modification map as a bit map.
Example 78 includes an accelerator sled comprising means for performing the method of any of Examples 67-77.
Example 79 includes one or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause an accelerator sled to perform the method of any of Examples 67-77.
Example 80 includes an accelerator sled comprising an accelerator device; and a object manager circuitry to receive a request from a compute sled, wherein the request includes a data object; process, with the accelerator device, the data object with a function to increase the speed of execution of a workload associated with the data object; track a modification to the data object made from the execution of the function; and send, to the compute sled, a modification map indicative of a portion of the data object that was modified, wherein the modification map is usable by the compute sled to reconstruct the modified data object.
Example 81 includes the subject matter of Example 80, and wherein to receive the request comprises to receive data indicative of the function to process the data object.
Example 82 includes the subject matter of any of Examples 80 and 81, and wherein to process the data object comprises to configure the accelerator device with a bit stream that defines the function to process the data object.
Example 83 includes the subject matter of any of Examples 80-82, and wherein to configure the accelerator device comprises to obtain the bit stream from a remote compute device.
Example 84 includes the subject matter of any of Examples 80-83, and wherein the accelerator sled further comprises a memory, and wherein to track a modification to the data object comprises to intercept a write operation to the memory.
Example 85 includes the subject matter of any of Examples 80-84, and wherein the accelerator sled further comprises a memory, and wherein to track the modification to the data object comprises to correlate a location of a write operation to a portion of the modification map.
Example 86 includes the subject matter of any of Examples 80-85, and wherein to track the modification comprises to indicate the modification in a corresponding portion of the modification map.
Example 87 includes the subject matter of any of Examples 80-86, and wherein to indicate the modification comprises to indicate an overwrite of data.
Example 88 includes the subject matter of any of Examples 80-87, and wherein to indicate the modification comprises to indicate an insertion of data.
Example 89 includes the subject matter of any of Examples 80-88, and wherein to indicate the modification comprises to indicate a deletion of data.
Example 90 includes the subject matter of any of Examples 80-89, and wherein the object manager circuitry is further to format the modification map as a bit map.
Example 91 includes the subject matter of any of Examples 80-90, and wherein the accelerator device comprises a field-programmable gate array (FPGA) and the object manager circuitry is incorporated into the FPGA.
Example 92 includes an accelerator sled comprising circuitry receiving a request from a compute sled, wherein the request includes a data object; circuitry for processing, with an accelerator device of the accelerator sled, the data object with a function to increase the speed of execution of a workload associated with the data object; means for tracking a modification to the data object made from the execution of the function; and circuitry for sending a modification map indicative of a portion of the data object that was modified, wherein the modification map is usable by the compute sled to reconstruct the modified data object.
Example 93 includes the subject matter of Example 92, and wherein the circuitry for receiving the request comprises circuitry for receiving data indicative of the function to process the data object.
Example 94 includes the subject matter of any of Examples 92 and 93, and wherein the circuitry for processing the data object comprises circuitry for configuring the accelerator device with a bit stream that defines the function to process the data object.
Example 95 includes the subject matter of any of Examples 92-94, and wherein the circuitry for configuring the accelerator device comprises circuitry for obtaining the bit stream from a remote compute device.
Example 96 includes the subject matter of any of Examples 92-95, and wherein the means for tracking a modification to the data object comprises circuitry for intercepting a write operation to a memory of the accelerator sled.
Example 97 includes the subject matter of any of Examples 92-96, and wherein the means for tracking the modification to the data object comprises circuitry for correlating a location of a write operation to a portion of the modification map.
Example 98 includes the subject matter of any of Examples 92-97, and wherein the means for tracking the modification comprises circuitry for indicating the modification in a corresponding portion of the modification map.
Example 99 includes the subject matter of any of Examples 92-98, and wherein the circuitry for indicating the modification comprises circuitry for indicating an overwrite of data.
Example 100 includes the subject matter of any of Examples 92-99, and wherein the circuitry for indicating the modification comprises circuitry for indicating an insertion of data.
Example 101 includes the subject matter of any of Examples 92-100, and wherein the circuitry for indicating the modification comprises circuitry for indicating a deletion of data.
Example 102 includes the subject matter of any of Examples 92-101, and further including circuitry for formatting the modification map as a bit map.

Claims

1. A compute sled comprising:

a memory device;

a network interface controller coupled to the memory device, wherein the network interface controller includes a modification logic unit to:

send a request to utilize an accelerator device on an accelerator sled, wherein the request includes a data object to be processed by the accelerator device to increase the speed of execution of a workload associated with the data object;

receive a modification map from the accelerator sled, wherein the modification map is indicative of a modification to the data object;

determine the modification to the data object based on the modification map; and

apply the modification to the data object in the memory device.

2. The compute sled of claim 1, wherein to send the request comprises to send data indicative of a function to be executed by the accelerator device on the data object.

3. The compute sled of claim 2, wherein to send the data indicative of a function to be executed comprises to send a bit stream that defines the function to be executed.

4. The compute sled of claim 2, wherein to send the data indicative of a function to be executed comprises to send an identifier of a bit stream to be used to configure the accelerator device to execute the function.

5. The compute sled of claim 2, wherein to send the data indicative of a function to be executed comprises to send data indicative of one or more of an encryption function, a data compression function, a domain transformation function, or a data reformatting function.

6. The compute sled of claim 1, wherein to receive a modification map comprises to receive a bit map indicative of portions of the data object that have been modified.

7. The compute sled of claim 6, wherein to receive the bit map comprises to receive a bit map that is further indicative of a type of modification made to each modified portion of the data object.

8. The compute sled of claim 6, wherein the modification logic unit is further to determine a size of each portion as a function of the size of the data object.

9. The compute sled of claim 1, wherein to apply the modification comprises to overwrite a portion of the data object with modified data provided by the accelerator sled.

10. The compute sled of claim 1, wherein to apply the modification comprises to insert, in a portion of the data object, data provided by the accelerator sled.

11. The compute sled of claim 1, wherein to apply the modification comprises to delete a portion of the data object.

12. The compute sled of claim 1, wherein the compute sled further comprises non-volatile memory and the modification logic unit is further to write the modification map to the non-volatile memory.

13. One or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a compute sled to:

send, with a modification logic unit of a network interface controller of the compute sled, a request to utilize an accelerator device on an accelerator sled, wherein the request includes a data object to be processed by the accelerator device to increase the speed of execution of a workload associated with the data object;

receive, with the modification logic unit, a modification map from the accelerator sled, wherein the modification map is indicative of a modification to the data object;

determine, with the modification logic unit, the modification to the data object based on the modification map; and

apply, with the modification logic unit, the modification to the data object in a memory device of the compute sled.

14. The one or more machine-readable storage media of claim 13, wherein to send the request comprises to send data indicative of a function to be executed by the accelerator device on the data object.

15. The one or more machine-readable storage media of claim 14, wherein to send the data indicative of a function to be executed comprises to send a bit stream that defines the function to be executed.

16. The one or more machine-readable storage media of claim 14, wherein to send the data indicative of a function to be executed comprises to send an identifier of a bit stream to be used to configure the accelerator device to execute the function.

17. The one or more machine-readable storage media of claim 14, wherein to send the data indicative of a function to be executed comprises to send data indicative of one or more of an encryption function, a data compression function, a domain transformation function, or a data reformatting function.

18. The one or more machine-readable storage media of claim 13, wherein to receive a modification map comprises to receive a bit map indicative of portions of the data object that have been modified.

19. The one or more machine-readable storage media of claim 18, wherein to receive the bit map comprises to receive a bit map that is further indicative of a type of modification made to each modified portion of the data object.

20. The one or more machine-readable storage media of claim 18, wherein the plurality of instructions further cause the compute sled to determine, with the modification logic unit, a size of each portion as a function of the size of the data object.

21. The one or more machine-readable storage media of claim 13, wherein to apply the modification comprises to overwrite a portion of the data object with modified data provided by the accelerator sled.

22. The one or more machine-readable storage media of claim 13, wherein to apply the modification comprises to insert, in a portion of the data object, data provided by the accelerator sled.

23. The one or more machine-readable storage media of claim 13, wherein to apply the modification comprises to delete a portion of the data object.

24. The one or more machine-readable storage media of claim 13, wherein the plurality of instructions further cause the compute sled to write the modification map to the non-volatile memory.

25. A compute sled comprising:

a memory device;

a network interface controller coupled to the memory device, wherein the network interface controller includes modification manager circuitry to:

apply the modification to the data object in the memory device.

26. A method comprising:

sending, by a modification logic unit of a network interface controller of a compute sled, a request to utilize an accelerator device on an accelerator sled, wherein the request includes a data object to be processed by the accelerator device to increase the speed of execution of a workload associated with the data object;

receiving, by the modification logic unit, a modification map from the accelerator sled, wherein the modification map is indicative of a modification to the data object;

determining, by the modification logic unit, the modification to the data object based on the modification map; and

applying, by the modification logic unit, the modification to the data object in a memory device of the compute sled.

27. The method of claim 26, wherein sending the request comprises sending data indicative of a function to be executed by the accelerator device on the data object.

28. The method of claim 27, wherein sending the data indicative of a function to be executed comprises sending a bit stream that defines the function to be executed.