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US6391725B1 - Semiconductor device and method for fabricating the same - Google Patents

Semiconductor device and method for fabricating the same Download PDF

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Publication number
US6391725B1
US6391725B1 US09/390,713 US39071399A US6391725B1 US 6391725 B1 US6391725 B1 US 6391725B1 US 39071399 A US39071399 A US 39071399A US 6391725 B1 US6391725 B1 US 6391725B1
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Prior art keywords
gate electrode
semiconductor device
insulating layer
recess
doped impurity
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US09/390,713
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Min Wha Park
Hae Chang Yang
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SK Hynix Inc
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LG Semicon Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts

Definitions

  • the present invention relates to a semiconductor device and, more particularly, to a semiconductor device which is applied to access transistors of an SRAM cell to improve its operation performance and a method for fabricating the same.
  • FIG. 2 is a plan view of a conventional semiconductor device and FIG. 3 is a cross-sectional view showing a structure of a conventional semiconductor device.
  • a field region and an active region are defined in a semiconductor substrate 1 and a field oxide layer 2 is formed on the field region.
  • a gate electrode 4 having a gate oxide layer 3 is formed on the active region.
  • a sidewall spacer 7 having a predetermined thickness is formed on both sides of the gate electrode 4 .
  • Lightly doped impurity regions 6 are formed beneath surface of the semiconductor substrate 1 both sides of the gate electrode 4 .
  • Source and drain regions 8 are formed beneath the surface of the semiconductor substrate 1 , but not under the gate electrode 4 and the sidewall spacer 7 .
  • first and second access transistors TA 1 and TA 2 are turned on. Subsequently, 5V is applied to a bitline and another 5V is applied to a bit bar line. Accordingly, data “1” and “0” are written in the first cell node CN 1 and the second cell node CN 2 , respectively. Thus, a second drive transistor TD 2 is turned on and a first drive transistor TD 1 off.
  • the conventional, aforementioned semiconductor device has problems.
  • a conventional semiconductor device is applied to access transistors of an SRAM cell, on reading data “0” stored in a cell node, the current driving power of access transistors is increased and thus current flows to a second drive transistor to read data “0”. As a result, the total current driving ratio is declined so that data “0” can not be exactly read, whereby the performance of the SRAM cell becomes inferior.
  • the present invention is directed to a semiconductor device and a method for fabricating the same that substantially obviate one or more of problems due to limitations and disadvantages of the related art.
  • a semiconductor device includes a gate insulating layer formed on a semiconductor substrate, a gate electrode formed on the gate insulating layer, lightly doped impurity regions having different lengths beneath surface of the semiconductor substrate at first and second sides of the gate electrode, and heavily doped impurity regions formed beneath the surface of the semiconductor substrate, extending from the lightly doped impurity regions.
  • a method for fabricating a semiconductor device includes the steps of providing a semiconductor substrate where an active region is defined, forming a gate electrode having a recess on a predetermined area of the active region to have a gate insulating layer between the gate electrode and the semiconductor substrate, forming lightly doped impurity regions in the active region at both sides of the gate electrode with the gate electrode serving as a mask, forming a sidewall spacer on both sides of the gate electrode, and forming heavily doped impurity regions in the active region with the sidewall spacer serving as a mask.
  • FIG. 1 is a circuit diagram of a general SRAM cell
  • FIG. 2 is a plan view of a conventional semiconductor device
  • FIG. 3 is a cross-sectional view showing a structure of the semiconductor device, taken along line I—I of FIG. 2;
  • FIG. 4 is a plan view of a semiconductor device according to the present invention.
  • FIG. 5 is a cross-sectional view showing a structure of the semiconductor device, taken along line II—II of FIG. 4;
  • FIGS. 6A to 6 D are cross-sectional views showing process steps of a semiconductor device according to a preferred embodiment of the present invention.
  • FIG. 7 is a cross-sectional view showing a structure of the semiconductor device, taken along line III—III of FIG. 4 .
  • FIG. 4 is a plan view of a semiconductor device
  • FIG. 5 is a cross-sectional view of the semiconductor device, taken along line II—II of FIG. 4
  • FIG. 7 is a cross-sectional view of the semiconductor device, taken along line III—III of FIG. 4 .
  • an active region and a field region are defined in a semiconductor substrate 21 , and a field oxide layer 22 is formed on the field region.
  • a gate electrode 24 having a gate oxide layer 23 is formed on the active region.
  • the gate electrode 24 has a recess therein.
  • Sidewall spacers 26 are formed to have different widths in asymmetry, filled the recess of the gate electrode 24 .
  • Lightly doped impurity regions 27 having different length beneath the sidewall spacers 26 are formed at both sides of the gate electrode 24 .
  • Source and drain regions 28 are formed on the active region at sides of the sidewall spacers 26 .
  • the width of the recess is less than half of the width of the sidewall spacers 26 and an identical height with the gate electrode 24 .
  • the gate oxide layer 23 is exposed at the bottom of the recess.
  • FIGS. 6A to 6 D are cross-sectional views showing process steps of the method.
  • an active region and a field region are defined in a semiconductor substrate 21 , and a field oxide layer 22 is formed on the field region by a local oxidation process.
  • a first oxide layer, a polysilicon layer, and an insulating layer are successively formed on the entire surface of the semiconductor substrate 21 and then anisotropically etched by a photo etching process by using a mask for gate electrode formation, thereby forming a gate oxide layer 23 , a gate electrode 24 , and a gate cap insulating layer 25 .
  • the gate electrode 24 has a recess therein.
  • the recess has a height of as high as the gate electrode 24 . Also there remains none of the gate oxide layer 23 at the bottom of the recess.
  • lightly doped impurity ions of an n-type are implanted to the substrate 21 at both sides of the gate electrode 24 so as to form lightly doped impurity regions 27 .
  • a second oxide layer is deposited on the semiconductor substrate 21 and then anisotropically etched to form a sidewall spacer 26 on both sides of the gate electrode 24 .
  • the second oxide layer is formed to be higher than half the height of the recess.
  • the second oxide layer fills the recess of the gate electrode 24 and the sidewall spacer 26 formed at the recess is longer than that formed at the other side of the gate electrode 24 .
  • the lightly doped impurity region 27 formed at the recess is longer than that at the other side of the gate electrode 24 .
  • n-type heavily doped impurity ions are implanted to form source and drain regions 28 beneath the surface of the semiconductor substrate 21 at sides of the sidewall spacer 26 .
  • FIG. 1 The operation of the semiconductor device which is applied to access transistors of an SRAM cell will be described in FIG. 1 .
  • 5V is applied to the word line to turn on the first and second access transistors TA 1 and TA 2 .
  • 5V is applied to each of the bitline and the bit bar line. Accordingly, there is no current flow along the first access transistor TA 1 between the bit line and the first cell node CN 1 .
  • the semiconductor device and the fabricating method thereof have the following advantages.
  • the semiconductor device of the present invention is applied to access transistors of an SRAM cell, on reading data “0”, current driving rate of the access transistors is declined by a lightly doped impurity region having a long cell node and thus current can be prevented from abruptly flowing to the drive transistor of an SRAM cell. Accordingly, the SRAM cell has low voltage so that it has better performance for read operation.

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  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor device which is applied to access transistors of an SRAM cell to improve its operation performance and a method for fabricating the same are disclosed. The semiconductor device includes a gate insulating layer formed on a semiconductor substrate, a gate electrode formed on the gate insulating layer, lightly doped impurity regions having different lengths beneath surface of the semiconductor substrate at first and second sides of the gate electrode, and heavily doped impurity regions formed beneath the surface of the semiconductor substrate, extending from the lightly doped impurity regions.

Description

This application is a divisional of application Ser. No. 08/951,511, filed on Oct. 16, 1997, now U.S. Pat. No. 5,973,362 the entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device which is applied to access transistors of an SRAM cell to improve its operation performance and a method for fabricating the same.
2. Discussion of the Related Art
A conventional semiconductor device will be described with reference to the attached drawings. FIG. 2 is a plan view of a conventional semiconductor device and FIG. 3 is a cross-sectional view showing a structure of a conventional semiconductor device.
As shown in FIGS. 2 and 3, a field region and an active region are defined in a semiconductor substrate 1 and a field oxide layer 2 is formed on the field region. A gate electrode 4 having a gate oxide layer 3 is formed on the active region. A sidewall spacer 7 having a predetermined thickness is formed on both sides of the gate electrode 4. Lightly doped impurity regions 6 are formed beneath surface of the semiconductor substrate 1 both sides of the gate electrode 4. Source and drain regions 8 are formed beneath the surface of the semiconductor substrate 1, but not under the gate electrode 4 and the sidewall spacer 7.
When a semiconductor device having the foregoing structure is applied to access transistors of an SRAM cell, the operation will be described in detail with reference to FIG. 1.
The operation of writing a data “1” in a first cell node CN1 will be described. When 5V is applied to a word line, first and second access transistors TA1 and TA2 are turned on. Subsequently, 5V is applied to a bitline and another 5V is applied to a bit bar line. Accordingly, data “1” and “0” are written in the first cell node CN1 and the second cell node CN2, respectively. Thus, a second drive transistor TD2 is turned on and a first drive transistor TD1 off.
The operation of reading a data “0” in the SRAM cell will be described. First of all, 5V is applied to each of the bitline and the bit bar line. At this time, there is no current flow along the first access transistor TA1 between the bitline and the first cell node CN1 in which data “1” has been written. In contrast, current flows from the bit bar line to the second cell node CN2 along the second access transistor TA2 due to voltage difference between the bit bar line and the second cell node CN2 in which data “0” has been written. At this time, the current flowing along the second access transistor TA2 flows along the second drive transistor abruptly so that the low data written in the second cell node CN2 comes to being read.
However, the conventional, aforementioned semiconductor device has problems. When a conventional semiconductor device is applied to access transistors of an SRAM cell, on reading data “0” stored in a cell node, the current driving power of access transistors is increased and thus current flows to a second drive transistor to read data “0”. As a result, the total current driving ratio is declined so that data “0” can not be exactly read, whereby the performance of the SRAM cell becomes inferior.
SUMMERY OF THE INVENTION
Therefore, the present invention is directed to a semiconductor device and a method for fabricating the same that substantially obviate one or more of problems due to limitations and disadvantages of the related art.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a semiconductor device includes a gate insulating layer formed on a semiconductor substrate, a gate electrode formed on the gate insulating layer, lightly doped impurity regions having different lengths beneath surface of the semiconductor substrate at first and second sides of the gate electrode, and heavily doped impurity regions formed beneath the surface of the semiconductor substrate, extending from the lightly doped impurity regions.
In another aspect of the invention, a method for fabricating a semiconductor device includes the steps of providing a semiconductor substrate where an active region is defined, forming a gate electrode having a recess on a predetermined area of the active region to have a gate insulating layer between the gate electrode and the semiconductor substrate, forming lightly doped impurity regions in the active region at both sides of the gate electrode with the gate electrode serving as a mask, forming a sidewall spacer on both sides of the gate electrode, and forming heavily doped impurity regions in the active region with the sidewall spacer serving as a mask.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
These and various other objects, features, and advantages of the present invention will be readily understood with reference to the following detailed description read in conjunction with the accompanying drawings, in which:
FIG. 1 is a circuit diagram of a general SRAM cell;
FIG. 2 is a plan view of a conventional semiconductor device;
FIG. 3 is a cross-sectional view showing a structure of the semiconductor device, taken along line I—I of FIG. 2;
FIG. 4 is a plan view of a semiconductor device according to the present invention;
FIG. 5 is a cross-sectional view showing a structure of the semiconductor device, taken along line II—II of FIG. 4;
FIGS. 6A to 6D are cross-sectional views showing process steps of a semiconductor device according to a preferred embodiment of the present invention; and
FIG. 7 is a cross-sectional view showing a structure of the semiconductor device, taken along line III—III of FIG. 4.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.
FIG. 4 is a plan view of a semiconductor device, FIG. 5 is a cross-sectional view of the semiconductor device, taken along line II—II of FIG. 4, and FIG. 7 is a cross-sectional view of the semiconductor device, taken along line III—III of FIG. 4.
As shown in FIGS. 4, 5, and 7, an active region and a field region are defined in a semiconductor substrate 21, and a field oxide layer 22 is formed on the field region. A gate electrode 24 having a gate oxide layer 23 is formed on the active region. The gate electrode 24 has a recess therein. Sidewall spacers 26 are formed to have different widths in asymmetry, filled the recess of the gate electrode 24. Lightly doped impurity regions 27 having different length beneath the sidewall spacers 26 are formed at both sides of the gate electrode 24. Source and drain regions 28 are formed on the active region at sides of the sidewall spacers 26. The width of the recess is less than half of the width of the sidewall spacers 26 and an identical height with the gate electrode 24. The gate oxide layer 23 is exposed at the bottom of the recess.
A method for fabricating the foregoing semiconductor device will be described in detail. FIGS. 6A to 6D are cross-sectional views showing process steps of the method.
Referring initially to FIG. 6A, an active region and a field region are defined in a semiconductor substrate 21, and a field oxide layer 22 is formed on the field region by a local oxidation process.
Referring to FIG. 6B, a first oxide layer, a polysilicon layer, and an insulating layer are successively formed on the entire surface of the semiconductor substrate 21 and then anisotropically etched by a photo etching process by using a mask for gate electrode formation, thereby forming a gate oxide layer 23, a gate electrode 24, and a gate cap insulating layer 25. At this time, the gate electrode 24 has a recess therein. The recess has a height of as high as the gate electrode 24. Also there remains none of the gate oxide layer 23 at the bottom of the recess.
Referring to FIG. 6C, with the gate electrode 24 serving as a mask, lightly doped impurity ions of an n-type are implanted to the substrate 21 at both sides of the gate electrode 24 so as to form lightly doped impurity regions 27. Next, a second oxide layer is deposited on the semiconductor substrate 21 and then anisotropically etched to form a sidewall spacer 26 on both sides of the gate electrode 24. At this time, the second oxide layer is formed to be higher than half the height of the recess. The second oxide layer fills the recess of the gate electrode 24 and the sidewall spacer 26 formed at the recess is longer than that formed at the other side of the gate electrode 24. Thus, the lightly doped impurity region 27 formed at the recess is longer than that at the other side of the gate electrode 24.
Referring to FIG. 6D, with the gate electrode 24 and the sidewall spacers 26. Serving as masks, n-type heavily doped impurity ions are implanted to form source and drain regions 28 beneath the surface of the semiconductor substrate 21 at sides of the sidewall spacer 26.
The operation of the semiconductor device which is applied to access transistors of an SRAM cell will be described in FIG. 1.
First, the operation of writing data “1” in a first node cell CN1 will be described. First, 5V is applied to a word line to turn on first and second access transistors. Another 5V is applied to a bitline and 0V to a bit bar line, so as to turn on the a second drive transistor TD2 and turn off a first drive transistor TD2. Accordingly, data “1” is written in the first cell node CN1 and data “0” is written in the second cell node CN2.
The operation of reading data “0” stored in the second cell node CN2 will be described. First, 5V is applied to the word line to turn on the first and second access transistors TA1 and TA2. 5V is applied to each of the bitline and the bit bar line. Accordingly, there is no current flow along the first access transistor TA1 between the bit line and the first cell node CN1.
In contrast, voltage difference between the bit bar line and the second cell node CN2 due to data “0” stored in the second cell node CN2, and thus current flows from the bit bar line to the second cell node CN2 through the second access transistor TA2. At this time, if the semiconductor device is applied to the second access transistor TA2, the lightly doped impurity region 27 connected to the second cell node CN2 is longer than the lightly doped impurity region 27 at the second access transistor TA2 connected to the bit bar line. The lightly doped impurity regions 27 function as resistors so that current can be prevented from flowing to the second drive transistor abruptly.
The semiconductor device and the fabricating method thereof have the following advantages. When the semiconductor device of the present invention is applied to access transistors of an SRAM cell, on reading data “0”, current driving rate of the access transistors is declined by a lightly doped impurity region having a long cell node and thus current can be prevented from abruptly flowing to the drive transistor of an SRAM cell. Accordingly, the SRAM cell has low voltage so that it has better performance for read operation.
It will be apparent to those skilled in the art that various modification and variations can be made in the semiconductor device and the fabricating method thereof of the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims (5)

What is claimed is:
1. A method for fabricating a semiconductor device comprising the steps of:
providing a semiconductor substrate where an active region is defined;
forming a gate electrode having a recess on a predetermined area of the active region to have a gate insulating layer between the gate electrode and the semiconductor substrate;
forming lightly doped impurity regions in the active region at both sides of the gate electrode with the gate electrode serving as a mask;
forming a sidewall spacer on both sides of the gate electrode; and
forming heavily doped impurity regions in the active region with the sidewall spacer serving as a mask.
2. The method as claimed in claim 1, wherein the recess has a height as high as the gate electrode, and the gate insulating layer is exposed at the bottom of the recess.
3. The method as claimed in claim 1, wherein the step of forming the sidewall spacer includes the steps of forming an insulating layer on the gate electrode and the gate insulating layer, and anisotropically etching the insulating layer to remain on the sides of the gate electrode.
4. The method as claimed in claim 3, wherein the thickness of the insulating layer is higher than half the height of the recess.
5. The method as claimed in claim 3, wherein after being anisotropically etched, the recess is completely buried by the sidewall spacer.
US09/390,713 1997-04-21 1999-09-07 Semiconductor device and method for fabricating the same Expired - Lifetime US6391725B1 (en)

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US7042050B2 (en) 2004-03-19 2006-05-09 Kabushiki Kaisha Toshiba Semiconductor device having MOSFET with offset-spacer, and manufacturing method thereof
WO2009050669A3 (en) * 2007-10-19 2009-06-11 Nxp Bv High voltage semiconductor device
US20100117163A1 (en) * 2008-11-13 2010-05-13 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same

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US6621146B1 (en) * 2001-09-26 2003-09-16 Lsi Logic Corporation Method and apparatus for the use of embedded resistance to linearize and improve the matching properties of transistors
CN100403551C (en) * 2005-03-08 2008-07-16 联华电子股份有限公司 High voltage component structure
JP4826127B2 (en) * 2005-04-25 2011-11-30 ソニー株式会社 Solid-state imaging device and manufacturing method thereof
KR100764737B1 (en) * 2006-02-09 2007-10-08 삼성전자주식회사 SRAM cell and its formation method
JP2008091412A (en) 2006-09-29 2008-04-17 Oki Electric Ind Co Ltd High voltage MOS transistor and manufacturing method thereof
JP5442235B2 (en) * 2008-11-06 2014-03-12 ルネサスエレクトロニクス株式会社 Semiconductor device manufacturing method and semiconductor device
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Publication number Priority date Publication date Assignee Title
US7042050B2 (en) 2004-03-19 2006-05-09 Kabushiki Kaisha Toshiba Semiconductor device having MOSFET with offset-spacer, and manufacturing method thereof
US20060160285A1 (en) * 2004-03-19 2006-07-20 Hideji Tsujii Semiconductor device having MOSFET with offset-spacer, and manufacturing method thereof
US7517745B2 (en) 2004-03-19 2009-04-14 Kabushiki Kaisha Toshiba Semiconductor device having MOSFET with offset-spacer, and manufacturing method thereof
US20090155973A1 (en) * 2004-03-19 2009-06-18 Kabushiki Kaisha Toshiba Semiconductor device having mosfet with offset-spacer, and manufacturing method thereof
US7638399B2 (en) 2004-03-19 2009-12-29 Kabushiki Kaisha Toshiba Semiconductor device having MOSFET with offset-spacer, and manufacturing method thereof
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US20100117163A1 (en) * 2008-11-13 2010-05-13 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same

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KR19980077522A (en) 1998-11-16
US5973362A (en) 1999-10-26

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