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US6764954B2 - Application of alignment marks to wafer - Google Patents

Application of alignment marks to wafer Download PDF

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Publication number
US6764954B2
US6764954B2 US10/333,453 US33345303A US6764954B2 US 6764954 B2 US6764954 B2 US 6764954B2 US 33345303 A US33345303 A US 33345303A US 6764954 B2 US6764954 B2 US 6764954B2
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Prior art keywords
layer
metal
metal layer
semiconductor wafer
area
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Expired - Lifetime
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US10/333,453
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US20030157779A1 (en
Inventor
Wolfgang Diewald
Klaus Mümmler
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Infineon Technologies AG
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Infineon Technologies AG
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Assigned to INFINEON TECHNOLOGIES AG reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DIEWALD, WOLFGANG, MUMMLER, KLAUS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED

Definitions

  • U.S. Pat. No. 6,051,496 discloses the use of a stop layer during the CMP process, said layer being deposited on a dielectric layer having lands and depressions, specifically in particular in the case of a CU damascene.
  • U.S. Pat. No. 6,080,636 discloses a production process for a photolithographic alignment mark by means of a CMP process.
  • U.S. Pat. No. 6,020,263 discloses a method of exposing alignment marks following a CMP process on tungsten metal.
  • alignment marks are generally applied to the semiconductor wafer. These alignment marks are generally a structure comprising bars and lines which, in general, are executed in the kerf region of the semiconductor wafer.
  • the kerf region of the semiconductor wafer represents a region about 50 to 100 ⁇ m wide between the individual chips on the semiconductor wafer which, when the semiconductor wafer is subsequently broken up into the individual chips, is then destroyed.
  • the alignment operation is difficult when an additional, optically non transparent layer is applied, which is needed for example for the production of a capacitor, and therefore the alignment mark structure lying underneath in the semiconductor wafer cannot be registered optically.
  • the application of the alignment marks to the semiconductor wafer in the prior art is then carried out in such a way that, during the etching of the preceding structure into the semiconductor wafer, at the same time the bars and lines are etched into the kerf area, the alignment masks being designed in such a way that during the following process steps, including the deposition of the optically non transparent layer, said alignment marks are no longer completely filled.
  • the topology of the alignment marks on the semiconductor wafer can then be registered by means of optical alignment mark detection methods and can be used to align the exposure device.
  • the trenches etched for the alignment marks also cannot be formed in such a way that these are not filled up completely during the copper deposition, since copper always begins to fill all the trenches from the bottom up, irrespective of their width, during the deposition methods which are normally used, and it is therefore not possible either to produce any voids, that is to say cavities, in the trenches, which then lead to a topology of the alignment marks on an optically non transparent layer that is subsequently deposited.
  • the application of the alignment mask is carried out in the damascene technique, the large-area metal layer being deposited onto a layer consisting of a dielectric and having large-area depressions.
  • the further thin intermediate layer is provided in order to form a nucleus for the metal deposition and as a diffusion barrier.
  • FIG. 1 shows a possible embodiment of the method according to the invention of applying alignment marks in the context of copper metallization with the aid of the damascene method
  • FIG. 1B after a first polishing step
  • FIG. 2 shows an apparatus for chemical-mechanical polishing
  • Integrated circuits are generally produced on the semiconductor wafers with the aid of lithographic methods.
  • each structural level is first produced via a photo mask in a thin radiation-sensitive layer deposited onto the semiconductor wafer, generally an organic resist layer, and then transferred into the semiconductor layer lying underneath in a special etching method.
  • care must be taken that the structures lying one above another and belonging to the integrated circuits are arranged in an accurate position in relation to one another, in order to achieve the highest possible integration density.
  • the exposure device for superimposing the mask structure is aligned exactly with a structure already present on the semiconductor wafer.
  • alignment marks are applied to the semiconductor wafer, preferably in a kerf area 1 which is 50 to 100 ⁇ m wide and which is subsequently used to break up the semiconductor wafers into the individual chips.
  • the alignment marks have to be designed in such a way that they produce a topology in the layer applied to the alignment marks which may then be registered optically.
  • an intermediate layer is then applied, preferably either by means of sputtering on or CVD deposition.
  • This intermediate layer ensures, firstly, reliable separation of the copper from the dielectric and from the semiconductor substrate lying underneath.
  • the material preferably used for the intermediate layer is an tantalum/tantalum nitride double layer.
  • this intermediate layer 5 is also applied in the area of the additional depressions 3 in the dielectric layer 2 , which are implemented in the kerf area 1 of the semiconductor wafer.
  • FIG. 2 shows, schematically, an apparatus for chemical-mechanical polishing, a plan view being illustrated in FIG. 2A and a section along the A line in FIG. 2 B.
  • a polishing table 10 On a rotatably arranged polishing table 10 there is arranged a resilient, perforated pad 11 which contains a polishing agent 12 .
  • the polishing agent 12 is supplied to the pad 11 via a polishing-agent feed 13 .
  • the semiconductor wafer to be processed is pressed onto the pad 11 on the polishing table 10 by a wafer carrier 14 . At the same time, the semiconductor wafer and the polishing table 10 rotate.
  • the copper layer 6 is removed in a first polishing process, being stopped on the intermediate layer 5 consisting of tantalum/tantalum nitride.
  • the copper polishing process is in this case carried out with a polishing agent based on aluminum oxide.
  • Pan W (Freudenberg) is preferably used as polishing table pad.
  • This first copper polishing step on the kerf area 1 is preferably carried out at the same time as the copper layer is polished away over the depressions provided for the conductor tracks.
  • a two-stage polishing process is used, which is suitable in particular for forming alignment marks in a copper metallization plane.
  • the two-stage polishing process presented in which the copper metal layer 6 is polished away first and then the intermediate layer 5 , can, however, also be replaced by a single-stage polishing process in which only copper polishing is carried out.
  • the lands 4 of the dielectric layer 2 then stand out between the metal surfaces, and said layer is then also revealed as a topology on a non transparent layer deposited thereon.
  • copper as metal and an intermediate layer of tantalum/tantalum nitride, however, there is also the possibility of using another metal or another material for the intermediate layer.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
US10/333,453 2000-07-26 2001-07-06 Application of alignment marks to wafer Expired - Lifetime US6764954B2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE10037446 2000-07-26
DE10037446.8 2000-07-26
DE10037446A DE10037446A1 (de) 2000-07-26 2000-07-26 Verfahren zum Aufbringen von Justiermarken auf einer Halbleiterscheibe
PCT/EP2001/007782 WO2002009176A2 (fr) 2000-07-26 2001-07-06 Procede d'application de reperes de reglage sur une plaquette semi-conductrice

Publications (2)

Publication Number Publication Date
US20030157779A1 US20030157779A1 (en) 2003-08-21
US6764954B2 true US6764954B2 (en) 2004-07-20

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US10/333,453 Expired - Lifetime US6764954B2 (en) 2000-07-26 2001-07-06 Application of alignment marks to wafer

Country Status (6)

Country Link
US (1) US6764954B2 (fr)
EP (1) EP1303880B1 (fr)
JP (1) JP3880929B2 (fr)
KR (1) KR100525014B1 (fr)
DE (1) DE10037446A1 (fr)
WO (1) WO2002009176A2 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070099378A1 (en) * 2003-11-18 2007-05-03 Samsung Electronics Co., Ltd. Semiconductor device having align key and method of fabricating the same
US20070102819A1 (en) * 2004-03-25 2007-05-10 Klaus Goller Method for producing an integrated circuit assembly with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement
US20070234539A1 (en) * 2006-04-05 2007-10-11 Samsung Electro-Mechanics Co., Ltd. Method for manufacturing capacitor embedded in PCB
US20110284990A1 (en) * 2010-04-30 2011-11-24 Silterra Malaysia Sdn Bhd Process for making an alignment structure in the fabrication of a semiconductor device
US10534276B1 (en) 2019-03-27 2020-01-14 International Business Machines Corporation Lithographic photomask alignment using non-planar alignment structures formed on wafer

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6713884B2 (en) * 2001-12-20 2004-03-30 Infineon Technologies Ag Method of forming an alignment mark structure using standard process steps for forming vertical gate transistors
US6596640B1 (en) * 2002-06-21 2003-07-22 Intel Corporation Method of forming a raised contact for a substrate
KR101023393B1 (ko) * 2004-08-20 2011-03-18 사천홍시현시기건유한공사 유기전계 발광장치용 밀봉기판 정렬마크 및 그 제조방법
US8466569B2 (en) * 2008-04-01 2013-06-18 Texas Instruments Incorporated Increasing exposure tool alignment signal strength for a ferroelectric capacitor layer
US8324742B2 (en) * 2008-04-01 2012-12-04 Texas Instruments Incorporated Alignment mark for opaque layer

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5786260A (en) 1996-12-16 1998-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a readable alignment mark structure using enhanced chemical mechanical polishing
US5858854A (en) 1996-10-16 1999-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming high contrast alignment marks
US5874778A (en) 1997-06-11 1999-02-23 International Business Machines Corporation Embedded power and ground plane structure
US5904563A (en) 1996-05-20 1999-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method for metal alignment mark generation
US6020263A (en) 1996-10-31 2000-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method of recovering alignment marks after chemical mechanical polishing of tungsten
US6051496A (en) 1998-09-17 2000-04-18 Taiwan Semiconductor Manufacturing Company Use of stop layer for chemical mechanical polishing of CU damascene
WO2000035627A2 (fr) 1998-12-16 2000-06-22 Speedfam-Ipec Corporation Polissage chimique et mecanique a plusieurs etapes
US6080636A (en) 1997-06-09 2000-06-27 Vanguard International Semiconductor Corporation Photolitography alignment mark manufacuturing process in tungsten CMP metallization
JP2000232154A (ja) 1999-02-12 2000-08-22 Sony Corp 半導体装置およびその製造方法
US6486049B2 (en) * 2001-04-30 2002-11-26 Motorola, Inc. Method of fabricating semiconductor devices with contact studs formed without major polishing defects

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5904563A (en) 1996-05-20 1999-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method for metal alignment mark generation
US5858854A (en) 1996-10-16 1999-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming high contrast alignment marks
US6020263A (en) 1996-10-31 2000-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method of recovering alignment marks after chemical mechanical polishing of tungsten
US5786260A (en) 1996-12-16 1998-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a readable alignment mark structure using enhanced chemical mechanical polishing
US6080636A (en) 1997-06-09 2000-06-27 Vanguard International Semiconductor Corporation Photolitography alignment mark manufacuturing process in tungsten CMP metallization
US5874778A (en) 1997-06-11 1999-02-23 International Business Machines Corporation Embedded power and ground plane structure
US6051496A (en) 1998-09-17 2000-04-18 Taiwan Semiconductor Manufacturing Company Use of stop layer for chemical mechanical polishing of CU damascene
WO2000035627A2 (fr) 1998-12-16 2000-06-22 Speedfam-Ipec Corporation Polissage chimique et mecanique a plusieurs etapes
JP2000232154A (ja) 1999-02-12 2000-08-22 Sony Corp 半導体装置およびその製造方法
US6486049B2 (en) * 2001-04-30 2002-11-26 Motorola, Inc. Method of fabricating semiconductor devices with contact studs formed without major polishing defects

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Gotkis, Y. et al., "Cu CMP with orbital technology. Summary of the Experience.", Advanced Semiconductor Manufacturing Conference IEEE/SEMI, pp. 364-371, 1998; XP 010314156.
Moussavi, M. et al., "Comparison of Barrier Materials and Deposition Processes for Copper Integration", Interconnect Technology Conference, IEEE, pp. 295-297, 1998; XP010295546.

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070099378A1 (en) * 2003-11-18 2007-05-03 Samsung Electronics Co., Ltd. Semiconductor device having align key and method of fabricating the same
US7718504B2 (en) * 2003-11-18 2010-05-18 Samsung Electronics Co., Ltd. Semiconductor device having align key and method of fabricating the same
US20070102819A1 (en) * 2004-03-25 2007-05-10 Klaus Goller Method for producing an integrated circuit assembly with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement
US7795105B2 (en) 2004-03-25 2010-09-14 Infineon Technologies Ag Method for producing an integrated circuit assembly with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement
US20070234539A1 (en) * 2006-04-05 2007-10-11 Samsung Electro-Mechanics Co., Ltd. Method for manufacturing capacitor embedded in PCB
US7736397B2 (en) * 2006-04-05 2010-06-15 Samsung Electro-Mechanics Co., Ltd. Method for manufacturing capacitor embedded in PCB
US20110284990A1 (en) * 2010-04-30 2011-11-24 Silterra Malaysia Sdn Bhd Process for making an alignment structure in the fabrication of a semiconductor device
US10534276B1 (en) 2019-03-27 2020-01-14 International Business Machines Corporation Lithographic photomask alignment using non-planar alignment structures formed on wafer

Also Published As

Publication number Publication date
EP1303880A2 (fr) 2003-04-23
DE10037446A1 (de) 2002-02-14
EP1303880B1 (fr) 2012-01-25
KR20030015895A (ko) 2003-02-25
WO2002009176A2 (fr) 2002-01-31
KR100525014B1 (ko) 2005-10-31
JP3880929B2 (ja) 2007-02-14
US20030157779A1 (en) 2003-08-21
JP2004505448A (ja) 2004-02-19
WO2002009176A3 (fr) 2002-05-10

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