US7067360B2 - Method of fabricating a fin field effect transistor - Google Patents
Method of fabricating a fin field effect transistor Download PDFInfo
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- US7067360B2 US7067360B2 US11/024,518 US2451804A US7067360B2 US 7067360 B2 US7067360 B2 US 7067360B2 US 2451804 A US2451804 A US 2451804A US 7067360 B2 US7067360 B2 US 7067360B2
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 230000005669 field effect Effects 0.000 title claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 28
- 150000004767 nitrides Chemical class 0.000 claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 5
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
- 239000002994 raw material Substances 0.000 claims description 3
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 3
- 150000002739 metals Chemical class 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/62—Fin field-effect transistors [FinFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
- H10D30/6739—Conductor-insulator-semiconductor electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
- H10D84/0119—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including complementary BJTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
Definitions
- the present disclosure relates to a method of fabricating a semiconductor device and, more particularly, to a method of fabricating a fin field effect transistor by which an electrically stable fin field effect transistor can be implemented
- FIG. 1 is a cross-sectional diagram of a known fin FET.
- polysilicon is used as a material of a gate 5 and a gate oxide layer 6 is formed of SiO2 as a gate dielectric.
- a threshold voltage of an NMOS or PMOS device due to a work function difference in case of using polysilicon for a bulk transistor varies, thereby degrading a stable operation of the device.
- leakage current is generated due to the SiO2 layer as the gate oxide layer, which may prevent the device from operating stably.
- FIG. 1 is a cross-sectional diagram of a known fin FET.
- FIG. 2 is a diagram depicting an example method of fabricating a fin FET.
- the example methods and apparatus described herein provide a method of fabricating a fin field effect transistor in which metal and high-K dielectric are used as a gate material and a gate dielectric, respectively, and in which a variation of a threshold voltage of a PMOS/NMOS device due to a work function difference is appropriately adjusted, and in which leakage current can be reduced.
- One example method includes forming a thermal oxide layer as a hard mask for etching a silicon fin on an SOI substrate, transcribing a fin pattern, forming a fin FET body by etching using the fin pattern as an etch mask, restoring a sidewall damaged by the etching in a manner of growing to remove a sacrifice silicon oxide layer, depositing a high-K dielectric as a gate dielectric, depositing a metal layer, planarizing the metal layer to a height of an hard oxide mask, forming a nitride layer on the planarized metal layer, patterning the nitride layer using a hard mask for forming a pattern to form a nitride layer pattern, forming a metal gate using the nitride layer pattern, removing a remaining hard oxide mask, and growing a sidewall oxide layer on the metal gate.
- one selected from the group consisting of HfO2, Ta2O5, and ZrO2 is used as a raw material of the high-K dielectric.
- the metal gate is formed of one selected from Ru—Ta, TaN, and Mo based metals.
- a thermal oxide layer is grown on an SOI (silicon on insulator) substrate having a buried oxide layer 10 about 400 nm thick and a P or N-doped device layer about 300 nm thick using a hard mask for silicon fin etching. Additionally, a fin pattern having a thickness of 20 ⁇ 100 nm is transcribed by E-beam lithography.
- SOI silicon on insulator
- a fin FET body is formed on the SiO2/SOI substrate by RIE (reactive ion etch) using the fin pattern as an etch mask. Subsequently, a sacrifice silicon oxide layer is grown about 70 nm thick and is then removed to restore sidewalls damaged by RIE.
- High-K dielectric is deposited 5 ⁇ 10 nm thick as a gate dielectric 60 . In doing so, HfO2, Ta2O5, ZrO2 or the like is used as a raw material of the high-K dielectric.
- a metal layer is deposited about 400 nm thick by physical vapor deposition (PVD) to form a gate.
- a Ru—Ta, TaN (cube and hexagonal), or Mo based metal is used as a gate electrode material.
- the metal layer is then planarized to the height of a hard oxide mask by CMP (chemical mechanical polishing).
- a silicon nitride (Si3N4) layer is deposited as a hard mask for forming a pattern on the metal layer by CVD (chemical vapor deposition). Patterning is then carried out by DUV (deep ultraviolet).
- a metal gate 50 is formed by etch using a pattern formed by the patterning as an etch mask and the remaining hard oxide mask is removed by HF.
- a sidewall oxide is grown about 75 nm thick to prevent shorting of the metal gate and to protect a silicon layer from source/drain ion implantation.
- source/drain ion implantation is carried out on the substrate using As or B as a dopant.
- RTA rapid thermal annealing
- reference numbers 10 , 20 , 30 , 40 , 50 , and 60 indicate buried oxide, Si, pad oxide, Si3N4, Metal gate, and high-K dielectric, respectively.
- metal and high-K dielectric are used as a gate material and a gate dielectric, respectively, whereby a variation of a threshold voltage of a PMOS/NMOS device due to a work function difference is appropriately adjusted. Additionally, the example fabrication method described herein can reduce leakage current and ensures electrical stability of the device operation.
Landscapes
- Thin Film Transistor (AREA)
Abstract
A method of fabricating a fin field effect transistor is disclosed. An example method forms a thermal oxide layer as a hard mask for etching a silicon fin on an SOI substrate, transcribes a fin pattern, forms a fin FET body by etching using the fin pattern as an etch mask, and restores a sidewall damaged by the etching remove a sacrificial silicon oxide layer. The example method also deposits a high-K dielectric as a gate dielectric, deposits a metal layer, planarizes the metal layer to a height of a hard oxide, forms a nitride layer on the planarized metal layer, and patterns the nitride layer using a hard mask for forming a pattern to form a nitride layer pattern. Additionally, the example method forms a metal gate using the nitride layer pattern, removes a remaining hard oxide mask, and grows a sidewall oxide layer on the metal gate.
Description
This application claims the benefit of Korean Application No. P2003-0100533 filed on Dec. 30, 2003, which is hereby incorporated herein by reference in its entirety.
The present disclosure relates to a method of fabricating a semiconductor device and, more particularly, to a method of fabricating a fin field effect transistor by which an electrically stable fin field effect transistor can be implemented
Generally, as a scaling of a bulk transistor reaches its process limit, a fin field effect transistor (hereinafter abbreviated FET) having a single or dual gate becomes more desirable. FIG. 1 is a cross-sectional diagram of a known fin FET. Referring to FIG. 1 , polysilicon is used as a material of a gate 5 and a gate oxide layer 6 is formed of SiO2 as a gate dielectric. However, even if a degree of device integration is raised using the fin FET, a threshold voltage of an NMOS or PMOS device due to a work function difference in case of using polysilicon for a bulk transistor varies, thereby degrading a stable operation of the device. Additionally, leakage current is generated due to the SiO2 layer as the gate oxide layer, which may prevent the device from operating stably.
In general, the example methods and apparatus described herein provide a method of fabricating a fin field effect transistor in which metal and high-K dielectric are used as a gate material and a gate dielectric, respectively, and in which a variation of a threshold voltage of a PMOS/NMOS device due to a work function difference is appropriately adjusted, and in which leakage current can be reduced.
One example method includes forming a thermal oxide layer as a hard mask for etching a silicon fin on an SOI substrate, transcribing a fin pattern, forming a fin FET body by etching using the fin pattern as an etch mask, restoring a sidewall damaged by the etching in a manner of growing to remove a sacrifice silicon oxide layer, depositing a high-K dielectric as a gate dielectric, depositing a metal layer, planarizing the metal layer to a height of an hard oxide mask, forming a nitride layer on the planarized metal layer, patterning the nitride layer using a hard mask for forming a pattern to form a nitride layer pattern, forming a metal gate using the nitride layer pattern, removing a remaining hard oxide mask, and growing a sidewall oxide layer on the metal gate.
Preferably, one selected from the group consisting of HfO2, Ta2O5, and ZrO2 is used as a raw material of the high-K dielectric. Also, preferably, the metal gate is formed of one selected from Ru—Ta, TaN, and Mo based metals.
Now referring to FIG. 2 , a thermal oxide layer is grown on an SOI (silicon on insulator) substrate having a buried oxide layer 10 about 400 nm thick and a P or N-doped device layer about 300 nm thick using a hard mask for silicon fin etching. Additionally, a fin pattern having a thickness of 20˜100 nm is transcribed by E-beam lithography.
After the fin pattern has been transcribed, a fin FET body is formed on the SiO2/SOI substrate by RIE (reactive ion etch) using the fin pattern as an etch mask. Subsequently, a sacrifice silicon oxide layer is grown about 70 nm thick and is then removed to restore sidewalls damaged by RIE. High-K dielectric is deposited 5˜10 nm thick as a gate dielectric 60. In doing so, HfO2, Ta2O5, ZrO2 or the like is used as a raw material of the high-K dielectric. A metal layer is deposited about 400 nm thick by physical vapor deposition (PVD) to form a gate. In doing so, a Ru—Ta, TaN (cube and hexagonal), or Mo based metal is used as a gate electrode material. The metal layer is then planarized to the height of a hard oxide mask by CMP (chemical mechanical polishing). A silicon nitride (Si3N4) layer is deposited as a hard mask for forming a pattern on the metal layer by CVD (chemical vapor deposition). Patterning is then carried out by DUV (deep ultraviolet). After completion of the patterning, a metal gate 50 is formed by etch using a pattern formed by the patterning as an etch mask and the remaining hard oxide mask is removed by HF.
Additionally, a sidewall oxide is grown about 75 nm thick to prevent shorting of the metal gate and to protect a silicon layer from source/drain ion implantation. Subsequently, source/drain ion implantation is carried out on the substrate using As or B as a dopant. Thereafter, RTA (rapid thermal annealing) is the carried out on the substrate. In FIG. 2 , reference numbers 10, 20, 30, 40, 50, and 60 indicate buried oxide, Si, pad oxide, Si3N4, Metal gate, and high-K dielectric, respectively.
Accordingly, with the example fabrication method described herein, metal and high-K dielectric are used as a gate material and a gate dielectric, respectively, whereby a variation of a threshold voltage of a PMOS/NMOS device due to a work function difference is appropriately adjusted. Additionally, the example fabrication method described herein can reduce leakage current and ensures electrical stability of the device operation.
While the examples herein have been described in detail with reference to example embodiments, it is to be understood that the coverage of this patent is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the sprit and scope of the appended claims.
Claims (3)
1. A method of fabricating a fin field effect transistor, comprising:
forming a thermal oxide layer as a hard mask for etching a silicon fin on an SOI substrate;
transcribing a fin pattern;
forming a fin FET body by etching using the fin pattern as an etch mask;
growing a sacrificial silicon oxide layer to restore a sidewall damaged by the etching;
removing the sacrificial silicon oxide layer;
depositing a high-K dielectric as a gate dielectric;
depositing a metal layer;
planarizing the metal layer to a height of a hard oxide;
forming a nitride layer on the planarized metal layer;
patterning the nitride layer using a hard oxide mask for forming a pattern to form a nitride layer pattern;
forming a metal gate using the nitride layer pattern;
removing a remaining hard oxide mask using high frequency; and
growing a sidewall oxide layer on the metal gate.
2. The method of claim 1 , wherein one selected from the group consisting of HfO2, Ta2O5, and ZrO2 is used as a raw material of the high-K dielectric.
3. The method of claim 1 , wherein the metal gate is formed of one selected from Ru—Ta, TaN, and Mo based metals.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030100533A KR100601911B1 (en) | 2003-12-30 | 2003-12-30 | Fin Pet Device Manufacturing Method |
| KR2003-0100533 | 2003-12-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| US20050142738A1 US20050142738A1 (en) | 2005-06-30 |
| US7067360B2 true US7067360B2 (en) | 2006-06-27 |
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ID=34698771
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US11/024,518 Expired - Fee Related US7067360B2 (en) | 2003-12-30 | 2004-12-28 | Method of fabricating a fin field effect transistor |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7067360B2 (en) |
| KR (1) | KR100601911B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070092995A1 (en) * | 2005-10-21 | 2007-04-26 | Arindom Datta | Microelectronics grade metal substrate, related metal-embedded devices and methods for fabricating same |
| US7833891B2 (en) | 2008-07-23 | 2010-11-16 | International Business Machines Corporation | Semiconductor device manufacturing method using oxygen diffusion barrier layer between buried oxide layer and high K dielectric layer |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4421618B2 (en) * | 2007-01-17 | 2010-02-24 | 東京エレクトロン株式会社 | Manufacturing method of fin-type field effect transistor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
| US6794718B2 (en) * | 2002-12-19 | 2004-09-21 | International Business Machines Corporation | High mobility crystalline planes in double-gate CMOS technology |
| US6815268B1 (en) * | 2002-11-22 | 2004-11-09 | Advanced Micro Devices, Inc. | Method for forming a gate in a FinFET device |
-
2003
- 2003-12-30 KR KR1020030100533A patent/KR100601911B1/en not_active Expired - Fee Related
-
2004
- 2004-12-28 US US11/024,518 patent/US7067360B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
| US6815268B1 (en) * | 2002-11-22 | 2004-11-09 | Advanced Micro Devices, Inc. | Method for forming a gate in a FinFET device |
| US6794718B2 (en) * | 2002-12-19 | 2004-09-21 | International Business Machines Corporation | High mobility crystalline planes in double-gate CMOS technology |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070092995A1 (en) * | 2005-10-21 | 2007-04-26 | Arindom Datta | Microelectronics grade metal substrate, related metal-embedded devices and methods for fabricating same |
| US7572665B2 (en) * | 2005-10-21 | 2009-08-11 | Wisconsin Alumni Research Foundation | Microelectronics grade metal substrate, related metal-embedded devices and methods for fabricating same |
| US20090291313A1 (en) * | 2005-10-21 | 2009-11-26 | Wisconsin Alummi Research Foundation | Microelectronics grade metal substrate, related metal-embedded devices and methods for fabricating same |
| US7833891B2 (en) | 2008-07-23 | 2010-11-16 | International Business Machines Corporation | Semiconductor device manufacturing method using oxygen diffusion barrier layer between buried oxide layer and high K dielectric layer |
Also Published As
| Publication number | Publication date |
|---|---|
| US20050142738A1 (en) | 2005-06-30 |
| KR20050068746A (en) | 2005-07-05 |
| KR100601911B1 (en) | 2006-07-14 |
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