[go: up one dir, main page]

US7129790B2 - Phase-locked loop circuit - Google Patents

Phase-locked loop circuit Download PDF

Info

Publication number
US7129790B2
US7129790B2 US10/518,329 US51832905A US7129790B2 US 7129790 B2 US7129790 B2 US 7129790B2 US 51832905 A US51832905 A US 51832905A US 7129790 B2 US7129790 B2 US 7129790B2
Authority
US
United States
Prior art keywords
output
amplifier
feedback path
phase
gain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US10/518,329
Other versions
US20060114068A1 (en
Inventor
Jacob Midtgaard
Oluf Bagger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
WSOU Investments LLC
Original Assignee
Nokia Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Inc filed Critical Nokia Inc
Assigned to NOKIA CORPORATION reassignment NOKIA CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MIDTGAARD, JACOB, BAGGER, OLUF
Publication of US20060114068A1 publication Critical patent/US20060114068A1/en
Application granted granted Critical
Publication of US7129790B2 publication Critical patent/US7129790B2/en
Assigned to NOKIA TECHNOLOGIES OY reassignment NOKIA TECHNOLOGIES OY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NOKIA CORPORATION
Assigned to OMEGA CREDIT OPPORTUNITIES MASTER FUND, LP reassignment OMEGA CREDIT OPPORTUNITIES MASTER FUND, LP SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WSOU INVESTMENTS, LLC
Assigned to WSOU INVESTMENTS, LLC reassignment WSOU INVESTMENTS, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NOKIA TECHNOLOGIES OY
Assigned to BP FUNDING TRUST, SERIES SPL-VI reassignment BP FUNDING TRUST, SERIES SPL-VI SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WSOU INVESTMENTS, LLC
Assigned to WSOU INVESTMENTS, LLC reassignment WSOU INVESTMENTS, LLC RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: OCO OPPORTUNITIES MASTER FUND, L.P. (F/K/A OMEGA CREDIT OPPORTUNITIES MASTER FUND LP
Assigned to OT WSOU TERRIER HOLDINGS, LLC reassignment OT WSOU TERRIER HOLDINGS, LLC SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WSOU INVESTMENTS, LLC
Assigned to WSOU INVESTMENTS, LLC reassignment WSOU INVESTMENTS, LLC RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: TERRIER SSC, LLC
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
    • H03F1/0216—Continuous control
    • H03F1/0222—Continuous control by using a signal derived from the input signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
    • H03F1/0216—Continuous control
    • H03F1/0233—Continuous control by using a signal derived from the output signal, e.g. bootstrapping the voltage supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/36—Modulator circuits; Transmitter circuits
    • H04L27/366—Arrangements for compensating undesirable properties of the transmission path between the modulator and the demodulator
    • H04L27/367—Arrangements for compensating undesirable properties of the transmission path between the modulator and the demodulator using predistortion
    • H04L27/368—Arrangements for compensating undesirable properties of the transmission path between the modulator and the demodulator using predistortion adaptive predistortion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/12—Indirect frequency synthesis using a mixer in the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

Definitions

  • the present invention relates to a phase locked loop circuit.
  • the modulation scheme is a constant amplitude scheme, also referred to as constant envelope modulation, which permits use of efficient non-linear amplifiers.
  • EDGE and UMTS use non-constant envelope modulation schemes.
  • the drawback is that the amplification of non-constant envelope RF signals requires the use of linear power amplifiers, which are inherently less efficient. The lower power efficiency of linear amplifiers translates into higher power consumption and higher heat dissipation.
  • linearisation architectures and schemes exist, including fixed and adaptive pre-distortion, adaptive bias, envelope elimination and restoration, polar loop and Cartesian loop transmitters. Details of such devices are shown in “Increasing Talk-Time with Efficient Linear PA's”, IEE Seminar on TETRA Market and Technology Developments, Mann S, Beach M, Warr P and McGeehan J, Institution of Electrical Engineers, 2000, which is incorporated herein by reference.
  • Envelope elimination and restoration (EER) transmitters separate envelope and phase information from an input modulated signal.
  • the phase information is then passed through a power amplifier as a constant envelope signal, permitting the use of efficient, non-linear amplifiers, while the envelope signal is added to the power amplifier output.
  • phase feedback is employed and the power amplifier is effectively placed within phase-locked loop.
  • a problem arises in the spurious emissions are generated by the power amplifier in the period before the loop is locked at the beginning of a transmission.
  • a phase-locked loop circuit comprising an oscillator controlled in dependence on the output of a phase detector, an output amplifier for amplifying the output of the oscillator and a feedback path to the phase detector from the output of the output amplifier, characterised by a second feedback path from the output of the oscillator to the phase detector, by-passing the output amplifier, and control means for disabling the output amplifier when the loop circuit is not locked and interrupting the second feedback path when the loop circuit has become locked.
  • the second feedback path includes a variable gain amplifier, the control means being configured to interrupt the second feedback path by reducing the gain of the variable gain amplifier. More preferably, the control means is configured to interrupt the second feedback path by ramping down the gain of the variable gain amplifier. Still more preferably, the control means is configured to ramp up the gain of output amplifier on enabling thereof, the ramping down of the gain of the variable gain amplifier overlapping the ramping up of the gain of output amplifier. Phase control means may be included for matching the phase of the output of the variable gain amplifier to that of the output of the output amplifier when both are operating.
  • phase control means may comprise a variable delay in the second feedback path, a phase detector receiving a signal from the second feedback path downstream of the variable delay and a signal from the first feedback path and a low-pass filter for filtering the output of the phase detector to provide a delay control input signal for the variable delay.
  • the first and second feedback paths share a common portion. More preferably, the first and second feedback paths are united by a summer and/or the common portion includes a frequency down converter.
  • a circuit according to the present invention may be advantageously employed in an envelope elimination and restoration transmitter such that the first feedback path provides a feedback signal for a closed loop envelope restoration circuit and the control means includes an envelope controller for controlling the gain of the output amplifier.
  • a circuit according to the present invention may be advantageously employed in a mobile phone such that the output amplifier is an RF power amplifier.
  • FIG. 1 is a perspective view of a mobile telephone handset
  • FIG. 2 is a schematic diagram of mobile telephone circuitry for use in the telephone handset of FIG. 1 ;
  • FIG. 3 is a block diagram of a first embodiment of the present invention.
  • FIG. 4 illustrate the initiation of a transmission by the embodiment shown in FIG. 3 ;
  • FIG. 5 is a block diagram of a second embodiment of the present invention.
  • a mobile station in the form of a mobile telephone handset 1 includes a microphone 2 , keypad 3 , with soft keys 4 which can be programmed to perform different functions, an LCD display 5 , a speaker 6 and an antenna 7 which is contained within the housing.
  • the mobile station 1 is operable to communicate through cellular radio links with individual public land mobile networks (PLMNs) operating according to communication schemes such as UMTS and EDGE.
  • PLMNs public land mobile networks
  • FIG. 2 illustrates the major circuit components of the telephone handset 1 .
  • Signal processing is carried out under the control of a digital micro-controller 9 which has an associated flash memory 10 .
  • Electrical analogue audio signals are produced by microphone 2 and amplified by pre-amplifier 11 .
  • pre-amplifier 11 Similarly, analogue audio signals are fed to the speaker 6 through an amplifier 12 .
  • the micro-controller 9 receives instruction signals from the keypad and soft keys 3 , 4 and controls operation of the LCD display 5 .
  • a smart card 13 in the form of a GSM SIM card which contains the usual GSM international mobile subscriber identity (IMSI) and an encryption key K i that is used for encoding the radio transmission in a manner well known per se.
  • IMSI GSM international mobile subscriber identity
  • K i an encryption key that is used for encoding the radio transmission in a manner well known per se.
  • the SIM card is removably received in a SIM card reader 14 .
  • the mobile telephone circuitry includes a codec 15 and an rf stage 16 including a power amplifier stage 17 feeding the antenna 7 .
  • the codec 15 receives analogue signals from the microphone amplifier 11 , digitises them into an appropriate signal format and feeds them to the power amplifier stage 17 in the rf stage 16 for transmission through the antenna 7 to the PLMN shown in FIG. 1 .
  • signals received from the PLMN are fed through the antenna 7 to be demodulated in the rf stage 16 and fed to codec 15 , so as to produce analogue signals fed to the amplifier 12 and speaker 6 .
  • the power amplifier stage 17 comprises an envelope elimination and restoration (EER) transmitter 18 which separates the envelope and phase components of an input modulated IF signal into two separate forward paths 19 , 20 .
  • EER envelope elimination and restoration
  • a common feedback path 21 is used for control of both the envelope and phase components of the RF output by the amplifier stage 17 .
  • the envelope forward path 19 comprises first and second envelope detectors 22 , 23 which detect the envelopes of the input modulated IF signal and the feedback signal from the feedback path 21 respectively.
  • the outputs of the envelope detectors 22 , 23 are fed to respective inputs of a comparator 24 .
  • the output of the comparator 24 is filtered by a low-pass filter 25 and applied to an envelope controller 26 .
  • the envelope controller 26 comprises a fast power supply modulator which directly modulates the supply voltage of the power amplifier 27 itself.
  • the phase forward path 20 comprises first and second limiters 28 , 29 which limit the input modulated IF signal and the feedback signal respectively to produce respective constant-amplitude signals.
  • the constant amplitude signals are applied to a phase detector 30 and the output of the phase detector 30 is filtered by a low-pass filter 31 and applied to a voltage-controlled oscillator 32 as is conventional in a phase-lock loop.
  • the RF signal produced by the voltage-controlled oscillator 32 is input into the power amplifier 27 which amplifies it in dependence on the signal input to the envelope controller 26 .
  • the output of the voltage-controlled oscillator 32 is also fed to a variable gain amplifier 33 which forms a branch of the common feedback path 21 .
  • a summer 34 receives the output of the variable gain amplifier 33 and the power amplifier 27 on respective inputs.
  • the output of the summer 34 is connected to one input of a mixer 35 .
  • the other input of the mixer 35 receives a local oscillator signal.
  • the output of the mixer is low-pass filtered by a feedback path filter 36 to select a low frequency mixing product.
  • the mixer 35 and filter 36 act to down convert the RF output of the amplifier 27 to the IF signal frequency.
  • the output of the feedback path filter 36 is fed to the inputs of the second envelope detector 23 and the second limited 29 to complete the feedback paths of the envelope and phase control loops.
  • a lock detector 40 is provided to detect when the phase locked loop is locked.
  • the lock detector 40 provides a control signal to the envelope controller 26 which disables the power amplifier 27 when the loop is not locked and enables the power amplifier 27 when the loop is locked.
  • the output of the lock detector 40 is also input into an amplifier control circuit 41 which produces a gain control signal for the variable gain amplifier 33 .
  • the amplifier control circuit 41 When the loop is not locked, the amplifier control circuit 41 outputs a circuit that keeps the variable gain amplifier's gain at a maximum. However, when lock is achieved and the output of the lock detector 40 changes state, the amplifier control circuit 41 outputs a signal that causes the gain of the variable gain amplifier 33 to decay to zero.
  • the power amplifier 27 is disabled and the voltage-controlled oscillator 32 runs freely, although it could also be disabled in the absence of an input IF signal.
  • the voltage-controlled oscillator 32 When an IF signal is initially input, the voltage-controlled oscillator 32 is locked to the input IF signal by the action of the loop comprising the voltage-controlled oscillator 32 , the variable gain amplifier 33 , the mixer 35 , the feedback path filter 36 , the second limiter 29 , the phase detector 30 and the low-pass filter 31 . Since the power amplifier 27 is not producing an output, the summer 34 can be disregarded. During this period the frequency and phase of the voltage-controlled oscillator 32 vary until lock is achieved. Once lock has been achieved and the frequency and phase of the voltage-controlled oscillator 32 have stabilised, the output of the lock detector 40 changes state and the power amplifier 27 is enabled. The gain of the power amplifier 27 is ramped up to avoid sharp transitions in the output RF signal. While the gain of the power amplifier 27 is ramping up, the gain of the variable gain amplifier is ramped down by the amplifier control circuit 41 so that the feedback signal becomes dominated by the output of the power amplifier 27 and then completely dependent on the output of the power amplifier
  • variable gain amplifier 33 The gain of the variable gain amplifier 33 is ramped down while the gain of the power amplifier 27 is ramping up to ensure that the amplitude of feedback signal is always sufficient to be limited by the second limiter 29 .
  • a second embodiment is substantially the same as the first embodiment, described above, except that a delay locked loop is added to the control the phase of the signal input to the variable gain amplifier 33 .
  • the delay locked loop is used so that during the transition from control on the basis of the voltage-controlled oscillator output to control on the basis of the power amplifier output, the output from the variable gain amplifier 33 does not tend to cancel the feedback from the power amplifier 27 due to a significant phase difference between the signals.
  • the delay locked loop comprises a voltage-controlled delay 37 for controllably delaying the output of the voltage-controlled oscillator 32 input into the variable gain amplifier 33 , a phase detector 38 connected to receive the input to the variable gain amplifier 33 and the output of the power amplifier 27 as its inputs and a low-pass filter 39 for filtering the output of the phase detector 38 to provide a control signal for the voltage-controlled delay 37 .
  • the phase detector of the delay locked loop receives the outputs of the variable gain amplifier and the power amplifier as its inputs.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Transmitters (AREA)
  • Amplifiers (AREA)

Abstract

A phase-locked loop circuit has an output amplifier (27) and a main feedback path from the output of the output amplifier (27). A subsidiary feedback path is provided directly from the output of the circuit's VCO (32). At the start of operation, the output amplifier (27) is disabled and the subsidiary feedback path is used until lock is achieved. Then the output amplifier (27) is enabled and the main feedback loop is used. This avoids spurious outputs from the outer amplifier while to loop locks.

Description

This application is the National Stage of International Application No. PCT/EP02/05722, International Filing Date, May 24, 2002, which designated the United States of America, and which international application was published under PCT Article 21(2) as WO Publication No. WO 03/100978 A1.
FIELD OF THE INVENTION
The present invention relates to a phase locked loop circuit.
BACKGROUND TO THE INVENTION
The present trend in portable communications devices such as mobile telephones is to increasingly lightweight devices with increased talk-time between battery recharge cycles. Such developments require ever more efficient radio-frequency (RF) amplifiers to minimise power consumption. In cellular systems such as GSM, the modulation scheme is a constant amplitude scheme, also referred to as constant envelope modulation, which permits use of efficient non-linear amplifiers. However, recent types of communication system such as EDGE and UMTS use non-constant envelope modulation schemes. The drawback is that the amplification of non-constant envelope RF signals requires the use of linear power amplifiers, which are inherently less efficient. The lower power efficiency of linear amplifiers translates into higher power consumption and higher heat dissipation.
A variety of linearisation architectures and schemes exist, including fixed and adaptive pre-distortion, adaptive bias, envelope elimination and restoration, polar loop and Cartesian loop transmitters. Details of such devices are shown in “Increasing Talk-Time with Efficient Linear PA's”, IEE Seminar on TETRA Market and Technology Developments, Mann S, Beach M, Warr P and McGeehan J, Institution of Electrical Engineers, 2000, which is incorporated herein by reference. However, many of these devices and techniques are unsuitable for battery operated portable devices such as mobile telephones, or are incapable of meeting current RF design standards, such as the TETRA linearity standard, ETSI publication ETS 300 396-2; “Trans-European Trunked Radio (TETRA);—Voice plus Data (V+D)—Part 2: Air Interface (AI)”; March 1996.
Envelope elimination and restoration (EER) transmitters separate envelope and phase information from an input modulated signal. The phase information is then passed through a power amplifier as a constant envelope signal, permitting the use of efficient, non-linear amplifiers, while the envelope signal is added to the power amplifier output. In order to correct AM-PM distortion, phase feedback is employed and the power amplifier is effectively placed within phase-locked loop.
A problem arises in the spurious emissions are generated by the power amplifier in the period before the loop is locked at the beginning of a transmission.
SUMMARY OF THE INVENTION
According to the present invention, there is provided a phase-locked loop circuit comprising an oscillator controlled in dependence on the output of a phase detector, an output amplifier for amplifying the output of the oscillator and a feedback path to the phase detector from the output of the output amplifier, characterised by a second feedback path from the output of the oscillator to the phase detector, by-passing the output amplifier, and control means for disabling the output amplifier when the loop circuit is not locked and interrupting the second feedback path when the loop circuit has become locked.
Thus, unwanted components in the output of the output amplifier can be avoided by ensuring that the amplifier does not become active until the loop has achieved lock.
Preferably, the second feedback path includes a variable gain amplifier, the control means being configured to interrupt the second feedback path by reducing the gain of the variable gain amplifier. More preferably, the control means is configured to interrupt the second feedback path by ramping down the gain of the variable gain amplifier. Still more preferably, the control means is configured to ramp up the gain of output amplifier on enabling thereof, the ramping down of the gain of the variable gain amplifier overlapping the ramping up of the gain of output amplifier. Phase control means may be included for matching the phase of the output of the variable gain amplifier to that of the output of the output amplifier when both are operating. Such phase control means may comprise a variable delay in the second feedback path, a phase detector receiving a signal from the second feedback path downstream of the variable delay and a signal from the first feedback path and a low-pass filter for filtering the output of the phase detector to provide a delay control input signal for the variable delay.
Preferably, the first and second feedback paths share a common portion. More preferably, the first and second feedback paths are united by a summer and/or the common portion includes a frequency down converter.
A circuit according to the present invention may be advantageously employed in an envelope elimination and restoration transmitter such that the first feedback path provides a feedback signal for a closed loop envelope restoration circuit and the control means includes an envelope controller for controlling the gain of the output amplifier.
A circuit according to the present invention may be advantageously employed in a mobile phone such that the output amplifier is an RF power amplifier.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a perspective view of a mobile telephone handset;
FIG. 2 is a schematic diagram of mobile telephone circuitry for use in the telephone handset of FIG. 1;
FIG. 3 is a block diagram of a first embodiment of the present invention;
FIG. 4 illustrate the initiation of a transmission by the embodiment shown in FIG. 3; and
FIG. 5 is a block diagram of a second embodiment of the present invention.
 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Embodiments of the invention will now be described by way of example with reference to the accompanying drawings.
Referring to FIG. 1, a mobile station in the form of a mobile telephone handset 1 includes a microphone 2, keypad 3, with soft keys 4 which can be programmed to perform different functions, an LCD display 5, a speaker 6 and an antenna 7 which is contained within the housing.
The mobile station 1 is operable to communicate through cellular radio links with individual public land mobile networks (PLMNs) operating according to communication schemes such as UMTS and EDGE.
FIG. 2 illustrates the major circuit components of the telephone handset 1. Signal processing is carried out under the control of a digital micro-controller 9 which has an associated flash memory 10. Electrical analogue audio signals are produced by microphone 2 and amplified by pre-amplifier 11. Similarly, analogue audio signals are fed to the speaker 6 through an amplifier 12. The micro-controller 9 receives instruction signals from the keypad and soft keys 3, 4 and controls operation of the LCD display 5.
Information concerning the identity of the user is held on a smart card 13 in the form of a GSM SIM card which contains the usual GSM international mobile subscriber identity (IMSI) and an encryption key Ki that is used for encoding the radio transmission in a manner well known per se. The SIM card is removably received in a SIM card reader 14.
The mobile telephone circuitry includes a codec 15 and an rf stage 16 including a power amplifier stage 17 feeding the antenna 7. The codec 15 receives analogue signals from the microphone amplifier 11, digitises them into an appropriate signal format and feeds them to the power amplifier stage 17 in the rf stage 16 for transmission through the antenna 7 to the PLMN shown in FIG. 1. Similarly, signals received from the PLMN are fed through the antenna 7 to be demodulated in the rf stage 16 and fed to codec 15, so as to produce analogue signals fed to the amplifier 12 and speaker 6.
Referring to FIG. 3, the power amplifier stage 17 comprises an envelope elimination and restoration (EER) transmitter 18 which separates the envelope and phase components of an input modulated IF signal into two separate forward paths 19, 20. A common feedback path 21 is used for control of both the envelope and phase components of the RF output by the amplifier stage 17.
The envelope forward path 19 comprises first and second envelope detectors 22, 23 which detect the envelopes of the input modulated IF signal and the feedback signal from the feedback path 21 respectively. The outputs of the envelope detectors 22, 23 are fed to respective inputs of a comparator 24. The output of the comparator 24 is filtered by a low-pass filter 25 and applied to an envelope controller 26.
The envelope controller 26 comprises a fast power supply modulator which directly modulates the supply voltage of the power amplifier 27 itself.
The phase forward path 20 comprises first and second limiters 28, 29 which limit the input modulated IF signal and the feedback signal respectively to produce respective constant-amplitude signals. The constant amplitude signals are applied to a phase detector 30 and the output of the phase detector 30 is filtered by a low-pass filter 31 and applied to a voltage-controlled oscillator 32 as is conventional in a phase-lock loop. The RF signal produced by the voltage-controlled oscillator 32 is input into the power amplifier 27 which amplifies it in dependence on the signal input to the envelope controller 26.
The output of the voltage-controlled oscillator 32 is also fed to a variable gain amplifier 33 which forms a branch of the common feedback path 21. A summer 34 receives the output of the variable gain amplifier 33 and the power amplifier 27 on respective inputs. The output of the summer 34 is connected to one input of a mixer 35. The other input of the mixer 35 receives a local oscillator signal. The output of the mixer is low-pass filtered by a feedback path filter 36 to select a low frequency mixing product. Thus, the mixer 35 and filter 36 act to down convert the RF output of the amplifier 27 to the IF signal frequency.
The output of the feedback path filter 36 is fed to the inputs of the second envelope detector 23 and the second limited 29 to complete the feedback paths of the envelope and phase control loops.
A lock detector 40 is provided to detect when the phase locked loop is locked. The lock detector 40 provides a control signal to the envelope controller 26 which disables the power amplifier 27 when the loop is not locked and enables the power amplifier 27 when the loop is locked.
The output of the lock detector 40 is also input into an amplifier control circuit 41 which produces a gain control signal for the variable gain amplifier 33. When the loop is not locked, the amplifier control circuit 41 outputs a circuit that keeps the variable gain amplifier's gain at a maximum. However, when lock is achieved and the output of the lock detector 40 changes state, the amplifier control circuit 41 outputs a signal that causes the gain of the variable gain amplifier 33 to decay to zero.
Referring to FIG. 4, when a transmission is not being made, the power amplifier 27 is disabled and the voltage-controlled oscillator 32 runs freely, although it could also be disabled in the absence of an input IF signal.
When an IF signal is initially input, the voltage-controlled oscillator 32 is locked to the input IF signal by the action of the loop comprising the voltage-controlled oscillator 32, the variable gain amplifier 33, the mixer 35, the feedback path filter 36, the second limiter 29, the phase detector 30 and the low-pass filter 31. Since the power amplifier 27 is not producing an output, the summer 34 can be disregarded. During this period the frequency and phase of the voltage-controlled oscillator 32 vary until lock is achieved. Once lock has been achieved and the frequency and phase of the voltage-controlled oscillator 32 have stabilised, the output of the lock detector 40 changes state and the power amplifier 27 is enabled. The gain of the power amplifier 27 is ramped up to avoid sharp transitions in the output RF signal. While the gain of the power amplifier 27 is ramping up, the gain of the variable gain amplifier is ramped down by the amplifier control circuit 41 so that the feedback signal becomes dominated by the output of the power amplifier 27 and then completely dependent on the output of the power amplifier 27.
The gain of the variable gain amplifier 33 is ramped down while the gain of the power amplifier 27 is ramping up to ensure that the amplitude of feedback signal is always sufficient to be limited by the second limiter 29.
Referring to FIG. 5, a second embodiment is substantially the same as the first embodiment, described above, except that a delay locked loop is added to the control the phase of the signal input to the variable gain amplifier 33. The delay locked loop is used so that during the transition from control on the basis of the voltage-controlled oscillator output to control on the basis of the power amplifier output, the output from the variable gain amplifier 33 does not tend to cancel the feedback from the power amplifier 27 due to a significant phase difference between the signals.
The delay locked loop comprises a voltage-controlled delay 37 for controllably delaying the output of the voltage-controlled oscillator 32 input into the variable gain amplifier 33, a phase detector 38 connected to receive the input to the variable gain amplifier 33 and the output of the power amplifier 27 as its inputs and a low-pass filter 39 for filtering the output of the phase detector 38 to provide a control signal for the voltage-controlled delay 37.
In another embodiment, the phase detector of the delay locked loop receives the outputs of the variable gain amplifier and the power amplifier as its inputs.

Claims (10)

1. A phase-locked loop circuit comprising:
an oscillator controlled in dependence on the output of a phase detector;
an output amplifier for amplifying the output of the oscillator;
a first feedback path to the phase detector from the output of the output amplifier;
a second feedback path from the output of the oscillator to the phase detector, by-passing the output amplifier; and
control means for disabling the output amplifier when the loop circuit is not locked and interrupting the second feedback path when the loop circuit has become locked;
wherein the second feedback path includes a variable gain amplifier and the control means is configured to interrupt the second feedback path by reducing the gain of the variable gain amplifier.
2. A circuit according to claim 1, wherein the control means is configured to interrupt the second feedback path by ramping down the gain of the variable gain amplifier.
3. A circuit according to claim 2, wherein the control means is configured to ramp up the gain of output amplifier on enabling thereof, the ramping down of the gain of the variable gain amplifier overlapping the ramping up of the gain of output amplifier.
4. A circuit according to claim 3, including phase control means for matching the phase of the output of the variable gain amplifier to that of the output of the output amplifier when both are operating.
5. A circuit according to claim 4, wherein the phase control means comprises a variable delay in the second feedback path, a phase detector receiving a signal from the second feedback path downstream of the variable delay and a signal from the first feedback path and a low-pass filter for filtering the output of the phase detector to provide a delay control input signal for the variable delay.
6. A circuit according to claim 1, wherein the first and second feedback paths share a common portion.
7. A circuit according to claim 6, wherein the first and second feedback paths are united by a summer.
8. A circuit according to claim 6, wherein said common portion includes a frequency down converter.
9. A circuit according to claim 1, wherein the first feedback path provides a feedback signal for a closed loop envelope restoration circuit of an envelope elimination and restoration transmitter, the control means including an envelope controller for controlling the gain of the output amplifier.
10. A circuit according to claim 1, wherein the output amplifier is an RF power amplifier of a mobile phone.
US10/518,329 2002-05-24 2002-05-24 Phase-locked loop circuit Expired - Lifetime US7129790B2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2002/005722 WO2003100978A1 (en) 2002-05-24 2002-05-24 Phase-locked loop circuit

Publications (2)

Publication Number Publication Date
US20060114068A1 US20060114068A1 (en) 2006-06-01
US7129790B2 true US7129790B2 (en) 2006-10-31

Family

ID=29558276

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/518,329 Expired - Lifetime US7129790B2 (en) 2002-05-24 2002-05-24 Phase-locked loop circuit

Country Status (3)

Country Link
US (1) US7129790B2 (en)
AU (1) AU2002344983A1 (en)
WO (1) WO2003100978A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100156471A1 (en) * 2008-12-19 2010-06-24 Frederic Roger Scalable cost function generator and method thereof
US8295394B1 (en) * 2008-10-23 2012-10-23 Scintera Networks, Inc. Error signal formation for linearization
US8706062B1 (en) 2008-12-19 2014-04-22 Scintera Networks, Inc. Self-adaptive power amplification

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004023220A1 (en) * 2004-03-11 2005-10-06 Siemens Ag Method and apparatus for generating a variable frequency vibration
US7359680B2 (en) 2004-09-14 2008-04-15 Telefonaktiebolaget Lm Ericsson (Publ) Delay calibration in polar modulation transmitters
US7983632B2 (en) * 2004-09-24 2011-07-19 Broadcom Corporation Feedback control loop for amplitude modulation in a polar transmitter with a translational loop
EP3267578B1 (en) 2016-07-08 2023-04-19 IMEC vzw Polar transmitter and method for generating a transmit signal using a polar transmitter

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5430416A (en) * 1994-02-23 1995-07-04 Motorola Power amplifier having nested amplitude modulation controller and phase modulation controller
US5982233A (en) 1996-06-28 1999-11-09 Telefonaktiebolaget Lm Ericsson Device and method for compensating phase distortion
EP0998088A2 (en) 1998-10-27 2000-05-03 Nokia Mobile Phones Ltd. Modulation with separate stages for phase and amplitude modulation
EP1052770A1 (en) 1999-05-10 2000-11-15 Securicor Wireless Technology Limited Modulator using AM and PM

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5430416A (en) * 1994-02-23 1995-07-04 Motorola Power amplifier having nested amplitude modulation controller and phase modulation controller
US5982233A (en) 1996-06-28 1999-11-09 Telefonaktiebolaget Lm Ericsson Device and method for compensating phase distortion
EP0998088A2 (en) 1998-10-27 2000-05-03 Nokia Mobile Phones Ltd. Modulation with separate stages for phase and amplitude modulation
EP1052770A1 (en) 1999-05-10 2000-11-15 Securicor Wireless Technology Limited Modulator using AM and PM

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8295394B1 (en) * 2008-10-23 2012-10-23 Scintera Networks, Inc. Error signal formation for linearization
US20100156471A1 (en) * 2008-12-19 2010-06-24 Frederic Roger Scalable cost function generator and method thereof
US8433745B2 (en) 2008-12-19 2013-04-30 Scintera Networks, Inc. Scalable cost function generator and method thereof
US8706062B1 (en) 2008-12-19 2014-04-22 Scintera Networks, Inc. Self-adaptive power amplification

Also Published As

Publication number Publication date
AU2002344983A1 (en) 2003-12-12
WO2003100978A1 (en) 2003-12-04
US20060114068A1 (en) 2006-06-01

Similar Documents

Publication Publication Date Title
US7062236B2 (en) Transmitter circuits
US7049887B2 (en) Envelope elimination and restoration linear amplifier
US6374092B1 (en) Efficient multimode power amplifier
AU672549B2 (en) Power amplifier having nested amplitude modulation controller and phase modulation controller
JP3711109B2 (en) Continuous closed-loop power control system including injection of modulation into the power amplifier of a radiotelephone
EP1755214B1 (en) RF power amplifier for wireless communication apparatus
Sowlati et al. Quad-band GSM/GPRS/EDGE polar loop transmitter
US6438360B1 (en) Amplifier system with load control to produce an amplitude envelope
CA2109410C (en) High efficiency dual mode power amplifier apparatus
KR100359601B1 (en) Load envelope following amplifier system
JP4230238B2 (en) Transmitting apparatus and adjustment method thereof
US7193459B1 (en) Power amplifier control technique for enhanced efficiency
US6681101B1 (en) RF transmitter with extended efficient power control range
US7424276B2 (en) Transmitter and wireless communication apparatus using the transmitter
US20060293005A1 (en) Wireless transmission apparatus, polar modulation transmission apparatus, and wireless communication apparatus
CA2259315C (en) Device and method for compensating phase distortion
JP2000514963A (en) Apparatus and method for wireless transmitter
US7129790B2 (en) Phase-locked loop circuit
US6122491A (en) Communications system using power amplifier with dynamic biasing
US6760604B2 (en) Portable radio transceiver having shared power source for audio and RF amplifiers
CN1939024A (en) Phase modulating apparatus, communication device, mobile wireless unit, and phase modulating method
US7412215B1 (en) System and method for transitioning from one PLL feedback source to another
JPH08191224A (en) Mobile communication device
JP4048589B2 (en) Transmission power control system for mobile phones
JP4377722B2 (en) Transmitter

Legal Events

Date Code Title Description
AS Assignment

Owner name: NOKIA CORPORATION, FINLAND

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MIDTGAARD, JACOB;BAGGER, OLUF;REEL/FRAME:017165/0601;SIGNING DATES FROM 20050905 TO 20051022

STCF Information on status: patent grant

Free format text: PATENTED CASE

CC Certificate of correction
CC Certificate of correction
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FEPP Fee payment procedure

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: NOKIA TECHNOLOGIES OY, FINLAND

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NOKIA CORPORATION;REEL/FRAME:035570/0457

Effective date: 20150116

AS Assignment

Owner name: OMEGA CREDIT OPPORTUNITIES MASTER FUND, LP, NEW YORK

Free format text: SECURITY INTEREST;ASSIGNOR:WSOU INVESTMENTS, LLC;REEL/FRAME:043966/0574

Effective date: 20170822

Owner name: OMEGA CREDIT OPPORTUNITIES MASTER FUND, LP, NEW YO

Free format text: SECURITY INTEREST;ASSIGNOR:WSOU INVESTMENTS, LLC;REEL/FRAME:043966/0574

Effective date: 20170822

AS Assignment

Owner name: WSOU INVESTMENTS, LLC, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NOKIA TECHNOLOGIES OY;REEL/FRAME:043953/0822

Effective date: 20170722

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.)

FEPP Fee payment procedure

Free format text: 11.5 YR SURCHARGE- LATE PMT W/IN 6 MO, LARGE ENTITY (ORIGINAL EVENT CODE: M1556); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12

AS Assignment

Owner name: BP FUNDING TRUST, SERIES SPL-VI, NEW YORK

Free format text: SECURITY INTEREST;ASSIGNOR:WSOU INVESTMENTS, LLC;REEL/FRAME:049235/0068

Effective date: 20190516

AS Assignment

Owner name: WSOU INVESTMENTS, LLC, CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:OCO OPPORTUNITIES MASTER FUND, L.P. (F/K/A OMEGA CREDIT OPPORTUNITIES MASTER FUND LP;REEL/FRAME:049246/0405

Effective date: 20190516

AS Assignment

Owner name: OT WSOU TERRIER HOLDINGS, LLC, CALIFORNIA

Free format text: SECURITY INTEREST;ASSIGNOR:WSOU INVESTMENTS, LLC;REEL/FRAME:056990/0081

Effective date: 20210528

AS Assignment

Owner name: WSOU INVESTMENTS, LLC, CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:TERRIER SSC, LLC;REEL/FRAME:056526/0093

Effective date: 20210528