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US7285465B2 - Method of manufacturing a SiC vertical MOSFET - Google Patents

Method of manufacturing a SiC vertical MOSFET Download PDF

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US7285465B2
US7285465B2 US11/353,992 US35399206A US7285465B2 US 7285465 B2 US7285465 B2 US 7285465B2 US 35399206 A US35399206 A US 35399206A US 7285465 B2 US7285465 B2 US 7285465B2
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base region
mask
sic
ion implantation
region
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US20060134847A1 (en
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Yoichiro Tarui
Ken-ichi Ohtsuka
Masayuki Imaizumi
Hiroshi Sugimoto
Tetsuya Takami
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H01L21/0465—Making n or p doped regions or layers, e.g. using diffusion using ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H01L21/047—Making n or p doped regions or layers, e.g. using diffusion using ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide

Definitions

  • the present invention relates to a semiconductor device structure in which a vertical MOSFET using SiC is fabricated by ion implantation, and to a method of manufacturing the structure.
  • a mask for ion implantation of a source region has to be different in width from a mask for ion implantation of a base region (see JP 10-233503 A, for example).
  • the conventional semiconductor device manufacturing method described above increases the number of steps to manufacture the MOSFET.
  • the process precision of each mask and the accuracy of aligning the two masks influence the channel length, which is one of the factors that determine characteristics of the MOSFET thus posing a great obstacle to device miniaturization.
  • device miniaturization is advanced, it brings another problem of increased JFET resistance, which is in a trade-off relation with channel resistance lowered by the miniaturization.
  • the present invention has been made in view of the above, and an object of the present invention is therefore to provide a semiconductor device, which is improved in the trade-off relation between channel resistance and JFET resistance, which presents a problem in device miniaturization.
  • Another object of the present invention is to provide a method of manufacturing a semiconductor device which makes it possible to use the same mask to form by ion implantation a source region and base region of a vertical MOSFET that is formed from SiC, and to advance device miniaturization.
  • a semiconductor device of the present invention relates to a vertical MOSFET that uses SiC, and has a tapered base region.
  • a source region and a base region are formed by ion implantation using the same mask.
  • a base region of a vertical MOSFET that uses SiC is tapered, thereby being capable of improving the trade-off relation between channel resistance and JFET resistance, and of advancing device miniaturization.
  • a method of manufacturing a semiconductor device of the invention when a vertical MOSFET using SiC is manufactured, the same mask is used to form a source region and a base region by ion implantation and an impurity is selectively doped in a self-aligning manner to complete the MOSFET.
  • the manufacturing method thus makes it possible to advance device miniaturization.
  • FIG. 1 is a sectional view showing a semiconductor device (SiC vertical MOSFET) manufactured in accordance with Embodiment 1 of the present invention
  • FIG. 2 is a diagram to illustrate the device structure of the semiconductor device that is manufactured in accordance with Embodiment 1 of the present invention
  • FIG. 3 is a diagram to illustrate ON resistance of the semiconductor device that is manufactured in accordance with Embodiment 1 of the present invention
  • FIG. 4 is a graph showing results of an experiment that has been conducted to examine the relation between interval Ld of a p base region 5 and JFET resistance Rj in the semiconductor device that is manufactured in accordance with Embodiment 1 of the present invention;
  • FIG. 5 is a diagram to illustrate the relation among a taper angle ⁇ of the p base region 5 , a channel length Lch, and the intervals Ld 1 and Ld 2 of the p base region in the case where an n source region 4 is tapered in the semiconductor device that is manufactured in accordance with Embodiment 1 of the present invention;
  • FIG. 6 is a diagram to illustrate the relation among a taper angle ⁇ of the p base region 5 , a channel length Lch, and the intervals Ld 1 and Ld 2 of the p base region in the case where the n source region 4 is not tapered in the semiconductor device that is manufactured in accordance with Embodiment 1 of the present invention;
  • FIG. 7 is a graph showing the relation between the taper angle of the p base region 5 and ON resistance in the case where the n source region 4 is tapered in the semiconductor device that is manufactured in accordance with Embodiment 1 of the present invention
  • FIG. 8 is a graph showing the relation between the taper angle of the p base region 5 and ON resistance in the case where the n source region 4 is not tapered in the semiconductor device that is manufactured in accordance with Embodiment 1 of the present invention
  • FIG. 9 is a diagram illustrating the taper angle of the p base region 5 and the bounds of punch-through in the semiconductor device that is manufactured in accordance with Embodiment 1 of the present invention.
  • FIG. 10 is a diagram to illustrate a method of manufacturing a semiconductor device in accordance with Embodiment 2 of the present invention by showing a method of forming a source region 4 and a base region 5 by ion implantation;
  • FIG. 11 is a diagram showing the relation among the taper angle of a mask, a channel length Lch, and the taper angle of the p base region 5 in the case where the implantation mask has the same range as SiC in the semiconductor device that is manufactured in accordance with Embodiment 2 of the present invention;
  • FIG. 12 is a diagram showing the relation among the taper angle of the mask, the channel length Lch, and the taper angle of the p base region 5 in the case where the implantation mask is a SiO 2 mask in the semiconductor device that is manufactured in accordance with Embodiment 2 of the present invention;
  • FIG. 13 is a sectional view showing a semiconductor device (SiC vertical MOSFET) manufactured in accordance with Embodiments 3 and 5 of the present invention.
  • FIG. 14 is a diagram to illustrate a method of manufacturing a semiconductor device in accordance with Embodiment 3 of the present invention by showing a method of forming a source region 4 and a base region 5 by ion implantation;
  • FIG. 15 is a diagram showing the relation among the ion implantation angle, a channel length Lch, and the taper angle of the p base region 5 in the case where an implantation mask has the same range as SiC in the semiconductor device that is manufactured in accordance with Embodiment 3 of the present invention;
  • FIG. 16 is a diagram showing the relation among the ion implantation angle, the channel length Lch, and the taper angle of the p base region 5 in the case where the implantation mask is a SiO 2 mask in the semiconductor device that is manufactured in accordance with Embodiment 3 of the present invention;
  • FIG. 17 is a graph showing the relation between the ion implantation angle and ON resistance in the case where the implantation mask has the same range as SiC in the semiconductor device that is manufactured in accordance with Embodiment 3 of the present invention.
  • FIG. 18 is a graph showing the relation between the ion implantation angle and ON resistance in the case where the implantation mask is a SiO 2 mask in the semiconductor device that is manufactured in accordance with Embodiment 3 of the present invention.
  • FIG. 19 is a sectional view showing a semiconductor device (SiC vertical MOSFET) manufactured in accordance with Embodiments 4 and 6 of the present invention.
  • FIG. 20 is a diagram to illustrate a method of manufacturing a semiconductor device in accordance with Embodiment 4 of the present invention by showing a method of forming a source region 4 and a base region 5 by ion implantation;
  • FIG. 21 is a diagram to illustrate a method of manufacturing a semiconductor device in accordance with Embodiment 5 of the present invention by showing a method of forming a source region 4 and a base region 5 by ion implantation;
  • FIG. 22 is a diagram to illustrate a method of manufacturing a semiconductor device in accordance with Embodiment 6 of the present invention by showing a method of forming a source region 4 and a base region 5 by ion implantation.
  • An outline of the present invention is given first.
  • manufacture of a vertical MOSFET that uses SiC it is difficult to diffuse an impurity through heat treatment, thus excluding from options a self-alignment process through thermal diffusion of an impurity as the one employed in manufacture of a vertical MOSFET that uses Si.
  • selective impurity doping is performed by ion implantation.
  • Si vertical MOSFET's high thermal diffusibility makes it difficult to control the shape (taper angle) of a region formed by ion implantation (ion implantation region) whereas SiC vertical MOSFET's thermal diffusibility that is ignorably low makes it easy to control the shape (taper angle) of an ion implantation region in a depth direction and in a lateral direction.
  • an implantation mask has vertical side faces for vertical ion implantation with respect to a substrate, and masks different from each other in width have to be used to form a source region and a base region by ion implantation since prior art is incapable of impurity doping by self-alignment process that uses the same mask.
  • activation annealing at a temperature of about 1500° C. is needed and it could cause some damage like roughening of a SiC surface.
  • a gate electrode serves as the only mask that is used throughout ion implantation, the gate electrode and a gate oxide film are damaged upon the activation annealing. It is therefore difficult to use a gate electrode as an implantation mask.
  • a vertical MOSFET that uses SiC according to the present invention is characterized by using the same ion implantation mask to form a source region and a base region by ion implantation.
  • the mask is tapered or ions are implanted obliquely, thereby making it possible to manufacture the MOSFET through selective impurity doping in a self-aligning manner.
  • the base region formed by this method is given a tapered shape and accordingly is characterized by its JFET resistance smaller than that of a conventional base region, which has an approximately vertical shape.
  • FIG. 1 is a sectional view showing a semiconductor device (SiC vertical MOSFET) manufactured in accordance with Embodiment 1 of the present invention.
  • a source region 4 and a base region 5 are formed by ion implantation in a drift region 6 , which is formed through epitaxial growth on a substrate 7 .
  • a gate oxide film 2 , a gate electrode 1 , a source electrode 3 , and a drain electrode 8 are formed to complete the MOSFET.
  • ON resistance which is indicative of the performance of the semiconductor device (vertical MOSFET) is divided into several components: source contact resistance Rcs, n source sheet resistance Rn+, channel resistance Rch, JFET resistance Rj, drift resistance Rd, substrate resistance Rsub, and drain contact resistance Rcd.
  • the channel resistance Rch is currently the largest in a vertical MOSFET that uses SiC, and presents the greatest obstacle to practical application of a SiC vertical MOSFET.
  • One way to reduce the channel resistance Rch is device miniaturization (in which a MOSFET is reduced in channel length and increased in channel width).
  • a MOSFET is reduced in channel length and increased in channel width.
  • there is a trade-off relation between an interval of the p base region 5 (see FIG. 2 , Ld 1 : an upper interval of the p base region 5 , Ld 2 : a lower interval of the p base region 5 ) and the JFET resistance Rj, causing Rj to increase while reducing Ld.
  • Providing the p base region 5 with the taper angle ⁇ brings an effect of improving the trade-off relation between the channel resistance Rch and the JFET resistance Rj.
  • a MOSFET with the taper angle ⁇ set to 0° is first prepared as a test sample to examine the relation between the interval of the p base region 5 and the JFET resistance Rj. Results thereof are shown in FIG. 4 .
  • the test sample is manufactured as a device that is capable of withstanding 1200 V to be used for an in-vehicle or industrial inverter, and employs for the drift region 6 a 10 ⁇ m-thick substrate having a carrier concentration of 1 ⁇ 10 16 cm ⁇ 3 .
  • the JFET resistance Rj can be reduced by increasing the interval Ld of the p base region 5 .
  • this lowers the withstand voltage of the MOSFET.
  • an increased electric field is applied to the gate oxide film 2 and the withstand voltage of the MOSFET becomes lower than a theoretical withstand voltage calculated from a p-n junction.
  • the JFET resistance Rj rapidly increases when the interval Ld of the p base region 5 becomes 2 ⁇ m or smaller, although the interval Ld of the p base region 5 is desired to be small from the viewpoint of miniaturization, and the withstand voltage of the MOSFET is lowered when the interval Ld of the p base region 5 becomes 4 ⁇ m or larger. Accordingly, the optimum value of the interval Ld of the p base region 5 is between 2 ⁇ m and 4 ⁇ m.
  • the trade-off relation between the JFET resistance Rj and the channel resistance Rch of the p base region 5 when the p base region 5 has the taper angle ⁇ is examined based on the above results.
  • the relation among the taper angle ⁇ , the JFET resistance rj, and the channel resistance Rch is calculated on the assumption that the device is for use as an in-vehicle or industrial inverter and is capable of withstanding 1200 V.
  • the implantation depth of the p base region 5 is given as dp
  • the implantation depth of the n source region 4 is given as dn
  • the channel length Lch and the intervals Ld 1 and Ld 2 of the p base region 5 satisfy the relation as the one shown in FIG. 5 or 6 .
  • the p base region 5 and the n source region 4 have the same taper angle ⁇ , the relation shown in FIG.
  • parameters of the MOSFET which is assumed to be a device having a withstand voltage of 1200 V for use as an in-vehicle or industrial inverter and which uses as the drift region 6 a 10 ⁇ m-thick substrate having a carrier concentration of 1 ⁇ 10 16 cm ⁇ 3 , include setting dp to 0.9 ⁇ m and dn to 0.3 ⁇ m.
  • the interval Ld 2 in relation to the taper angle ⁇ is calculated setting Ld 1 to 2.5 ⁇ m and, assuming that the interval Ld 2 determines the JFET resistance Rj, the JFET resistance Rj is obtained from FIG. 4 .
  • the channel resistance Rch is 20 m ⁇ /cm 2 when the channel length Lch is 2 ⁇ m according to the results of the experimental manufacture carried out by the inventors of the present invention.
  • the channel resistance Rch is expected to be reduced through device miniaturization (in which a MOSFET is reduced in channel length and increased in channel width) and improvement of the process in the future and, for that reason, the channel resistance Rch of the p base region 5 when the channel length Lch is 2 ⁇ m is assumed here to be 20, 10, and 5 m ⁇ /cm 2 .
  • the channel resistance Rch is calculated from the channel length Lch in relation to the taper angle ⁇ assuming that the channel resistance Rch is in proportion to the channel length Lch.
  • the taper angle ⁇ is small (60° or less)
  • the channel length Lch is small and accordingly the channel resistance Rch is small except when the taper angle ⁇ is 30° or less, where the lower interval Ld 2 of the p base region 5 is reduced to cause a rapid increase in JFET resistance Rj. Therefore, the taper angle ⁇ is desirably 30° to 60° (30° or more and 60° or less), more desirably, 30° to 45° (30° or more and 45° or less).
  • FIGS. 7 and 8 state that punch-through is avoided when the taper angle ⁇ is 30° or larger.
  • an interval Lp (the minimum value of an interval of the source region 4 and the base region 5 ) shown in FIG. 9 becomes 0.3 ⁇ m or less as the taper angle ⁇ reaches 30° or smaller to cause punch-through and lower the withstand voltage of the MOSFET
  • the concentration of the p base region 5 is 5 ⁇ 10 17 to 10 ⁇ 10 18 cm ⁇ 3 and the drift region has a concentration of 1 ⁇ 10 16 cm ⁇ 3 .
  • a depletion layer when the drain voltage of the MOSFET is 1200 V extends 0.11 to 0.23 ⁇ m on the side of the p base region 5 .
  • Punch-through is caused as the interval Lp becomes smaller than the depletion layer.
  • the taper angle ⁇ has to be set to 30° or more, so that the interval Lp becomes equal to or more than 0.3 ⁇ m.
  • Ld 1 2 to 4 ⁇ m.
  • the influence of the JFET resistance Rj is small and the taper angle dependency of the ON resistance is approximately identical with the one in FIGS. 7 and 8 .
  • the influence of the JFET resistance Rj is large and the absolute value of the ON resistance is larger than in FIGS.
  • the taper angle ⁇ of the p base region 5 is desirably 30° to 60°, more desirably, 30° to 45°.
  • the base region 5 of the vertical MOSFET that uses SiC is tapered to thereby improve the trade-off relation between the channel resistance and the JFET resistance and advance device miniaturization.
  • FIG. 10 is a diagram to illustrate a method of manufacturing a semiconductor device according to Embodiment 2 of the present invention in which the source region 4 and the base region 5 of the semiconductor device (SiC vertical MOSFET) shown in FIG. 1 are formed by ion implantation. If a tapered ion implantation mask 9 as shown in FIG. 10 is used in ion implantation, a taper end portion 10 is implanted with ions even though it is under the implantation mask 9 . The width of the region that is implanted with ions despite being under the implantation mask 9 is in proportion to the depth of the ion implantation.
  • the channel length and the taper angle of the base region 5 are determined by the material of the implantation mask 9 and the taper angle ⁇ . Specifically, the relation among the shape of the implantation mask, the channel length Lch, and the taper angle of the base region 5 is examined for a case (a) where the implantation mask 9 is formed from a material that has the same ion implantation range as SiC and for a case (b) where the implantation mask 9 is formed from SiO 2 , which has been used in the experimental manufacture by the inventors of the present invention (the implantation range of SiO 2 is 1.7 times longer than that of SiC). Results thereof are shown in FIGS. 11 and 12 .
  • the taper angle ⁇ of the implantation mask 9 matches the taper angle ⁇ of the p base region 5 as shown in FIG. 11 .
  • the taper angle ⁇ of the p base region 5 is desirably 30° to 60°, more desirably, 30° to 45° in the case where a device for use as an in-vehicle or industrial inverter, which has a withstand voltage of 1200 V, is manufactured.
  • a method to process the implantation mask 9 into a desired shape when the implantation mask 9 is formed from SiO 2 is dry etching using a resist mask. If the etching selective ratio of SiO 2 to the resist is large, SiO 2 alone is dry-etched to give vertical side faces to the SiO 2 implantation mask. On the other hand, if the etching selective ratio is small, the resist is dry-etched as well as the SiO 2 mask to thereby reduce the width of the resist that is used as an etching mask. Through etching under such conditions, the implantation mask made of SiO 2 is tapered and its taper angle can be controlled by the selective ratio of SiO 2 to the resist.
  • a selective impurity doping can be carried out by the above-described method through a self-alignment process that uses the same mask 9 .
  • the channel length of the MOSFET and the taper angle of the p base region 5 can readily be controlled by controlling the shape of the implantation mask 9 , and it is advantageous in miniaturization of the MOSFET
  • the trade-off relation between the channel resistance Rch and the JFET resistance Rj can be improved by providing the p base region 5 with a taper angle.
  • FIG. 13 is a sectional view showing a semiconductor device (SiC vertical MOSFET) manufactured in accordance with Embodiment 3 of the present invention.
  • a source region 4 and a base region 5 are formed by ion implantation in a drift region 6 , which is formed through epitaxial growth on a substrate 7 .
  • a gate oxide film 2 , a gate electrode 1 , a source electrode 3 , and a drain electrode 8 are formed to complete the MOSFET.
  • FIG. 14 is a diagram to illustrate a method of manufacturing a semiconductor device in accordance with Embodiment 3 of the present invention by showing a method of forming the source region 4 and the base region 5 by ion implantation.
  • N ions for example, are implanted vertically with respect to the substrate and at the same time Al ions are implanted obliquely with respect to the substrate at an implantation angle that is smaller than that of N ions.
  • an implantation mask 11 that has vertical side faces as in prior art is used, a region under the implantation mask 11 is not implanted with N ions and is implanted with Al ions alone. This region serves as a channel of the MOSFET.
  • the base region 5 is tapered to thereby obtain an effect of improving the trade-off relation between the JFET resistance Rj and the channel resistance Rch upon miniaturization as described in Embodiment 1.
  • the channel length and the taper angle of the base region 5 are determined by the material of the implantation mask 11 and the ion implantation angle. Specifically, the relation among the ion implantation angle, the channel length Lch, and the taper angle of the base region 5 is examined for a case (a) where the implantation mask 11 is formed from a material that has the same ion implantation range as SiC and for a case (b) where the implantation mask 11 is formed from SiO 2 , which has been used in the experimental manufacture by the inventors of the present invention (the implantation range of SiO 2 is 1.7 times longer than that of SiC). Results thereof are shown in FIGS. 15 and 16 .
  • the taper angle of the p base region 5 is vertical, matching the shape of the mask as shown in FIG. 15 .
  • the p base region 5 is tapered and its taper angle ⁇ ′′ is larger than 0° as shown in FIG. 16 .
  • parameters of the MOSFET which is assumed to be a device having a withstand voltage of 1200 V for use as an in-vehicle or industrial inverter and which uses as the drift region 6 a 10 ⁇ m-thick substrate having a carrier concentration of 1 ⁇ 10 16 cm ⁇ 3 , include setting dp to 0.9 ⁇ m and dn to 0.3 ⁇ m as in Embodiment 1, and the optimum implantation angle under this setting is examined.
  • the ON resistance decreases steadily as the implantation angle ⁇ is increased irrespective of how large the interval Ld 1 of the p base region 5 is.
  • the ON resistance is small when the implantation angle ⁇ is large and the channel length Lch is small.
  • punch-through takes place to lower the withstand voltage as described in Embodiment 1.
  • the optimum ion implantation angle ⁇ is 70° or less and, taking into account the margin, the implantation angle is desirably large around 60° to 70°.
  • the case (b) where the implantation mask 11 is formed from SiO 2 (which has an implantation range 1.7 times longer than that of SiC) is considered.
  • the taper angle ⁇ ′ of the p base region 5 and the channel length Lch can be calculated in relation to the ion implantation angle ⁇ .
  • the interval Ld 2 in relation to the taper angle ⁇ ′ is calculated setting Ld 1 to 2.5 ⁇ m and, assuming that the interval Ld 2 determines the JFET resistance Rj, the JFET resistance Rj is obtained from FIG. 4 .
  • the channel resistance Rch is similarly calculated from the channel length Lch.
  • Ld 1 is 2.5 ⁇ m but the tendency of steady decrease of the ON resistance to an increase of the implantation angle ⁇ is maintained as far as Ld 1 is 2 to 4 ⁇ m.
  • a large implantation angle ⁇ and a short channel length Lch mean low ON resistance and a small influence on a change of the JFET resistance Rj.
  • the implantation angle ⁇ has to be 75° or less in order to set Lp to 0.3 ⁇ m or more.
  • the ion implantation angle ⁇ has to be set to 75° or less in order to set the interval Lp to 0.3 ⁇ m or more.
  • the optimum ion implantation angle ⁇ is 75° or less and, taking into account the margin, the implantation angle is desirably large around 65° to 75°.
  • the ion implantation angle can be controlled by simply tilting a substrate to match the direction of an implantation mask utilizing orientation flat of the substrate.
  • Al is implanted at two different angles on the left and on the right in FIG. 14 , it is also possible to implant ions at two or more different angles on each side.
  • the implantation illustrated in FIG. 14 can be achieved by a single implantation operation if the substrate is tilted and rotated upon ion implantation instead of merely tilting the substrate to the left and right.
  • a selective impurity doping can be carried out by the above-described method through a self-alignment process that uses the same mask.
  • the channel length of the MOSFET can readily be controlled by controlling the depth and angle of ion implantation, and it is advantageous in MOSFET miniaturization over prior art in which different masks have to be used for ion implantation.
  • the p base region 5 can be tapered by using for an ion implantation mask a material that has a longer ion implantation range than SiC, and the trade-off relation between the channel resistance Rch and the JFET resistance Rj is thus improved upon device miniaturization.
  • FIG. 19 is a sectional view showing a semiconductor device (SiC vertical MOSFET) manufactured in accordance with Embodiment 4 of the present invention.
  • a source region 4 and a base region 5 are formed by ion implantation in a drift region 6 , which is formed through epitaxial growth on a substrate 7 .
  • a gate oxide film 2 , a gate electrode 1 , a source electrode 3 , and a drain electrode 8 are formed to complete the MOSFET.
  • FIG. 20 is a diagram to illustrate a method of manufacturing a semiconductor device in accordance with Embodiment 4 of the present invention by showing a method of forming the source region 4 and the base region 5 by ion implantation.
  • a region where the base region 5 alone is implanted with ions is created under a tapered implantation mask 9 by implanting ions vertically and obliquely with respect to the substrate using the implantation mask 9 .
  • This region serves as a channel of the MOSFET.
  • the channel length and the taper angle of the p base region 5 can be controlled by controlling the depth and implantation angle of ion implantation and the shape (taper angle) of the implantation mask.
  • Embodiment 4 a selective impurity doping can be carried out by the above-described method through a self-alignment process that uses the same mask.
  • Embodiment 4 has more parameters that control the channel length and the taper angle of the p base region 5 than Embodiments 2 and 3, making it possible to facilitate MOSFET miniaturization and improve the trade-off relation between the channel resistance Rch and the JFET resistance Rj.
  • FIG. 21 is a diagram to illustrate a method of manufacturing a semiconductor device according to Embodiment 5 of the present invention in which the source region 4 and the base region 5 of the semiconductor device (SiC vertical MOSFET) shown in FIG. 13 are formed by ion implantation.
  • the source region 4 and the base region 5 are each formed by implanting ions obliquely with respect to the substrate.
  • the width of an implanted region under a mask 10 is increased as the implantation angle ⁇ is reduced. Therefore, if the ion implantation angle ⁇ of the base region 5 is set smaller than that of the source region 4 , a region where the base region 5 alone is implanted with ions is created under the mask 10 .
  • This region serves as a channel of the MOSFET Similar to Embodiment 3, the channel length can be controlled by controlling the depth and implantation angle of ion implantation.
  • a selective impurity doping can be carried out by the above-described method through a self-alignment process that uses the same mask.
  • the channel length of the MOSFET can readily be controlled by controlling the depth and angle of ion implantation, and it is advantageous in MOSFET miniaturization over prior art in which different masks have to be used for ion implantation.
  • the p base region 5 can be tapered by using for an ion implantation mask a material that has a longer ion implantation range than SiC, and the trade-off relation between the channel resistance Rch and the JFET resistance Rj is thus improved upon MOSFET miniaturization.
  • FIG. 22 is a diagram to illustrate a method of manufacturing a semiconductor device according to Embodiment 6 of the present invention in which the source region 4 and the base region 5 of the semiconductor device (SiC vertical MOSFET) shown in FIG. 19 are formed by ion implantation.
  • the source region 4 and the base region 5 are each formed by implanting ions obliquely with respect to the substrate using the tapered implantation mask 9 .
  • the width of an implanted region under the mask 9 is increased as the implantation angle ⁇ is reduced. Therefore, if the ion implantation angle ⁇ of the p base region 5 is set smaller than that of the source region 4 , a region where the base region 5 alone is implanted with ions is created under the mask 9 .
  • This region serves as a channel of the MOSFET Combined with the effect of an implantation mask being tapered, the channel length and the taper angle of the p base region 5 can be controlled by controlling the depth and implantation angle of ion implantation and the shape (taper angle) of the implantation mask.
  • Embodiment 6 a selective impurity doping can be carried out by the above-described method through a self-alignment process that uses the same mask.
  • Embodiment 6 has more parameters that control the channel length and the taper angle of the p base region 5 than Embodiments 2 and 3, making it possible to facilitate MOSFET miniaturization.
  • the trade-off relation between the channel resistance Rch and the JFET resistance Rj can be improved by providing the p base region 5 with a taper angle.

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Abstract

A semiconductor device and its manufacturing method are provided in which the trade-off relation between channel resistance and JFET resistance, an obstacle to device miniaturization, is improved and the same mask is used to form a source region and a base region by ion implantation. In a vertical MOSFET that uses SiC, a source region and a base region are formed by ion implantation using the same tapered mask to give the base region a tapered shape. The taper angle of the tapered mask is set to 30° to 60° when the material of the tapered mask has the same range as SiC in ion implantation, and to 20° to 45° when the material of the tapered mask is SiO2.

Description

This application is a divisional of U.S. patent application Ser. No. 10/802,824, filed Mar. 18, 2004, now U.S. Pat. No. 7,029,969.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device structure in which a vertical MOSFET using SiC is fabricated by ion implantation, and to a method of manufacturing the structure.
2. Description of the Related Art
Conventionally, to manufacture a vertical MOSFET that uses SiC by ion implantation, a mask for ion implantation of a source region has to be different in width from a mask for ion implantation of a base region (see JP 10-233503 A, for example).
Because of the use of different masks in ion implantation of a source region and a base region, the conventional semiconductor device manufacturing method described above increases the number of steps to manufacture the MOSFET. In addition, the process precision of each mask and the accuracy of aligning the two masks influence the channel length, which is one of the factors that determine characteristics of the MOSFET thus posing a great obstacle to device miniaturization. Furthermore, if device miniaturization is advanced, it brings another problem of increased JFET resistance, which is in a trade-off relation with channel resistance lowered by the miniaturization.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above, and an object of the present invention is therefore to provide a semiconductor device, which is improved in the trade-off relation between channel resistance and JFET resistance, which presents a problem in device miniaturization.
Another object of the present invention is to provide a method of manufacturing a semiconductor device which makes it possible to use the same mask to form by ion implantation a source region and base region of a vertical MOSFET that is formed from SiC, and to advance device miniaturization.
A semiconductor device of the present invention relates to a vertical MOSFET that uses SiC, and has a tapered base region.
According to a method of manufacturing a semiconductor device of the present invention, when a vertical MOSFET using SiC is manufactured, a source region and a base region are formed by ion implantation using the same mask.
According to a semiconductor device of the present invention, a base region of a vertical MOSFET that uses SiC is tapered, thereby being capable of improving the trade-off relation between channel resistance and JFET resistance, and of advancing device miniaturization.
According to a method of manufacturing a semiconductor device of the invention, when a vertical MOSFET using SiC is manufactured, the same mask is used to form a source region and a base region by ion implantation and an impurity is selectively doped in a self-aligning manner to complete the MOSFET. The manufacturing method thus makes it possible to advance device miniaturization.
BRIEF DESCRIPTION OF THE DRAWINGS
In the accompanying drawings:
FIG. 1 is a sectional view showing a semiconductor device (SiC vertical MOSFET) manufactured in accordance with Embodiment 1 of the present invention;
FIG. 2 is a diagram to illustrate the device structure of the semiconductor device that is manufactured in accordance with Embodiment 1 of the present invention;
FIG. 3 is a diagram to illustrate ON resistance of the semiconductor device that is manufactured in accordance with Embodiment 1 of the present invention;
FIG. 4 is a graph showing results of an experiment that has been conducted to examine the relation between interval Ld of a p base region 5 and JFET resistance Rj in the semiconductor device that is manufactured in accordance with Embodiment 1 of the present invention;
FIG. 5 is a diagram to illustrate the relation among a taper angle θ of the p base region 5, a channel length Lch, and the intervals Ld1 and Ld2 of the p base region in the case where an n source region 4 is tapered in the semiconductor device that is manufactured in accordance with Embodiment 1 of the present invention;
FIG. 6 is a diagram to illustrate the relation among a taper angle θ of the p base region 5, a channel length Lch, and the intervals Ld1 and Ld2 of the p base region in the case where the n source region 4 is not tapered in the semiconductor device that is manufactured in accordance with Embodiment 1 of the present invention;
FIG. 7 is a graph showing the relation between the taper angle of the p base region 5 and ON resistance in the case where the n source region 4 is tapered in the semiconductor device that is manufactured in accordance with Embodiment 1 of the present invention;
FIG. 8 is a graph showing the relation between the taper angle of the p base region 5 and ON resistance in the case where the n source region 4 is not tapered in the semiconductor device that is manufactured in accordance with Embodiment 1 of the present invention;
FIG. 9 is a diagram illustrating the taper angle of the p base region 5 and the bounds of punch-through in the semiconductor device that is manufactured in accordance with Embodiment 1 of the present invention;
FIG. 10 is a diagram to illustrate a method of manufacturing a semiconductor device in accordance with Embodiment 2 of the present invention by showing a method of forming a source region 4 and a base region 5 by ion implantation;
FIG. 11 is a diagram showing the relation among the taper angle of a mask, a channel length Lch, and the taper angle of the p base region 5 in the case where the implantation mask has the same range as SiC in the semiconductor device that is manufactured in accordance with Embodiment 2 of the present invention;
FIG. 12 is a diagram showing the relation among the taper angle of the mask, the channel length Lch, and the taper angle of the p base region 5 in the case where the implantation mask is a SiO2 mask in the semiconductor device that is manufactured in accordance with Embodiment 2 of the present invention;
FIG. 13 is a sectional view showing a semiconductor device (SiC vertical MOSFET) manufactured in accordance with Embodiments 3 and 5 of the present invention;
FIG. 14 is a diagram to illustrate a method of manufacturing a semiconductor device in accordance with Embodiment 3 of the present invention by showing a method of forming a source region 4 and a base region 5 by ion implantation;
FIG. 15 is a diagram showing the relation among the ion implantation angle, a channel length Lch, and the taper angle of the p base region 5 in the case where an implantation mask has the same range as SiC in the semiconductor device that is manufactured in accordance with Embodiment 3 of the present invention;
FIG. 16 is a diagram showing the relation among the ion implantation angle, the channel length Lch, and the taper angle of the p base region 5 in the case where the implantation mask is a SiO2 mask in the semiconductor device that is manufactured in accordance with Embodiment 3 of the present invention;
FIG. 17 is a graph showing the relation between the ion implantation angle and ON resistance in the case where the implantation mask has the same range as SiC in the semiconductor device that is manufactured in accordance with Embodiment 3 of the present invention;
FIG. 18 is a graph showing the relation between the ion implantation angle and ON resistance in the case where the implantation mask is a SiO2 mask in the semiconductor device that is manufactured in accordance with Embodiment 3 of the present invention;
FIG. 19 is a sectional view showing a semiconductor device (SiC vertical MOSFET) manufactured in accordance with Embodiments 4 and 6 of the present invention;
FIG. 20 is a diagram to illustrate a method of manufacturing a semiconductor device in accordance with Embodiment 4 of the present invention by showing a method of forming a source region 4 and a base region 5 by ion implantation;
FIG. 21 is a diagram to illustrate a method of manufacturing a semiconductor device in accordance with Embodiment 5 of the present invention by showing a method of forming a source region 4 and a base region 5 by ion implantation; and
FIG. 22 is a diagram to illustrate a method of manufacturing a semiconductor device in accordance with Embodiment 6 of the present invention by showing a method of forming a source region 4 and a base region 5 by ion implantation.
 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
An outline of the present invention is given first. In manufacture of a vertical MOSFET that uses SiC, it is difficult to diffuse an impurity through heat treatment, thus excluding from options a self-alignment process through thermal diffusion of an impurity as the one employed in manufacture of a vertical MOSFET that uses Si. Typically, selective impurity doping is performed by ion implantation.
On the other hand, Si vertical MOSFET's high thermal diffusibility makes it difficult to control the shape (taper angle) of a region formed by ion implantation (ion implantation region) whereas SiC vertical MOSFET's thermal diffusibility that is ignorably low makes it easy to control the shape (taper angle) of an ion implantation region in a depth direction and in a lateral direction.
Conventionally, an implantation mask has vertical side faces for vertical ion implantation with respect to a substrate, and masks different from each other in width have to be used to form a source region and a base region by ion implantation since prior art is incapable of impurity doping by self-alignment process that uses the same mask. After the ion implantation, activation annealing at a temperature of about 1500° C. is needed and it could cause some damage like roughening of a SiC surface.
Accordingly, if a gate electrode serves as the only mask that is used throughout ion implantation, the gate electrode and a gate oxide film are damaged upon the activation annealing. It is therefore difficult to use a gate electrode as an implantation mask.
In view of the above, a vertical MOSFET that uses SiC according to the present invention is characterized by using the same ion implantation mask to form a source region and a base region by ion implantation. The mask is tapered or ions are implanted obliquely, thereby making it possible to manufacture the MOSFET through selective impurity doping in a self-aligning manner. The base region formed by this method is given a tapered shape and accordingly is characterized by its JFET resistance smaller than that of a conventional base region, which has an approximately vertical shape. Specific embodiment modes for carrying out the present invention will be described below.
Embodiment 1
FIG. 1 is a sectional view showing a semiconductor device (SiC vertical MOSFET) manufactured in accordance with Embodiment 1 of the present invention. A source region 4 and a base region 5 are formed by ion implantation in a drift region 6, which is formed through epitaxial growth on a substrate 7. Then a gate oxide film 2, a gate electrode 1, a source electrode 3, and a drain electrode 8 are formed to complete the MOSFET.
An effect of providing the p base region 5 of this semiconductor device with a taper angle θ as shown in FIG. 2 is described. As shown in FIG. 3, ON resistance, which is indicative of the performance of the semiconductor device (vertical MOSFET), is divided into several components: source contact resistance Rcs, n source sheet resistance Rn+, channel resistance Rch, JFET resistance Rj, drift resistance Rd, substrate resistance Rsub, and drain contact resistance Rcd. The channel resistance Rch is currently the largest in a vertical MOSFET that uses SiC, and presents the greatest obstacle to practical application of a SiC vertical MOSFET.
One way to reduce the channel resistance Rch is device miniaturization (in which a MOSFET is reduced in channel length and increased in channel width). In this case, there is a trade-off relation between an interval of the p base region 5 (see FIG. 2, Ld1: an upper interval of the p base region 5, Ld2: a lower interval of the p base region 5) and the JFET resistance Rj, causing Rj to increase while reducing Ld. Providing the p base region 5 with the taper angle θ brings an effect of improving the trade-off relation between the channel resistance Rch and the JFET resistance Rj.
In order to obtain a specific estimation of this effect, an experiment has been conducted in which a MOSFET with the taper angle θ set to 0° is first prepared as a test sample to examine the relation between the interval of the p base region 5 and the JFET resistance Rj. Results thereof are shown in FIG. 4. The test sample is manufactured as a device that is capable of withstanding 1200 V to be used for an in-vehicle or industrial inverter, and employs for the drift region 6 a 10 μm-thick substrate having a carrier concentration of 1×1016 cm−3. The results show that the JFET resistance Rj rapidly increases as the interval Ld (Ld=Ld1=Ld2) of the p base region 5 is reduced.
According to the results shown in FIG. 4, the JFET resistance Rj can be reduced by increasing the interval Ld of the p base region 5. However, this lowers the withstand voltage of the MOSFET. As a result of evaluation made by actually preparing a test sample, it has been found that, when the interval Ld of the p base region 5 is 4 μm or larger, an increased electric field is applied to the gate oxide film 2 and the withstand voltage of the MOSFET becomes lower than a theoretical withstand voltage calculated from a p-n junction.
To summarize the above, the JFET resistance Rj rapidly increases when the interval Ld of the p base region 5 becomes 2 μm or smaller, although the interval Ld of the p base region 5 is desired to be small from the viewpoint of miniaturization, and the withstand voltage of the MOSFET is lowered when the interval Ld of the p base region 5 becomes 4 μm or larger. Accordingly, the optimum value of the interval Ld of the p base region 5 is between 2 μm and 4 μm.
The trade-off relation between the JFET resistance Rj and the channel resistance Rch of the p base region 5 when the p base region 5 has the taper angle θ is examined based on the above results. To elaborate, the relation among the taper angle θ, the JFET resistance rj, and the channel resistance Rch is calculated on the assumption that the device is for use as an in-vehicle or industrial inverter and is capable of withstanding 1200 V.
For simplification, two types of MOSFET structures, one in which the p base region 5 and the n source region 4 have the same taper angle θ and the other in which the p base region 5 has the taper angle θ but not the n source region 4 (θ=0), are considered referring to FIGS. 5 and 6. When the implantation depth of the p base region 5 is given as dp and the implantation depth of the n source region 4 is given as dn, the channel length Lch and the intervals Ld1 and Ld2 of the p base region 5 satisfy the relation as the one shown in FIG. 5 or 6. To elaborate, when the p base region 5 and the n source region 4 have the same taper angle θ, the relation shown in FIG. 5, the channel length Lch=(dp−dn) sin θ, Ld2=Ld1+2dp sin θ, is satisfied and, when the n source region 4 does not have the taper angle θ, the relation shown in FIG. 6, the channel length Lch=dp sin θ, Ld2=Ld1+2dp sin θ, is satisfied.
Here, parameters of the MOSFET, which is assumed to be a device having a withstand voltage of 1200 V for use as an in-vehicle or industrial inverter and which uses as the drift region 6 a 10 μm-thick substrate having a carrier concentration of 1×1016 cm−3, include setting dp to 0.9 μm and dn to 0.3 μm. The interval Ld2 in relation to the taper angle θ is calculated setting Ld1 to 2.5 μm and, assuming that the interval Ld2 determines the JFET resistance Rj, the JFET resistance Rj is obtained from FIG. 4. The channel resistance Rch is 20 mΩ/cm2 when the channel length Lch is 2 μm according to the results of the experimental manufacture carried out by the inventors of the present invention. The channel resistance Rch is expected to be reduced through device miniaturization (in which a MOSFET is reduced in channel length and increased in channel width) and improvement of the process in the future and, for that reason, the channel resistance Rch of the p base region 5 when the channel length Lch is 2 μm is assumed here to be 20, 10, and 5 mΩ/cm2. The channel resistance Rch is calculated from the channel length Lch in relation to the taper angle θ assuming that the channel resistance Rch is in proportion to the channel length Lch.
FIGS. 7 and 8 show results of calculating, by the above method, the relation between the ON resistance (=Rj+Rch) and the taper angle θ when the n source region 4 has the taper angle θ and when the n source region 4 does not. When the taper angle θ is small (60° or less), the channel length Lch is small and accordingly the channel resistance Rch is small except when the taper angle θ is 30° or less, where the lower interval Ld2 of the p base region 5 is reduced to cause a rapid increase in JFET resistance Rj. Therefore, the taper angle θ is desirably 30° to 60° (30° or more and 60° or less), more desirably, 30° to 45° (30° or more and 45° or less).
FIGS. 7 and 8 state that punch-through is avoided when the taper angle θ is 30° or larger. This means that an interval Lp (the minimum value of an interval of the source region 4 and the base region 5) shown in FIG. 9 becomes 0.3 μm or less as the taper angle θ reaches 30° or smaller to cause punch-through and lower the withstand voltage of the MOSFET In the device with a 1200-V withstand voltage which is chosen here as a specific example of the MOSFET, the concentration of the p base region 5 is 5×1017 to 10×1018 cm−3 and the drift region has a concentration of 1×1016 cm−3. A depletion layer when the drain voltage of the MOSFET is 1200 V extends 0.11 to 0.23 μm on the side of the p base region 5. Punch-through is caused as the interval Lp becomes smaller than the depletion layer. There is a strong possibility of punch-through when the interval Lp is 0.3 μm or less taking into account a margin in a device manufacturing process. Therefore, in order to avoid punch-through, the taper angle θ has to be set to 30° or more, so that the interval Lp becomes equal to or more than 0.3 μm.
FIGS. 7 and 8 show only the results of the case when Ld1 is 2.5 μm, but the ON resistance exhibits an identical taper angle dependency throughout the optimum value range of the interval Ld of the p base region 5 (Ld1=2 to 4 μm). When the upper interval Ld1 of the p base region 5 is 2.5 μm or more, the influence of the JFET resistance Rj is small and the taper angle dependency of the ON resistance is approximately identical with the one in FIGS. 7 and 8. When the upper interval Ld1 of the p base region 5 is 2.5 μm or less, the influence of the JFET resistance Rj is large and the absolute value of the ON resistance is larger than in FIGS. 7 and 8 at any taper angle, but still the taper angle dependency of the ON resistance is the same. Therefore, when the Ld1 is 2 to 4 μm, the taper angle θ of the p base region 5 is desirably 30° to 60°, more desirably, 30° to 45°.
According to Embodiment 1, the base region 5 of the vertical MOSFET that uses SiC is tapered to thereby improve the trade-off relation between the channel resistance and the JFET resistance and advance device miniaturization.
Embodiment 2
FIG. 10 is a diagram to illustrate a method of manufacturing a semiconductor device according to Embodiment 2 of the present invention in which the source region 4 and the base region 5 of the semiconductor device (SiC vertical MOSFET) shown in FIG. 1 are formed by ion implantation. If a tapered ion implantation mask 9 as shown in FIG. 10 is used in ion implantation, a taper end portion 10 is implanted with ions even though it is under the implantation mask 9. The width of the region that is implanted with ions despite being under the implantation mask 9 is in proportion to the depth of the ion implantation. Since ions are implanted deeper in the base region 5 than in the source region 4, a region where ions are implanted in the base region 5 alone and not in the source region 4 is created under the mask 9. This region serves as a channel of the MOSFET In addition, the source region 4 and the base region 5 are both tapered, thus obtaining an effect of improving the trade-off relation between the JFET resistance Rj and the channel resistance Rch upon miniaturization as described in Embodiment 1.
The channel length and the taper angle of the base region 5 are determined by the material of the implantation mask 9 and the taper angle θ. Specifically, the relation among the shape of the implantation mask, the channel length Lch, and the taper angle of the base region 5 is examined for a case (a) where the implantation mask 9 is formed from a material that has the same ion implantation range as SiC and for a case (b) where the implantation mask 9 is formed from SiO2, which has been used in the experimental manufacture by the inventors of the present invention (the implantation range of SiO2 is 1.7 times longer than that of SiC). Results thereof are shown in FIGS. 11 and 12. In the case (a) where a material that has the same ion implantation range as SiC is employed for the implantation mask 9, the taper angle θ of the implantation mask 9 matches the taper angle θ of the p base region 5 as shown in FIG. 11. In the case (b) where SiO2 is employed for the implantation mask 9, a taper angle θ′ of the p base region 5 is larger than a taper angle θ of the implantation mask 9 as shown in FIG. 12. This is because the range of SiO2 is 1.7 times the range of SiC, from which is extracted the relation 1.7 tan θ=tan θ′.
As has been described in the preceding Embodiment 1, the taper angle θ of the p base region 5 is desirably 30° to 60°, more desirably, 30° to 45° in the case where a device for use as an in-vehicle or industrial inverter, which has a withstand voltage of 1200 V, is manufactured. Therefore, when a material that has the same ion implantation range as SiC is employed, the taper angle θ of the implantation mask 9 is desirably 30° to 60°, more desirably, 30° to 45° and, when the implantation mask 9 is formed from SiO2, the taper angle θ of the implantation mask 9 is desirably 20° to 45°, more desirably, 20° to 30° from the relation 1.7 tan θ=tan θ′.
A method to process the implantation mask 9 into a desired shape when the implantation mask 9 is formed from SiO2 is dry etching using a resist mask. If the etching selective ratio of SiO2 to the resist is large, SiO2 alone is dry-etched to give vertical side faces to the SiO2 implantation mask. On the other hand, if the etching selective ratio is small, the resist is dry-etched as well as the SiO2 mask to thereby reduce the width of the resist that is used as an etching mask. Through etching under such conditions, the implantation mask made of SiO2 is tapered and its taper angle can be controlled by the selective ratio of SiO2 to the resist.
According to Embodiment 2, a selective impurity doping can be carried out by the above-described method through a self-alignment process that uses the same mask 9. In addition, the channel length of the MOSFET and the taper angle of the p base region 5 can readily be controlled by controlling the shape of the implantation mask 9, and it is advantageous in miniaturization of the MOSFET Furthermore, the trade-off relation between the channel resistance Rch and the JFET resistance Rj can be improved by providing the p base region 5 with a taper angle.
Embodiment 3
FIG. 13 is a sectional view showing a semiconductor device (SiC vertical MOSFET) manufactured in accordance with Embodiment 3 of the present invention. A source region 4 and a base region 5 are formed by ion implantation in a drift region 6, which is formed through epitaxial growth on a substrate 7. Then a gate oxide film 2, a gate electrode 1, a source electrode 3, and a drain electrode 8 are formed to complete the MOSFET.
FIG. 14 is a diagram to illustrate a method of manufacturing a semiconductor device in accordance with Embodiment 3 of the present invention by showing a method of forming the source region 4 and the base region 5 by ion implantation. As shown in FIG. 14, N ions, for example, are implanted vertically with respect to the substrate and at the same time Al ions are implanted obliquely with respect to the substrate at an implantation angle that is smaller than that of N ions. When an implantation mask 11 that has vertical side faces as in prior art is used, a region under the implantation mask 11 is not implanted with N ions and is implanted with Al ions alone. This region serves as a channel of the MOSFET. In addition, if the material of the implantation mask 11 is SiO2 or the like that has a longer ion implantation range than SiC, the base region 5 is tapered to thereby obtain an effect of improving the trade-off relation between the JFET resistance Rj and the channel resistance Rch upon miniaturization as described in Embodiment 1.
The channel length and the taper angle of the base region 5 are determined by the material of the implantation mask 11 and the ion implantation angle. Specifically, the relation among the ion implantation angle, the channel length Lch, and the taper angle of the base region 5 is examined for a case (a) where the implantation mask 11 is formed from a material that has the same ion implantation range as SiC and for a case (b) where the implantation mask 11 is formed from SiO2, which has been used in the experimental manufacture by the inventors of the present invention (the implantation range of SiO2 is 1.7 times longer than that of SiC). Results thereof are shown in FIGS. 15 and 16. In the case (a) where a material that has the same ion implantation range as SiC is employed for the implantation mask 11, the taper angle of the p base region 5 is vertical, matching the shape of the mask as shown in FIG. 15. In the case (b) where SiO2 is employed for the implantation mask 11, the p base region 5 is tapered and its taper angle θ″ is larger than 0° as shown in FIG. 16.
Here, parameters of the MOSFET which is assumed to be a device having a withstand voltage of 1200 V for use as an in-vehicle or industrial inverter and which uses as the drift region 6 a 10 μm-thick substrate having a carrier concentration of 1×1016 cm−3, include setting dp to 0.9 μm and dn to 0.3 μm as in Embodiment 1, and the optimum implantation angle under this setting is examined.
First, the case (a) where the implantation mask 11 is formed from a material that has the same ion implantation range as SiC is considered. The angle of the p base region 5 is not changed by the implantation angle θ and therefore the JFET resistance Rj is not changed. The channel length Lch is calculated in relation to the ion implantation angle θ to obtain the channel resistance Rch. As described in Embodiment 1, the ON resistance (Rj+Rch) obtained in relation to the ion implantation angle θ when the interval Ld1 of the p base region 5 is 2.5 νm is as shown in FIG. 17. Shown here is the case in which Ld1 is 2.5 μm but the ON resistance decreases steadily as the implantation angle θ is increased irrespective of how large the interval Ld1 of the p base region 5 is. In other words, the ON resistance is small when the implantation angle θ is large and the channel length Lch is small. However, as the channel length Lch becomes smaller, punch-through takes place to lower the withstand voltage as described in Embodiment 1. To elaborate, the channel length Lch can be expressed as Lch=dp·cos θ in FIG. 15 and punch-through is caused when Lp=Lch=0.3 μm or less. Taking this into account, the ion implantation angle θ has to be set to 70° or less in order to set the interval Lp to 0.3 μm or more.
To summarize the above, in the case (a) where the implantation mask 11 is formed from a material that has the same ion implantation range as SiC, the optimum ion implantation angle θ is 70° or less and, taking into account the margin, the implantation angle is desirably large around 60° to 70°.
Next, the case (b) where the implantation mask 11 is formed from SiO2 (which has an implantation range 1.7 times longer than that of SiC) is considered. The taper angle θ′ of the p base region 5 and the channel length Lch can be calculated in relation to the ion implantation angle θ. As described in Embodiment 1, the interval Ld2 in relation to the taper angle θ′ is calculated setting Ld1 to 2.5 μm and, assuming that the interval Ld2 determines the JFET resistance Rj, the JFET resistance Rj is obtained from FIG. 4. The channel resistance Rch is similarly calculated from the channel length Lch. Then, the ON resistance (=JFET resistance Rj+channel resistance Rch) obtained in relation to the ion implantation angle θ is as shown in FIG. 18.
Shown here is the case in which Ld1 is 2.5 μm but the tendency of steady decrease of the ON resistance to an increase of the implantation angle θ is maintained as far as Ld1 is 2 to 4 μm. In other words, a large implantation angle θ and a short channel length Lch mean low ON resistance and a small influence on a change of the JFET resistance Rj. As to punch-through, the implantation angle θ has to be 75° or less in order to set Lp to 0.3 μm or more. To elaborate, Lch, θ, and Lp can be expressed as Lch=1.7·dp·cos θ, tan θ=0.7 cot θ′, Lp=Lch·cos θ′−dn·sin θ′, respectively, in FIG. 16 and punch-through is caused when Lp=0.3 μm or less. Taking this into account, the ion implantation angle θ has to be set to 75° or less in order to set the interval Lp to 0.3 μm or more.
To summarize the above, in the case (b) where the implantation mask 11 is formed from SiO2 (which has an implantation range 1.7 times longer than that of SiC), the optimum ion implantation angle θ is 75° or less and, taking into account the margin, the implantation angle is desirably large around 65° to 75°.
In actual ion implantation, the ion implantation angle can be controlled by simply tilting a substrate to match the direction of an implantation mask utilizing orientation flat of the substrate. Although Al is implanted at two different angles on the left and on the right in FIG. 14, it is also possible to implant ions at two or more different angles on each side. The implantation illustrated in FIG. 14 can be achieved by a single implantation operation if the substrate is tilted and rotated upon ion implantation instead of merely tilting the substrate to the left and right.
According to Embodiment 3, a selective impurity doping can be carried out by the above-described method through a self-alignment process that uses the same mask. In particular, the channel length of the MOSFET can readily be controlled by controlling the depth and angle of ion implantation, and it is advantageous in MOSFET miniaturization over prior art in which different masks have to be used for ion implantation. Furthermore, the p base region 5 can be tapered by using for an ion implantation mask a material that has a longer ion implantation range than SiC, and the trade-off relation between the channel resistance Rch and the JFET resistance Rj is thus improved upon device miniaturization.
Embodiment 4
FIG. 19 is a sectional view showing a semiconductor device (SiC vertical MOSFET) manufactured in accordance with Embodiment 4 of the present invention. A source region 4 and a base region 5 are formed by ion implantation in a drift region 6, which is formed through epitaxial growth on a substrate 7. Then a gate oxide film 2, a gate electrode 1, a source electrode 3, and a drain electrode 8 are formed to complete the MOSFET.
FIG. 20 is a diagram to illustrate a method of manufacturing a semiconductor device in accordance with Embodiment 4 of the present invention by showing a method of forming the source region 4 and the base region 5 by ion implantation. As shown in FIG. 20, similar to the above Embodiments 2 and 3, a region where the base region 5 alone is implanted with ions is created under a tapered implantation mask 9 by implanting ions vertically and obliquely with respect to the substrate using the implantation mask 9. This region serves as a channel of the MOSFET. The channel length and the taper angle of the p base region 5 can be controlled by controlling the depth and implantation angle of ion implantation and the shape (taper angle) of the implantation mask.
According to Embodiment 4, a selective impurity doping can be carried out by the above-described method through a self-alignment process that uses the same mask. In particular, Embodiment 4 has more parameters that control the channel length and the taper angle of the p base region 5 than Embodiments 2 and 3, making it possible to facilitate MOSFET miniaturization and improve the trade-off relation between the channel resistance Rch and the JFET resistance Rj.
Embodiment 5
FIG. 21 is a diagram to illustrate a method of manufacturing a semiconductor device according to Embodiment 5 of the present invention in which the source region 4 and the base region 5 of the semiconductor device (SiC vertical MOSFET) shown in FIG. 13 are formed by ion implantation. As shown in FIG. 21, the source region 4 and the base region 5 are each formed by implanting ions obliquely with respect to the substrate. The width of an implanted region under a mask 10 is increased as the implantation angle θ is reduced. Therefore, if the ion implantation angle θ of the base region 5 is set smaller than that of the source region 4, a region where the base region 5 alone is implanted with ions is created under the mask 10. This region serves as a channel of the MOSFET Similar to Embodiment 3, the channel length can be controlled by controlling the depth and implantation angle of ion implantation.
According to Embodiment 5, a selective impurity doping can be carried out by the above-described method through a self-alignment process that uses the same mask. In particular, the channel length of the MOSFET can readily be controlled by controlling the depth and angle of ion implantation, and it is advantageous in MOSFET miniaturization over prior art in which different masks have to be used for ion implantation. Furthermore, the p base region 5 can be tapered by using for an ion implantation mask a material that has a longer ion implantation range than SiC, and the trade-off relation between the channel resistance Rch and the JFET resistance Rj is thus improved upon MOSFET miniaturization.
Embodiment 6
FIG. 22 is a diagram to illustrate a method of manufacturing a semiconductor device according to Embodiment 6 of the present invention in which the source region 4 and the base region 5 of the semiconductor device (SiC vertical MOSFET) shown in FIG. 19 are formed by ion implantation. As shown in FIG. 22, the source region 4 and the base region 5 are each formed by implanting ions obliquely with respect to the substrate using the tapered implantation mask 9. The width of an implanted region under the mask 9 is increased as the implantation angle θ is reduced. Therefore, if the ion implantation angle θ of the p base region 5 is set smaller than that of the source region 4, a region where the base region 5 alone is implanted with ions is created under the mask 9. This region serves as a channel of the MOSFET Combined with the effect of an implantation mask being tapered, the channel length and the taper angle of the p base region 5 can be controlled by controlling the depth and implantation angle of ion implantation and the shape (taper angle) of the implantation mask.
According to Embodiment 6, a selective impurity doping can be carried out by the above-described method through a self-alignment process that uses the same mask. In particular, Embodiment 6 has more parameters that control the channel length and the taper angle of the p base region 5 than Embodiments 2 and 3, making it possible to facilitate MOSFET miniaturization. Moreover, the trade-off relation between the channel resistance Rch and the JFET resistance Rj can be improved by providing the p base region 5 with a taper angle.

Claims (4)

1. A method of manufacturing a silicon carbide (SiC) vertical MOSFET, the method comprising:
forming an SiC mask on a surface of a layer of SiC, the SiC mask having side surfaces substantially parallel to a normal to the surface of the layer of SiC;
implanting first ions into the layer of SiC through the surface in a direction forming an angle not larger than 70° with the surface, using the SiC mask as an ion implantation mask, to produce a base region having a first conductivity type in the layer of SiC; and
implanting second ions into the layer of SiC through the surface in a direction substantially parallel to the normal, using the SiC mask as an ion implantation mask to produce a source region having a second conductivity type, opposite the first conductivity type, within the base region, so that channel length of the base region, measured along the surface, is at least 0.3 microns.
2. The method according to claim 1 including simultaneously implanting the first ions and the second ions.
3. A method of manufacturing a silicon carbide (SiC) vertical MOSFET, the method comprising:
forming an SiO2 mask on a surface of a layer of SiC, the SiO2 mask having side surfaces forming substantially parallel to a normal to the surface of the layer of SiC;
implanting first ions into the layer of SiC through the surface in a direction forming an angle not larger than 75° with the surface, using the SiO2 mask as an ion implantation mask, to produce a base region having a first conductivity type in the layer of SiC; and
implanting second ions into the layer of SiC through the surface in a direction substantially parallel to the normal, using the SiO2 mask as an ion implantation mask to produce a source region having a second conductivity type, opposite the first conductivity type, within the base region, so that the base region has a thickness, relative to the source region, of at least 0.3 microns.
4. The method according to claim 3 including simultaneously implanting the first ions and the second ions.
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