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WO1991011827A1 - Passivated silicon substrate - Google Patents

Passivated silicon substrate Download PDF

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Publication number
WO1991011827A1
WO1991011827A1 PCT/US1991/000392 US9100392W WO9111827A1 WO 1991011827 A1 WO1991011827 A1 WO 1991011827A1 US 9100392 W US9100392 W US 9100392W WO 9111827 A1 WO9111827 A1 WO 9111827A1
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WO
WIPO (PCT)
Prior art keywords
silicon
layer
silicon dioxide
dioxide layer
hydrazine
Prior art date
Application number
PCT/US1991/000392
Other languages
French (fr)
Inventor
Marc J. Madou
Original Assignee
Commtech International
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Filing date
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Publication of WO1991011827A1 publication Critical patent/WO1991011827A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
    • H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

Definitions

  • the present invention relates to a silicon chip which has been passivated in a manner which renders it highly resistive to degradation in the presence of high humidity and/or liquid water.
  • the process is useful in preparing silicon chips for semiconductor processing applications and for producing icroelectrochemical cells on or below the surface of silicon chips.
  • Such insulation layers can comprise silicon dioxide, silicon nitride or silicon oxynitride.
  • silicon dioxide silicon dioxide
  • silicon nitride silicon oxynitride.
  • one or the other of these layers is used although there are instances, set forth, for example, in U.S. Patent 4,062,040, issued December 6, 1977 to S.A. Abbas and R.C. Dockerty, wherein one of these dielectric layers (in. the specific instance mentioned a silicon nitride layer) is deposited over another of these layers (in the instance mentioned a silicon dioxide layer) .
  • the silicon dioxide layer is produced, as is conventionally done, by reaction of the silicon chip with dry oxygen at a temperature of, for example, 800#C, and that the silicon nitride layer is made conventionally, for example by reaction of ammonia and silane or of ammonia and tetrachlorosilane, the thicknesses of each layer can be controlled as is needed for the particular device being formulated.
  • xx. is also known to provide a silicon oxynitride layer, for example by annealing silicon nitride in an oxygen atmosphere, or by annealing silicon dioxide in an ammonia atmosphere, both at elevated temperature.
  • Silicon nitride layers made as discussed above are generally relatively permeable to vaporous water and liquid water (generally due to the existence of small holes) which can pass through such layers and damage the circuitry lying beneath them.
  • the silicon dioxide layers themselves are relatively permeable to water (again generally due to the existence of small holes) which can pass through such layers thereby damaging the device of which they form a part.
  • the present invention is directed to overcoming one or more of the problems as set forth above.
  • a passivated silicon substrate is set forth in accordance with an embodiment of the invention.
  • the passivated substrate comprises a silicon substrate having a surface region on which a passivation coating is required.
  • a silicon dioxide layer covers the surface region, the silicon dioxide layer being no more than about 1,000 Angstroms thick.
  • a silicon oxynitride layer covers the silicon dioxide layer, the silicon oxynitride layer being no more than about 300 Angstroms thick and having been produced by reaction of ammonia, hydrazine or methyl amine with an initially thicker silicon dioxide layer.
  • a silicon nitride layer covers the silicon oxynitride layer.
  • the silicon nitride layer is at least about 250
  • Angstroms thick and is produced by chemical vapor deposition.
  • a method is set forth of passivating a silicon substrate.
  • the method comprises providing a silicon dioxide layer of a desired initial thickness on the surface of the substrate whereat a passivation covering is desired .
  • the silicon dioxide layer is reacted with ammonia, hydrazine or methyl amine to form a silicon oxynitride layer over the silicon dioxide layer.
  • the silicon dioxide layer after the reacting, is from about 10 to about 1,000 Angstroms in thickness.
  • the resulting silicon oxynitride layer is from about 10 to about 300 Angstroms in thickness.
  • a silicon nitride layer at least about 250 Angstroms in thickness is chemically vapor deposited over the silicon oxynitride layer.
  • a passivated silicon substrate in accordance with the present invention has a unique advantage of being substantially moisture impermeable because of the presence of the intermediate silicon oxynitride layer.
  • silicon substrates can be utilized in highly moist environments for long periods of time without deterioration due to the moisture.
  • the thickness of the silicon dioxide layer and the thickness of the silicon nitride layer can be controlled as desired by the device fabricator so as to be appropriate for whatever device is being fabricated.
  • Such a passivation technique is particularly useful in those situations wherein a silicon substrate is to be directly exposed to water containing solutions (liquids). Such can be the case if the device is a microelectrochemical cell which lies upon, or in a well leading into the surface of, a silicon wafer or chip.
  • Figure 1 illustrates, in cross-sectional view, a silicon substrate passivated in accordance with the present invention
  • Figure 2 illustrates, in cross-sectional view, a microchemical sensor passivated in accordance with an embodiment of the present invention.
  • the passivated silicon substrate structure 10 includes a silicon substrate 12 having a surface region 14 on which a passivation coating 16 is required.
  • a silicon dioxide layer 18 covers the surface region 14.
  • the silicon dioxide layer 18 is generally no more than about 1,000 Angstroms thick, and is preferably in the range from about 50 Angstroms thick to about 300 Angstroms thick.
  • a silicon oxynitride layer 20 covers the silicon dioxide layer 18.
  • the silicon oxynitride layer is generally at least about 10 Angstroms thick and is no more than about 300 Angstroms thick. It is produced by reaction of ammonia, hydrazine or methyl amine, preferably ammonia, with an initially thicker silicon dioxide layer 18.
  • the reaction with the ammonia is carried out by flowing very pure ammonia over the silicon dioxide layer 18 at a temperature which falls within a range from about 1,000#C to about 1,400#C. Suitably, the temperature can be about 1,350#C.
  • the ammonia is generally flowed over the wafer at about atmospheric pressure but pressure and flow rate are not critical. Other reactive chemicals which might interfere with the reaction must be excluded during the reaction with ammonia. However, chemically inert gases such as nitrogen, argon, helium and the like can be present. Hydrazine or methyl amine may substitute for the ammonia. Mixtures of two or more such compounds can also be used.
  • a silicon nitride layer 22 covers the silicon oxynitride layer 20, the silicon nitride layer 22 being at least about 250 Angstroms, preferably at least about 500 Angstroms thick and having been produced by chemical vapor deposition.
  • chemical vapor deposition can be carried out in any of the ways known in the art.
  • silicon nitride deposition may be affected at temperatures which' fall within the range from about 600#C to about 1, 100#C in accordance with reactions such as the following:
  • Hydrazine or methyl amine can substitute for the ammonia. Mixtures of all or any two such chemicals can also be utilized. However, ammonia is the preferred chemical for this purpose.
  • the silicon dioxide layer 18 can be made by conventional procedures, for example by reacting dry oxygen with underlying silicon substrate 12, for example at a temperature which falls within a range from about 600#C to about 1,000#C.
  • silicon dioxide can be deposited from silane or silicon tetrachloride in accordance with the following reactions at temperatures which fall within a range from about 800#C to about 1,100#C:
  • silicon dioxide can be deposited from silane oxidation at a temperature in the range from about 300#C to about 500#C according to the equation:
  • Figure 2 illustrates an embodiment wherein the technique has been utilized to passivate the surface of an electrochemical cell having a well 24 which includes an electrode 26 and is filled with a water containing electrolytic medium 28.
  • the electrolytic medium can be a liquid solution, a gel, or a solid polymer electrolyte which includes a significant portion of water.
  • a conductor 30 fills a passivated passage 32 -and comes from a backside 34 of the silicon substrate 12 to the electrode 26. The passivation also serves to insulate the conductor 30 from the substrate 12 " .
  • the present invention provides a passivated silicon substrate 10 useful in the semiconductor industry, particularly for the making of integrated circuits, transistors and the like. It is also useful for the manufacture of microelectrochemical cells and half cells.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

A passivated silicon substrate structure (10) is set forth. A silicon substrate has a surface region (14) covered by a silicon dioxide layer (18) no more than about 1,000 Angstroms thick. A silicon oxynitride layer (20) of no more than about 300 Angstroms thick covers the silicon dioxide layer. The silicon oxynitride layer is produced by reaction of ammonia, hydrazine or methyl amine with an initially thicker silicon dioxide layer. A silicon nitride layer (22) covers the silicon oxynitride layer. The silicon nitride layer is at least about 250 Angstroms thick. It is produced by chemical vapor deposition. A passivation layer as set forth above provides electric insulation and is highly resistant to moisture attack.

Description

Description
PASSIVATED SILICON SUBSTRATE
Technical Field
The present invention relates to a silicon chip which has been passivated in a manner which renders it highly resistive to degradation in the presence of high humidity and/or liquid water. The process is useful in preparing silicon chips for semiconductor processing applications and for producing icroelectrochemical cells on or below the surface of silicon chips.
Background Of The Invention
It is customary in the silicon wafer processing art to provide an insulation layer for an underlying silicon wafer. Such insulation layers can comprise silicon dioxide, silicon nitride or silicon oxynitride. Generally one or the other of these layers is used although there are instances, set forth, for example, in U.S. Patent 4,062,040, issued December 6, 1977 to S.A. Abbas and R.C. Dockerty, wherein one of these dielectric layers (in. the specific instance mentioned a silicon nitride layer) is deposited over another of these layers (in the instance mentioned a silicon dioxide layer) .
If the silicon dioxide layer is produced, as is conventionally done, by reaction of the silicon chip with dry oxygen at a temperature of, for example, 800#C, and that the silicon nitride layer is made conventionally, for example by reaction of ammonia and silane or of ammonia and tetrachlorosilane, the thicknesses of each layer can be controlled as is needed for the particular device being formulated. xx. is also known to provide a silicon oxynitride layer, for example by annealing silicon nitride in an oxygen atmosphere, or by annealing silicon dioxide in an ammonia atmosphere, both at elevated temperature. What results is a thin layer of silicon oxynitride in the first instance below a silicon dioxide layer and in the second instance above a silicon dioxide layer. Such layers of silicon oxynitride are invariably very thin due to the method of their formation. Accordingly, their use is limited to those cases wherein one desires to have a very thin dielectric layer.
Silicon nitride layers made as discussed above are generally relatively permeable to vaporous water and liquid water (generally due to the existence of small holes) which can pass through such layers and damage the circuitry lying beneath them. The silicon dioxide layers themselves are relatively permeable to water (again generally due to the existence of small holes) which can pass through such layers thereby damaging the device of which they form a part. Thus, there is a very real and serious problem which the prior art has not solved which relates to protecting or passivating a silicon substrate in such a manner that resulting device can be utilized in a highly humid or even liquid environment for long periods of time without appreciable damage.
The present invention is directed to overcoming one or more of the problems as set forth above.
Disclosure Of Invention
A passivated silicon substrate is set forth in accordance with an embodiment of the invention. The passivated substrate comprises a silicon substrate having a surface region on which a passivation coating is required. A silicon dioxide layer covers the surface region, the silicon dioxide layer being no more than about 1,000 Angstroms thick. A silicon oxynitride layer covers the silicon dioxide layer, the silicon oxynitride layer being no more than about 300 Angstroms thick and having been produced by reaction of ammonia, hydrazine or methyl amine with an initially thicker silicon dioxide layer. A silicon nitride layer covers the silicon oxynitride layer. The silicon nitride layer is at least about 250
Angstroms thick and is produced by chemical vapor deposition.
In accordance with another embodiment of the present invention a method is set forth of passivating a silicon substrate. The method comprises providing a silicon dioxide layer of a desired initial thickness on the surface of the substrate whereat a passivation covering is desired . The silicon dioxide layer is reacted with ammonia, hydrazine or methyl amine to form a silicon oxynitride layer over the silicon dioxide layer. The silicon dioxide layer, after the reacting, is from about 10 to about 1,000 Angstroms in thickness. The resulting silicon oxynitride layer is from about 10 to about 300 Angstroms in thickness. A silicon nitride layer at least about 250 Angstroms in thickness is chemically vapor deposited over the silicon oxynitride layer.
A passivated silicon substrate in accordance with the present invention has a unique advantage of being substantially moisture impermeable because of the presence of the intermediate silicon oxynitride layer. Thus, such silicon substrates can be utilized in highly moist environments for long periods of time without deterioration due to the moisture. At the same rime, the thickness of the silicon dioxide layer and the thickness of the silicon nitride layer can be controlled as desired by the device fabricator so as to be appropriate for whatever device is being fabricated. Such a passivation technique is particularly useful in those situations wherein a silicon substrate is to be directly exposed to water containing solutions (liquids). Such can be the case if the device is a microelectrochemical cell which lies upon, or in a well leading into the surface of, a silicon wafer or chip.
Brief Description Of The Drawings
The present invention will be better understood by reference to the figures of the drawings wherein like numbers denote like parts throughout and wherein:
Figure 1 illustrates, in cross-sectional view, a silicon substrate passivated in accordance with the present invention; and Figure 2 illustrates, in cross-sectional view, a microchemical sensor passivated in accordance with an embodiment of the present invention.
Best Mode For Carrying Out Invention
Adverting to Figure.1 there is illustrated a passivated silicon substrate structure 10 in accordance with an embodiment of the present invention. The passivated silicon substrate structure 10 includes a silicon substrate 12 having a surface region 14 on which a passivation coating 16 is required.
A silicon dioxide layer 18 covers the surface region 14. The silicon dioxide layer 18 is generally no more than about 1,000 Angstroms thick, and is preferably in the range from about 50 Angstroms thick to about 300 Angstroms thick.
A silicon oxynitride layer 20 covers the silicon dioxide layer 18. The silicon oxynitride layer is generally at least about 10 Angstroms thick and is no more than about 300 Angstroms thick. It is produced by reaction of ammonia, hydrazine or methyl amine, preferably ammonia, with an initially thicker silicon dioxide layer 18. The reaction with the ammonia is carried out by flowing very pure ammonia over the silicon dioxide layer 18 at a temperature which falls within a range from about 1,000#C to about 1,400#C. Suitably, the temperature can be about 1,350#C. The ammonia is generally flowed over the wafer at about atmospheric pressure but pressure and flow rate are not critical. Other reactive chemicals which might interfere with the reaction must be excluded during the reaction with ammonia. However, chemically inert gases such as nitrogen, argon, helium and the like can be present. Hydrazine or methyl amine may substitute for the ammonia. Mixtures of two or more such compounds can also be used.
A silicon nitride layer 22 covers the silicon oxynitride layer 20, the silicon nitride layer 22 being at least about 250 Angstroms, preferably at least about 500 Angstroms thick and having been produced by chemical vapor deposition. Such chemical vapor deposition can be carried out in any of the ways known in the art. For example, silicon nitride deposition may be affected at temperatures which' fall within the range from about 600#C to about 1, 100#C in accordance with reactions such as the following:
3SiH4 + 4NH3 & Si3N4 + 12H2
3SiCl4 + 4NH3 & Si3N4 + 12HC1
Hydrazine or methyl amine can substitute for the ammonia. Mixtures of all or any two such chemicals can also be utilized. However, ammonia is the preferred chemical for this purpose.
The silicon dioxide layer 18 can be made by conventional procedures, for example by reacting dry oxygen with underlying silicon substrate 12, for example at a temperature which falls within a range from about 600#C to about 1,000#C. Alternatively, silicon dioxide can be deposited from silane or silicon tetrachloride in accordance with the following reactions at temperatures which fall within a range from about 800#C to about 1,100#C:
SiH4 + H2 + 2C02 & Si02 + 3H2CO SiCl4 + 2H2 + 2C02 & Si02 + 4HC1 + 2C0 Alternatively, silicon dioxide can be deposited from silane oxidation at a temperature in the range from about 300#C to about 500#C according to the equation:
SiH4 + 02 & Si02 + 2H2
Figure 2 illustrates an embodiment wherein the technique has been utilized to passivate the surface of an electrochemical cell having a well 24 which includes an electrode 26 and is filled with a water containing electrolytic medium 28. For example, the electrolytic medium can be a liquid solution, a gel, or a solid polymer electrolyte which includes a significant portion of water. A conductor 30 fills a passivated passage 32 -and comes from a backside 34 of the silicon substrate 12 to the electrode 26. The passivation also serves to insulate the conductor 30 from the substrate 12".
Industrial Applicability
The present invention provides a passivated silicon substrate 10 useful in the semiconductor industry, particularly for the making of integrated circuits, transistors and the like. It is also useful for the manufacture of microelectrochemical cells and half cells.
While the invention has been described in connection with specific embodiments thereof, it will be understood that it is capable of further modification, and this application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice in the art to which the invention pertains and as may be applied to the essential features hereinbefore set forth, and as fall within the scope of the invention and the limits of the appended claims.

Claims

ClaimsThat Which Is Claimed Is:
1. A passivated silicon substrate, comprising: a silicon substrate having a surface region on which a passivation coating is required; a silicon dioxide layer covering said surface region, said silicon dioxide layer being no more than about 1,000 Angstroms thick; a silicon oxynitride layer covering said silicon dioxide layer, said silicon oxynitride layer being no more than about 300 Angstroms thick and having being produced by reaction of NH3 , methyl amine with an initially thicker silicon dioxide layer; and a silicon nitride layer covering said silicon oxynitride layer, said silicon nitride layer being at least about 250 Angstroms thick and having been produced by chemical vapor deposition.
2. A passivated substrate as set forth in claim 1, wherein said chemical vapor deposition is carried out by contacting ammonia, hydrazine or methyl amine and SiH4 or SiCl4 with said silicon oxynitride layer at a temperature which falls within a range from about 600#C to about 1,100#C.
3. A passivated substrate as set forth in claim 2, wherein said reaction with NH3, hydrazine or methyl amine is carried out by contacting said ammonia, hydrazine or methyl amine with an initially thicker silicon dioxide layer at a temperature which falls within a range from about 1,000# to about 1,400#.
4. A passivated substrate as set forth in claim 1, wherein said reaction with NH_ , hydrazine or methyl amine is carried out by contacting said . ammonia, hydrazine or methyl amine with an initially thicker silicon dioxide layer at a temperature which falls within a range from about 1,000# to about 1,400*.
5. A method of passivating a silicon substrate, comprising: providing a silicon dioxide layer of a desired initial thickness on the surface of the substrate whereat a passivation covering is required; reacting the silicon dioxide layer with NH3, hydrazine or methyl a ineto form a silicon oxynitride layer over said silicon dioxide layer, the silicon dioxide layer after said reacting being from about 50 Angstroms to about 1,000 Angstroms in thickness and the resulting silicon oxynitride layer being from about 10 Angstroms to about 300 Angstroms in thickness; chemically vapor depositing a silicon nitride layer at least about 250 Angstroms in thickness over said silicon oxynitride layer.
6. A method as set forth in claim 5, wherein said chemical vapor deposition is carried out by contacting ammonia, hydrazine or methyl amine and SiH4 or SiCl4 with said silicon oxynitride layer at a temperature which falls within a range from about 600#C to about 1,100#C.
7. A method as set forth in claim 6, wherein said reaction with NH_ is carried out by contacting said ammonia, hydrazine or methyl amine with an initially thicker silicon dioxide layer at a temperature which falls within a range from about 1,000# to about 1,400#.
8. A method as set forth in claim 5, wherein said reaction with NH, is carried out by contacting said ammonia, hydrazine or methyl amine with an initially thicker silicon dioxide layer at a temperature which falls within a range from about 1,000# to about 1,400#.
PCT/US1991/000392 1990-01-29 1991-01-22 Passivated silicon substrate WO1991011827A1 (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5304840A (en) * 1992-07-24 1994-04-19 Trw Inc. Cryogenic radiation-hard dual-layer field oxide for field-effect transistors
US5608252A (en) * 1993-03-10 1997-03-04 Sharp Microelectronics Technology, Inc. Semiconductor with implanted dielectric layer having patched pin-holes
US6011308A (en) * 1996-06-14 2000-01-04 Nec Corporation Semiconductor device having a barrier film formed to prevent the entry of moisture and method of manufacturing the same
WO2000004581A1 (en) * 1998-07-17 2000-01-27 Infineon Technologies Ag Passivation layer for power semiconductors with pn junctions appearing on the surface
US20230369070A1 (en) * 2022-05-12 2023-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package structure and method of manufacturing thereof

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