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WO1992008231A1 - Systeme de raccordement de memoire morte - Google Patents

Systeme de raccordement de memoire morte Download PDF

Info

Publication number
WO1992008231A1
WO1992008231A1 PCT/US1991/008098 US9108098W WO9208231A1 WO 1992008231 A1 WO1992008231 A1 WO 1992008231A1 US 9108098 W US9108098 W US 9108098W WO 9208231 A1 WO9208231 A1 WO 9208231A1
Authority
WO
WIPO (PCT)
Prior art keywords
rom
address
data
pins
select
Prior art date
Application number
PCT/US1991/008098
Other languages
English (en)
Inventor
Yao T. Yen
Original Assignee
Transcomputer, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Transcomputer, Inc. filed Critical Transcomputer, Inc.
Publication of WO1992008231A1 publication Critical patent/WO1992008231A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/65—Updates
    • G06F8/66—Updates of program code stored in read-only memory [ROM]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards

Definitions

  • the present invention relates to an apparatus for use in conjunction with an existing ROM which contains original information stored as binary bits.
  • the information provided by the apparatus is different from the original information even though the original information stored in the ROM is not altered.
  • ROM read ⁇ only-memory
  • PROM programmable-read-only- memories
  • EPROM electrically-programmable-read ⁇ only-memories
  • PROMs and EPROMs are merely subclasses of ROMs, insofar as this invention are concerned, we will only refer to ROMs. It will be understood that a reference to a ROM also refers to PROMs, EPROMs, EAROMs and EEPROMs.
  • ROMs or systems containing ROMs are sold where the ROM (or PROM or EPROM) contains the vendor's copyrighted software or data.
  • ROM or PROM or EPROM
  • a common example of such a system is a personal computer (PC) containing a basic input/output system (BIOS) ROM which contains program code that handles microprocessor-to-peripheral communications for the PC.
  • BIOS basic input/output system
  • VAR value added reseller
  • the end user is limited to the BIOS code provided by the PC vendor or to developing an entirely new code in a so called clean room.
  • a device is needed to allow a user to develop and implement enhancements to software or data stored in a ROM, PROM or EPROM without infringing a copyright in the original data or software.
  • a device for enhancing the program code of a first ROM is presented.
  • An original ROM is connected to address and data busses in parallel with a patch ROM.
  • the original ROM contains a given set of code or data, while the patch ROM contains replacement code or data, such as enhancements to the code.
  • a select ROM has inputs connected to the address bus and outputs connected to the chip select input pins of the original and patch ROMs. When the ROMs are addressed, the select ROM selects either the original ROM or the patch ROM, depending upon the address.
  • the select ROM controls the data bus by enabling the appropriate chip select pins of the original and patch ROMs.
  • the patch and select ROM's are contained in a single module, which plugs into the socket provided for the original ROM. The original ROM is then plugged into the module to complete the interconnections among the ROMs.
  • Figure 1 is a block diagram of a ROM and socket module according to the prior art.
  • Figure 2 is a block diagram of a Rom patch device according to the present invention.
  • Figure 3 is a side elevation view of the prior art.
  • Figure 4 is a side elevation view of a ROM patch module according to the present invention.
  • Figure 5 is a bottom view of the ROM patch module of Figure 4.
  • a ROM contains program code stored to be retrievable by a series of binary address locations.
  • a typical ROM 10 such as an Intel 2764 EPROM, has an address bus 12 for selecting an appropriate memory location, a data bus for providing the information stored in the selected memory location and a chip select pin 16 to activate the ROM so that the information stored in the selected memory location becomes available external to the ROM. In the absence of the appropriate logic signal on the chip select line 16, the lines of the data bus remain floating.
  • a typical function of a ROM 10 in a PC is to control the Basic Input/Output System (BIOS) , so that the ROM 10 contains instructions to enable the microprocessor to communicate with peripheral equipment such as printers, displays, memory controllers and the like.
  • BIOS Basic Input/Output System
  • program instructions beginning at the address on the address bus 12 are presented on the data bus 14.
  • the ROM patch device of the present invention enables the user to enhance or alter the instructions provided by an original ROM without altering the instructions which are stored in the original ROM 10, and thus, without infringing the copyright on the BIOS code.
  • the address bus 12 is tied to the input and the data bus 14 is tied to the output of the ROM 10.
  • ROM 20 and the patch ROM 22 are connected in parallel to the ROM 10 with respect to the address bus 12; i.e., the address bus 12 is coupled to the input of both the select ROM 20 and the patch ROM 22. However, only the output of the patch ROM 22 is coupled in parallel to the original ROM 10 with respect to the data bus 14.
  • ROM 20 and ROM 22 may be user programmable EPROMs.
  • the contents of the ROM 20 and the ROM 22 contained in device 54 may be initially blank.
  • a user may plug device 54 into a commercially available PROM programming equipment, and program each of ROM 20 and ROM 22 sequentially.
  • the chip selects 18 and 19 are brought to the external pins Jl and J2, as shown in Figure 2.
  • the external pins Jl and J2 may be connected by an external cable to the PROM programming equipment. By controlling the signals applied to the external pins Jl and J2, the address bus 12 and the data bus 14 available at the socket pins 60, the contents of the ROMs 20 and 22 can be programmed to suit a particular user application.
  • ROMs have eight lines in the data bus to provide a byte of binary data for each location addressed. Only two of the output lines of the of the select ROM 20 are used for the present invention: a first output line is coupled as the chip select 18 of the original ROM 10 and a second output line is coupled as the chip select 19 of the patch ROM 22. Further, the chip select 16 for selecting the original ROM 10 before the ROM patch device is used, is now coupled to enable the select ROM 20. Thus, whenever a host system would have accessed data or code from the original ROM 10, it will now access data or code from either the original ROM 10 or the patch ROM 22 under control of the select ROM 20.
  • every address location having a corresponding valid address in the original ROM 10 has information stored in the select ROM 20.
  • the data site that supplies a binary bit as the chip select 18 to the original ROM 10 will contain the opposite binary condition as the data site that supplies a binary bit as the chip select 19 to the patch ROM 22 so that only one or the other of the original ROM 10 or the patch ROM 22 can drive the data bus 14.
  • the select ROM is coded so that either the original ROM or the patch ROM are enabled but not both.
  • the ROM 22 contains alternative or substitute instructions that are programmed by the user.
  • Table I contains a series of sample instructions for the original ROM 10, the select ROM 20 and the patch ROM 22.
  • the original ROM 10 contains fifteen original instructions A - O.
  • the user wants to modify the software by substituting the alternate instruction F and alternate instruction J for the original instructions F and J stored in address 6 and 10, respectively.
  • the select ROM has eight outputs because that is the type of device commercially available.
  • the first output is used to drive the original ROM's chip select and the second output is used to drive the patch ROM's chip select.
  • the condition of the first and second outputs for the select ROM are opposite.
  • the first output is a binary "1" and the second output is a binary "0" to select the original ROM.
  • the binary conditions are reversed to select the patch ROM.
  • the remaining six outputs do not matter to this invention and are indicated by an "x" for a "don't care" condition.
  • the original ROM 10 contains a BIOS program it is packaged in a dual-in-line (DIP) package and mounted in a socket 50 on a PC mother board 52 as shown in Figure 3 rather than being soldered.
  • the original ROM 10 is removed from the socket 50 and is inserted into a socket 58 on a ROM patch device 54.
  • the ROM patch device 54 includes a printed circuit board 56 on which the select ROM 20 and the patch ROM 22 are mounted.
  • the select ROM 20 and the patch ROM 22 are packaged in leadless chip carrier (LCC) packages. Thus, they are sufficiently small to fit within the boundaries of the pins 60 on the printed circuit board 56 as shown in Figure 5.
  • LCC leadless chip carrier
  • the printed circuit board 56 includes the appropriate interconnection traces to electrically couple the socket 58 for the original ROM 10, the select ROM 20 and the patch ROM 22 to one another and to the appropriate pins 60.
  • the ROM patch device 54 is inserted into the socket 50 on the PC mother board 52 by the pins 62. Thus, the ROM patch device 54 does not require any additional space on the mother board 52. In such a design, ROM patch device 54 has length and width substantially identical to ROM 10, but the height is slightly increased. Ordinarily, this will not be a problem.

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)

Abstract

Système permettant d'améliorer le code de pogrammation d'une première mémoire morte, comprenant une mémoire morte d'origine (10) connectée à des bus d'adresses et de données (respectivement 12 et 14) en parallèle avec une mémoire morte de raccordement (22). La mémoire morte d'origine (10) renferme un ensemble donné de codes ou de données, alors que la mémoire morte de raccordement (22) contient des données ou un code de remplacement, tels que des améliorations pour le code. Une mémoire morte de sélection (20) comporte des entrées connectées au bus d'adresses (12) et des sorties (18 et 19) connectées aux broches d'entrée de sélection de circuit des mémoires mortes d'origine et de raccordement (respectivement 10 et 22). Lorsqu'on accède aux mémoires mortes, la mémoire morte de sélection choisit la mémoire morte d'origine (10) ou la mémoire morte de raccordement (22), en fonction de l'adresse. La mémoire morte de sélection (20) commande le bus de données en activant les broches appropriées de sélection de circuit des mémoires mortes d'origine et de raccordement (respectivement 10 et 22).
PCT/US1991/008098 1990-11-02 1991-11-01 Systeme de raccordement de memoire morte WO1992008231A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US60830290A 1990-11-02 1990-11-02
US608,302 1990-11-02

Publications (1)

Publication Number Publication Date
WO1992008231A1 true WO1992008231A1 (fr) 1992-05-14

Family

ID=24435892

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1991/008098 WO1992008231A1 (fr) 1990-11-02 1991-11-01 Systeme de raccordement de memoire morte

Country Status (1)

Country Link
WO (1) WO1992008231A1 (fr)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997017656A1 (fr) * 1995-11-07 1997-05-15 Advanced Micro Devices, Inc. Appareil et procede de correction de microcode
GB2309324A (en) * 1996-01-17 1997-07-23 Motorola Inc Method for storing repair data in a microprocessor
EP0889405A1 (fr) * 1997-06-19 1999-01-07 Nec Corporation Méthode de débogage de logiciel
WO2000038081A1 (fr) * 1998-12-21 2000-06-29 Infineon Technologies Ag Unite commandee par programme a memoires internes et externes
EP1244007A2 (fr) 2001-03-21 2002-09-25 Broadcom Corporation Correction dynamique de microcode
GB2384582A (en) * 2002-01-28 2003-07-30 Ericsson Telefon Ab L M Software correction
WO2005036486A1 (fr) * 2003-10-10 2005-04-21 Giesecke & Devrient Gmbh Acces a des elements de donnees dans un support de donnees portable
EP1646052A1 (fr) * 2004-10-07 2006-04-12 Infineon Technologies AG Circuit mémoire incorporant un remplacement flexible de cellules mémoire défectueuses relatif aux arrangements en forme de lignes de bit ou de lignes de mot
US7243206B2 (en) * 2003-04-14 2007-07-10 Arm Limited Method and apparatus for using a RAM memory block to remap ROM access requests
US20110055821A1 (en) * 2009-08-31 2011-03-03 Sony Computer Entertainment Inc. Information Processing Apparatus

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4319343A (en) * 1980-07-16 1982-03-09 Honeywell Inc. Programmable digital memory circuit
US4490812A (en) * 1982-09-30 1984-12-25 Mostek Corporation User reprogrammable programmed logic array
US4610000A (en) * 1984-10-23 1986-09-02 Thomson Components-Mostek Corporation ROM/RAM/ROM patch memory circuit
US4609985A (en) * 1982-12-30 1986-09-02 Thomson Components-Mostek Corporation Microcomputer with severable ROM
US4785425A (en) * 1987-02-27 1988-11-15 Emhart Industries, Inc. Electronic locking system
US4884237A (en) * 1984-03-28 1989-11-28 International Business Machines Corporation Stacked double density memory module using industry standard memory chips

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4319343A (en) * 1980-07-16 1982-03-09 Honeywell Inc. Programmable digital memory circuit
US4490812A (en) * 1982-09-30 1984-12-25 Mostek Corporation User reprogrammable programmed logic array
US4609985A (en) * 1982-12-30 1986-09-02 Thomson Components-Mostek Corporation Microcomputer with severable ROM
US4884237A (en) * 1984-03-28 1989-11-28 International Business Machines Corporation Stacked double density memory module using industry standard memory chips
US4610000A (en) * 1984-10-23 1986-09-02 Thomson Components-Mostek Corporation ROM/RAM/ROM patch memory circuit
US4785425A (en) * 1987-02-27 1988-11-15 Emhart Industries, Inc. Electronic locking system

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5796974A (en) * 1995-11-07 1998-08-18 Advanced Micro Devices, Inc. Microcode patching apparatus and method
WO1997017656A1 (fr) * 1995-11-07 1997-05-15 Advanced Micro Devices, Inc. Appareil et procede de correction de microcode
GB2309324A (en) * 1996-01-17 1997-07-23 Motorola Inc Method for storing repair data in a microprocessor
GB2309324B (en) * 1996-01-17 2000-09-06 Motorola Inc Method for storing repair data in a micro processor system
EP0889405A1 (fr) * 1997-06-19 1999-01-07 Nec Corporation Méthode de débogage de logiciel
US6175935B1 (en) 1997-06-19 2001-01-16 Nec Corporation Software debugging method and recording medium to which debugging program has been recorded
WO2000038081A1 (fr) * 1998-12-21 2000-06-29 Infineon Technologies Ag Unite commandee par programme a memoires internes et externes
EP1244007A3 (fr) * 2001-03-21 2007-05-23 Broadcom Corporation Correction dynamique de microcode
EP1244007A2 (fr) 2001-03-21 2002-09-25 Broadcom Corporation Correction dynamique de microcode
GB2384582A (en) * 2002-01-28 2003-07-30 Ericsson Telefon Ab L M Software correction
US7516372B2 (en) 2002-01-28 2009-04-07 Microsoft Corporation Processor control system for supplying control instructions to a processor
US7243206B2 (en) * 2003-04-14 2007-07-10 Arm Limited Method and apparatus for using a RAM memory block to remap ROM access requests
WO2005036486A1 (fr) * 2003-10-10 2005-04-21 Giesecke & Devrient Gmbh Acces a des elements de donnees dans un support de donnees portable
EP1646052A1 (fr) * 2004-10-07 2006-04-12 Infineon Technologies AG Circuit mémoire incorporant un remplacement flexible de cellules mémoire défectueuses relatif aux arrangements en forme de lignes de bit ou de lignes de mot
US7263011B2 (en) 2004-10-07 2007-08-28 Infineon Technologies Ag Memory circuit with flexible bitline-related and/or wordline-related defect memory cell substitution
US20110055821A1 (en) * 2009-08-31 2011-03-03 Sony Computer Entertainment Inc. Information Processing Apparatus
US8949205B2 (en) * 2009-08-31 2015-02-03 Sony Corporation Information processing apparatus for processing application software and a patch file

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