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WO1993002473A1 - Liaisons programmables par tension pour circuits integres - Google Patents

Liaisons programmables par tension pour circuits integres Download PDF

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Publication number
WO1993002473A1
WO1993002473A1 PCT/US1992/006138 US9206138W WO9302473A1 WO 1993002473 A1 WO1993002473 A1 WO 1993002473A1 US 9206138 W US9206138 W US 9206138W WO 9302473 A1 WO9302473 A1 WO 9302473A1
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WO
WIPO (PCT)
Prior art keywords
refractory
layer
depositing
aluminum
conductive
Prior art date
Application number
PCT/US1992/006138
Other languages
English (en)
Inventor
Simon S. Cohen
Jack I. Raffel
Peter W. Wyatt
Original Assignee
Massachusetts Institute Of Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/735,427 external-priority patent/US5258643A/en
Application filed by Massachusetts Institute Of Technology filed Critical Massachusetts Institute Of Technology
Publication of WO1993002473A1 publication Critical patent/WO1993002473A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the technical field of this invention is solid state integrated circuit fabrication and, more particularly, methods for fabricating voltage programmable link structures.
  • Programmable conductive paths are increasingly employed in solid-state integrated circuit fabrication to produce a wide variety of programmable circuits including, for example, field programmable gate arrays ("FPGAs”), programmable read only memories (“PROMs”), and other programmable electronic devices.
  • FPGAs field programmable gate arrays
  • PROMs programmable read only memories
  • Such devices are "programmed" by the application of an electrical voltage to trigger an "antifuse” link structure disposed between two metallization layers and thereby establish an electrical connection across a region of the device which had previously been an insulator.
  • link structures must remain insulating at the normal operating voltage for solid state devices (e.g., nominally five volts), but must reliably "break down,” or respond, to a programming voltage which is higher than the normal operating voltage, but not so high as to damage other structures on the circuit (e.g., not more than about fifteen volts) .
  • hillocks can pierce or otherwise damage overlying insulator layers unless such insulator layers are rather thick (e.g. greater than about 500 nanometers).
  • hillocks are less troublesome because the intermetallic insulators normally used are thick, but fabrication of a link structure with a low programming voltage requires the use of a thin insulator.
  • the thin insulator layer required for link structures makes link structures particularly sensitive to the occurrence of hillocks. If the insulator layer is too thin, hillocks may damage the insulator thereby lowering the breakdown voltage below normal operating voltages. However, if a thick insulator layer is employed to avoid inadvertent breakdowns, the resulting programming voltage may be so high as to damage other structures on the wafer. Since hillocks do not occur according to a uniform distribution it is extremely difficult to manufacture a reliable link structure with a low programming voltage using aluminum-based metallization.
  • One way to avoid the problem of hillocks is to use non-metallic conductors, such as polysilicon or doped silicon, instead of aluminum.
  • Methods and systems are disclosed for fabricating electrically programmable link structures by fabricating a first conductor, which comprises a refractory conductive material, then fabricating an insulative link material over the refractory conductive material and, subsequently, depositing an upper conductive material over the link material.
  • a first conductor which comprises a refractory conductive material
  • an insulative link material over the refractory conductive material and, subsequently, depositing an upper conductive material over the link material.
  • an electrical path can be formed between the first and second conductive elements by applying a programming voltage between such elements across at least one selected region of the insulator, such that the insulative link material is transformed in the region and rendered conductive to form an electrical signal path.
  • the present invention provides reliable link structures that can be consistently programmed by the application of programming voltages of about 10 volts or less, with a current of about 10 microamps or less, over a time of about 1 millisecond or less. These programming parameters are a significant improvement over prior art techniques and substantially reduce the possibility of damage to adjacent device structures during programming.
  • the first conductive element is entirely composed of a refractory conductive material.
  • the first conductive element is a composite of non-refractory conductive material that is capped with a sufficient thickness of refractory conductive material. This embodiment is particularly useful because aluminum, a non-refractory material, can be retained as the primary conductor, and the refractory conductive material merely caps the aluminum.
  • the lower conductive element will typically range from about 300 to about 1,000 nanometers in thickness. Up to about 95 percent of the conductive line can be aluminum so long as it is capped with about 5 nanometers or more of refractory conductive material.
  • the refractory conductive material used in the lower conductive element is a refractory metal, refractory metal alloy, refractory metal nitride, or refractory metal suicide.
  • the refractory conductive material should have a low thermal coefficient of expansion, for example, below 10.0 x 10- 6 /°C, preferably below 7.0 x 10- 6 /°C and most preferably under 5.0 x 10 ⁇ 6 /°C.
  • This low thermal expansion coefficient is especially useful when a bulk refractory material is used as the conductive element because the metallization layer can be more closely matched thermally to the underlying substrate and/or devices therein which will typically be silicon-based materials.
  • the low thermal expansion coefficient also provides a closer match to the silicon-based decomposable link materials which can be deposited to form the programmable links of the present invention as described in more detail below.
  • Particularly useful refractory conductive materials include titanium, titanium alloys, molybdenum, and molybdenum alloys which typically have a thermal expansion coefficient of about 4.0 x 10 ⁇ 6 /°C (a value that matches silicon's coefficient, nominally 3.0 x 10" 6o C, quite well).
  • non-refractory materials such as aluminum or aluminum alloys
  • aluminum is used alone as the lower conductive material, its thermal expansion during the various wafer processing and device fabrication steps that follow can cause microfractures in the link material, resulting in premature breakdowns, inadvertent breakdowns and a wide variation in the voltage needed to program individual link structures from one site to another on a wafer.
  • aluminum has a tendency to form rather marked surface irregularities in the form of "hillocks" and the like, during sintering and other device processing steps. These hillocks can pierce or otherwise damage overlying insulator layers unless such insulator layers are rather thick (e.g. greater than 500 nanometers).
  • refractory materials such as titanium, molybdenum or their alloys and compounds, even as thin "cap” layers, is also preferred because of the relatively smooth surfaces that can be achieved with such metallization layers.
  • the refractory conductive materials disclosed herein substantially match the thermal expansion characteristics of the link materials, the likelihood of detrimental thermal stresses, microfractures, etc. is greatly reduced.
  • the smooth surface topography of the refractory conductive materials in the present invention reduces the chance that projections from the metal layer can pierce or otherwise damage the adjacent link material, and thereby permits thinner insulators to be used.
  • the link structures of the present invention can be programmed by application of a substantially uniform threshold voltage with little deviation from one link to another in use.
  • the lower refractory conductive material should maintain a smooth upper surface throughout processing, that is, a surface defined by the substantial absence of hillocks and other projections greater than about 10 nanometers above the nominal plane of the surface, and more preferably defined by the absence of hillocks and the like greater than about 5 nanometers in height.
  • some refractory conductive materials useful in the present invention can have a surface topography, as deposited, that is slightly coarse (e.g. with grains that may vary in height from one to another by about 1 to 5 nanometers) due to the vertical columnar structures that are typically present in molydenum and similar materials, as initially formed. Such surface irregularities do not appear to effect the performance of link structures.
  • the lower conductive element comprises "modified alumin m" which is aluminum that incorporates a refractory conductive material in a region near, at least, the surface of the aluminum.
  • Modified aluminum is formed by "treating" aluminum with a refractory conductive material. This embodiment is useful because the modified aluminum can be produced by processes that differ only minimally from the standard integrated circuit manufacturing process.
  • the modified aluminum is produced by first depositing a layer of aluminum according to standard processing techniques. The aluminum layer can then be patterned (e.g., by masking and etching or the like) to form conductive lines. Then a thin layer of refractory conductive material is deposited over the entire wafer substrate, or just those portions where links are desired. The wafer is then sintered, which causes an intermetallic compound to form near the adjacent surfaces of the aluminum and the refractory conductive material.
  • the layer of refractory material is removed (e.g., by selective etching) from those portions of the wafer where it has not been incorporated into the metallization. This re-exposes the substrate in regions where no aluminum was present, but the surface of the aluminum remains as an intermetallic compound. This intermetallic compound effectively prevents the aluminum from forming hillocks during later processing steps.
  • the resulting, modified aluminum has a very flat surface (e.g., surface irregularities with height of less than 50 nanometers over a span of greater than about 10 micrometers) .
  • the aluminum alloy is patterned as above, and then a refractory metal is deposited selectively only on the aluminum surfaces.
  • the wafer is then sintered as above, with no selective etch step required.
  • an aluminum layer can be deposited, and followed directly by the deposition of a refractory conductive material.
  • the bimetallic layer can next be sintered and then patterned (or vice versa) to yield a similar surface-modified aluminum metallization. The sintering may take place either before or after deposition of insulating layers.
  • a very thin layer e.g., less than about 50 nanometers
  • This coating layer is too thin to cause hillocks or other potentially damaging surface phenomena, but it protects the refractory material during subsequent processing steps. If modified aluminum is used, the coating layer may be deposited either before or after sintering.
  • the link material is preferably a silicon oxide insulator and can also include one or more other insulating layers to physically separate the oxide from the first and second conductive elements. Silicon nitrides are particularly useful as protective barrier layers in separating the oxide layer from aluminum based metallization.
  • the transformable insulator can be formed (e.g., by deposition) of silicon oxide, silicon nitride or combinations of these materials. In one preferred embodiment, a three part structure can be employed comprising a silicon nitride - silicon oxide - silicon nitride composite. In contrast to prior art sandwich structures, this composite link structure protects the oxide component from, rather than exposing it to, the conductive metal lines, thereby minimizing the chance of chemical reactions that could degrade the structure over time.
  • PECVD plasma-enhanced chemical vapor deposition
  • CVD thermal chemical vapor deposition
  • silicon-rich insulators have been found useful. In some applications, it may be preferable to deposit silicon-rich compositions with up to twice as much silicon as the normal (Si ⁇ 2 and Si3N4) stoichiometric formulae.
  • the oxide layers of the link compositions can be described by the formula: SiO x , where x can range from about 1.5 to about 2.0, and the nitride layers can be described by the formula: SiN y , where y can range from about 0.3 to about 1.3.
  • a thick oxide insulator normally separates the lower and upper conductive layers.
  • the thick insulator may be deposited either before or after the transformable insulator. In one approach, for example, the thick insulator is deposited over the entire surface and then etched away in regions where programmable links are desired. A transformable insulator is then deposited in those regions.
  • an upper conductive element can be deposited above the link material and the lower conductive element.
  • This second metallization layer can be aluminum or any other low resistance conductive material. In some applications, it can be preferable to construct the upper conductive layer as a mirror image of the lower conductive layer.
  • the wafer again can be covered by a thin layer of refractory conductive material followed by a standard aluminum metallization layer. If modified aluminum is desired, sintering the wafer then forms an intermetallic compound of aluminum and the refractory material at the metallization surface which contacts the link insulator. Then the second metallization layer is patterned, leaving an upper conductive element over the link material.
  • the composition of the upper metallization may be further modified by co-depositing aluminum and the refractory metal (either sequentially or together), and then sintering the structure to create a bimetallic compound with enough refractory components throughout to achieve a hillock-free boundary.
  • the upper metallization can be formed by sequentially depositing a refractory metal, aluminum and a second refractory layer, and then sintering.
  • a tri-layer composite upper metallization of sequential aluminum, refractory metal and aluminum layers can be deposited as the upper conductor, with the first aluminum deposition being very thin (e.g. about 10-30 nanometers) to isolate the insulator from possible damage during the refractory deposition.
  • the upper conductive layer can include a thin bottom film of non-refractory metal, such as aluminum.
  • the thin metal film can be deposited over the transformable insulator in order to protect it during subsequent processing steps.
  • the thin metal film is deposited above the transformable insulator over the entire wafer surface.
  • the metal film is then patterned (e.g., by resist masking) and removed except in the link regions.
  • a thick insulator is subsequently deposited over the entire surface and then etched away to expose the link regions.
  • the remaining thin metal film pads act as etch stops which protect the transformable insulator from damage during the steps of depositing and etching the thick insulator.
  • the thin film also protects the transformable insulator during deposition of the rest of the upper conductive layer. Protecting the integrity of the transformable insulator results in voltage programmable links which exhibit a more uniform distribution of breakdown voltages.
  • conductive links can be formed by the application of a predetermined voltage, typically greater than seven volts but less than 15 volts, preferably on the order of about 7.5 to about 12.5 volts, and most preferably on the order of about 8.5 to about 10.5 volts.
  • a predetermined voltage typically greater than seven volts but less than 15 volts, preferably on the order of about 7.5 to about 12.5 volts, and most preferably on the order of about 8.5 to about 10.5 volts.
  • aluminum as used herein is intended to encompass not only pure aluminum but also various aluminum alloys, including AlSi, AlSiCu, AlCu, AITi, AlCuCr and the like which are known and used routinely in the semiconductor industry.
  • first and second metallization layers are used herein to distinguish between lower and upper metallization lines, it should be clear that the "first" metallization line need not be the first or lowest conductive path in the integrated circuit. Likewise, the “second” layer need not be the only other metallization layer. There may be other metallization layers that do not enter into the programmable link.
  • the invention can be practiced to establish links between more than two conductive layers, the terms "first" and “second” being merely shorthand expressions for the bottom and top of the conductive path, respectively.
  • substrate is used herein to describe various layers which may lie below the "first" metallization layer, including the bulk silicon of the wafer, active devices (e.g. sources, gates and/or drain regions), field oxide layers, gate oxide layers, and other structures as the case may be.
  • active devices e.g. sources, gates and/or drain regions
  • field oxide layers e.g. field oxide layers
  • gate oxide layers e.g. field oxide layers
  • other structures as the case may be.
  • FIG. IA is a sectional schematic view of a voltage programmable link structure according to the invention.
  • FIG. IB is a sectional schematic view of another voltage programmable link structure according to the invention.
  • FIG. 2A is a schematic illustration of an initial processing step
  • FIG. 2B is a second processing step
  • FIG 2C is a further processing step, respectively, in the formation of a metallization according to the invention
  • FIG. 3 is a graph of the surface profile of a conventional aluminum metallization layer, following common sintering treatment, showing the formation of irregular surface hillocks;
  • FIG. 4 is a graph of the surface profile of a modified metallization layer according to the invention, again following sintering, showing the formation of a smooth surface without hillocks;
  • FIGS. 5 and 6 are histograms of programmable links activated by an applied voltage in accordance with the invention, showing the relative numbers of links achieved at various programming voltages;
  • FIG. 7 is a sectional view of an integrated circuit showing a plurality of programmable link structures in accordance with the invention. Detailed Description
  • a programmable link structure 10A is shown formed upon a substrate 12 (which can be a field insulator or an active device layer of an integrated circuit wafer) .
  • the link 10A includes a first (lower) metallization layer 14 comprising a refractory conductive material.
  • first metallization layer 14 consists entirely of a refractory conductive material.
  • it comprises a first layer of non-refractory conductive material, such as aluminum or silicon, and a second, capping, layer of refractory conductive material.
  • first metallization layer 14 can be modified aluminum.
  • modified aluminum can be formed by depositing an aluminum layer on substrate 12, followed by deposition of a thin (e.g., less than about 50 nm) refractory conductive layer. The wafer can then be sintered to form an intermetallic compound. The bimetal film may be patterned either before or after this sintering step, and the insulators 18 and 20 may be deposited either before or after the sintering step. (A method of forming a modified aluminum metallization layer 14 is illustrated in Fig. 2 and described in more detail below.)
  • First metallization layer 14 may further include a thin conductive top coating 16 (again less than about 50 nanometers) of a non-refractory conductor, such as aluminum. Above this first metallization layer 14, a thick oxide insulator 18 is typically deposited in all regions, except those where a programmable link is desired. (In practice, the oxide is typically deposited uniformly over the wafer and etched away by conventional masking techniques to form a local via and expose the first metallization layer 14 or the conductive top coating 16, if present.)
  • a transformable insulator 20 is then deposited as the link material into the etched via.
  • a second (upper) metal line 28 is formed over the link (e.g., by deposition, masking and etching, or other techniques well known in the industry) .
  • second metal 28 may correspond to mirror images of the possible embodiments of first metallization layer 14. So second metal 28 may consist entirely of a refractory conductive material, or alternatively, it may consist of a layer of refractory conductive material covered by a layer of non-refractory conductive material. In yet another embodiment second metal 28 may comprise modified aluminum. A thin bottom coating of non-refractory conductive material 30 may also separate second metal 28 from link material 20.
  • the decomposable insulator 20 comprises a three-part deposited sandwich consisting of a first silicon nitride layer 22, a middle silicon oxide layer 24 and upper silicon nitride layer 26.
  • These three layers can each have thicknesses ranging from about 5 to 30 nanometers, preferably less than 15 nanometers.
  • each of the three layers can be about 10 nanometers thick.
  • the thickness of these layers may vary with particular applications, but they should be designed such that the application of a voltage from upper conductive metal layer 28 to the lower metallization layer 14 will cause the link material to become conductive.
  • FIG. IB an alternative embodiment of the programmable link structure 10B is shown again formed upon a substrate 12.
  • the link 10B includes a first (lower) metallization layer 14 comprising a refractory material and, optionally, having a thin conductive top coating 16 of aluminum or the like.
  • Deposited directly above the first metallization is the transformable insulator 20, again preferably comprising a multi-layer composite (e.g., a first silicon nitride layer 22, a middle silicon oxide layer 24 and an upper silicon nitride layer 26).
  • a thin conductive metal layer e.g., aluminum
  • a base pad 30 for an upper conductor.
  • FIGS. 2A-2C illustrate a process for fabricating aluminum which is modified on its sidewalls as well as its top surface.
  • a conductive material 28 e.g., aluminum, modified aluminum or a bulk refractive conductor
  • FIGS. 2A-2C illustrate a process for fabricating aluminum which is modified on its sidewalls as well as its top surface.
  • an aluminum line 13 is deposited on substrate 12.
  • a thin layer of refractory conductive material 15 is deposited over aluminum 13.
  • the refractory material 15 may be deposited exclusively over the aluminum 13, or alternatively, the refractory material 15 may also be deposited over other portions of the substrate 12.
  • the wafer is then sintered which causes an intermetallic compound 17 to form near the adjacent surfaces of the aluminum 13 and the refractory conductive material 15.
  • FIG. 2B illustrates the formation of the intermetallic compound.
  • the combination of the aluminum 13 and the intermetallic compound 17 comprises the modified aluminum.
  • a selective "etch back" procedure removes the unreacted refractory material 15, re-exposing the substrate in regions where no aluminum was present, but the surface of the modified aluminum remains as an intermetallic compound with refractory properties.
  • the aluminum-modifying step may be preferable to repeat the aluminum-modifying step at the top surface of the second metallization layer, thereby, achieving a hillock-free upper surface of the second metal layer.
  • This upper surface can further be coated with a protective or smoothing coating, e.g., on the order of about 10 to 50 nanometers, of aluminum.
  • a protective or smoothing coating e.g., on the order of about 10 to 50 nanometers, of aluminum.
  • An alternative method of incorporating the refractory component into the metallization would be to employ ion implantation techniques to drive titanium, molybdenum or other refractory metal ions into the aluminum layer (e.g., either uniformly across the surface immediately following the aluminum deposition step, or selectively at link sites following patterning of the metallization lines) to create at least one modified aluminum conductor at the link site.
  • FIG. 3 is a graph illustrating the typical surface irregularities found when aluminum is deposited as a first (lower) metallization layer material. As can be seen in FIG. 3, the aluminum surface exhibits a number of protrusions or "hillocks" which extend above the surface layer by as much as 1 micrometer. The surface irregularities can result in microfractures of the overlying materials during wafer processing.
  • FIG. 4 shows the much smoother surface structure of modified aluminum treated in accordance with the present invention.
  • FIG. 5 is an histogram of programmable links activated by an applied voltage in accordance with the invention, showing the relative numbers of links achieved at various programming voltages. As the results indicate, the distribution of breakdown voltages was quite narrow. A total of 742 links were activated by application of voltage in the range of about 8.5 to 10.5 volts. The link structures were nitride-oxide-nitride (10 nanometers each) sandwich structures with molybdenum as the lower conductor and aluminum as the upper conductor.
  • FIG. 6 is an histogram of programmable link structures made with modified aluminum and activated by an applied voltage in accordance with the invention, showing the relative numbers of links achieved at various programming voltages. The distribution of breakdown voltages was again quite narrow. A total of 85 links were tested.
  • the links included in FIG. 6 were fabricated on a single wafer.
  • the thickness of the aluminum alloy (AISi) used in the lower conductor was 750 nm.
  • the aluminum was coated with a 30 nm layer of titanium, and then 30 nm of Al.
  • a thick silicon oxide insulator was formed over the first layer of metallization everywhere except the link regions, where the transformable insulators were deposited.
  • These link insulators were nitride-oxide-nitride (10, 15, 10 nanometers each) sandwich structures.
  • the upper conductors were fabricated above the transformable insulators with a 30 nm layer of Al, followed by a 750 nm layer of AISi. Finally, the wafer was sintered at 455°C for 30 minutes.
  • link structures of the present invention have also been fabricated with aluminum layers coated with molybdenum and then sintered to yield molybdenum-modified aluminum metallizations.
  • Another advantage of the link structures of the present invention is that the breakdown voltage can be adjusted by a simple step of heat cycling, thereby permitting the manufacturer to tailor the programming voltage of particular devices to specific needs. Without being limited to any particular principle or mechanism, it appears that sintering permits the reaction of the refractory component of the metallization (e.g., the titanium) with elements that form the link material, thereby forming conductive (or semiconductive) titanium nitrides and oxides, or the like, which weaken the link and result in lower breakdown voltages.
  • the breakdown voltage can be adjusted by sintering the device at about 450°C for one or more thirty-minute cycles.
  • FIG. 7 is a sectional view of an integrated circuit 40 showing a plurality of programmable link structures in accordance with the invention.
  • circuit 40 a number of active devices are formed upon a substrate S.
  • a transistor is shown comprising source 42, drain 44 and gate 46.
  • the components of this active device are isolated from the other structures of the wafer by a thick oxide layer 48 (and a thinner gate oxide 50 in the vicinity of the transistor gate 46) .
  • the formation of such active devices is well known in the art.
  • Another transistor having similar source, drain and gate elements 42', 44', and 46', respectively, is shown at the right side of FIG. 7.
  • First metallization layer Ml is deposited in order to interconnect various active device elements on circuit 40.
  • the conductor layer Ml provides electrical connections to the source 42 and drain 44.
  • Metallization layer Ml can also provide electrical contacts with polysilicon gate region 46' as shown on the right side of the figure.
  • metallization layer Ml comprises a refractory conductive material, composite, or modified aluminum, as described above, which substantially reduces the hillock-induced defects associated with aluminum-based structures.
  • Layer Ml can further include a non-refractory top coating as described above.
  • a via is first created (e.g., by etching away portions of insulator 52) above those sites where a link is to be formed with the underlying metal lines Ml.
  • a decomposable insulator 20 is deposited according to the present invention.
  • the decomposable insulator 20 can comprise a three-part deposition sandwich, as described above, consisting of a first silicon nitride layer 22, a middle silicon oxide layer 24 and upper silicon nitride layer 26.
  • each of the three layers of the link structure 20 can be about 10 nanometers thick.
  • a second (upper) metallization layer M2 can be deposited and patterned to form another set of interconnects, again as described above.
  • Link structure 60 permits an electrically programmable link to be formed between upper metal layer M2, lower layer Ml and transistor drain 44.
  • link structure 70 permits the formation of a link between layers M2 and Ml (in which the Ml line is electrically connected to another device element not shown in the sectional plane of FIG. 7).
  • Link structure 80 permits the formation of a link between M2, Ml and the gate 46' of the transistor shown on the right side of the figure.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
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Abstract

L'invention décrit des procédés et des dispositifs servant à fabriquer des structures de liaisons programmables électriquement (10) et comprenant les étapes suivantes: fabrication d'un premier conducteur en métal (14) en matériau réfractaire conducteur, en composite ou en alliage d'aluminium modifié au moyen d'un matériau réfractaire; fabrication d'un isolant de liaison transformable (20) au-dessus du premier conducteur (14) et, ensuite, dépôt d'un deuxième conducteur (28) sur le matériau de liaison. En fonctionnement, un trajet électrique peut se former entre le premier et le deuxième conducteur au moyen de l'application d'une tension entre lesdits conducteurs dans au moins une région sélectionnée de l'isolant, de façon à transformer le matériau de liaison isolant dans ladite région, ainsi qu'à le rendre conducteur, afin de constituer un trajet de signal électrique.
PCT/US1992/006138 1991-07-25 1992-07-22 Liaisons programmables par tension pour circuits integres WO1993002473A1 (fr)

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Application Number Priority Date Filing Date Title
US07/735,427 US5258643A (en) 1991-07-25 1991-07-25 Electrically programmable link structures and methods of making same
US735,427 1991-07-25
US86067892A 1992-03-30 1992-03-30
US860,678 1992-03-30

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5572050A (en) * 1994-12-06 1996-11-05 Massachusetts Institute Of Technology Fuse-triggered antifuse
DE10103298A1 (de) * 2001-01-25 2002-08-22 Infineon Technologies Ag Integrierte Anti-Fuse-Struktur

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0250078A2 (fr) * 1986-05-09 1987-12-23 Actel Corporation Elément d'interconnexion programmable à basse impédance
US4748490A (en) * 1985-08-01 1988-05-31 Texas Instruments Incorporated Deep polysilicon emitter antifuse memory cell
EP0414361A2 (fr) * 1989-08-24 1991-02-27 Advanced Micro Devices, Inc. Structure semi-conductrice antifusible et procédé

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4748490A (en) * 1985-08-01 1988-05-31 Texas Instruments Incorporated Deep polysilicon emitter antifuse memory cell
EP0250078A2 (fr) * 1986-05-09 1987-12-23 Actel Corporation Elément d'interconnexion programmable à basse impédance
EP0414361A2 (fr) * 1989-08-24 1991-02-27 Advanced Micro Devices, Inc. Structure semi-conductrice antifusible et procédé

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SOLID STATE TECHNOLOGY vol. 30, no. 4, April 1987, WASHINGTON US pages 155 - 162 Y. PAULEAU 'Interconnect Materials for VLSI Circuits' *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5572050A (en) * 1994-12-06 1996-11-05 Massachusetts Institute Of Technology Fuse-triggered antifuse
DE10103298A1 (de) * 2001-01-25 2002-08-22 Infineon Technologies Ag Integrierte Anti-Fuse-Struktur

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