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WO1993003500A1 - Procede de formation d'un element resistant dans un dispositif a semi-conducteur et memoire ram statique obtenue par ce procede - Google Patents

Procede de formation d'un element resistant dans un dispositif a semi-conducteur et memoire ram statique obtenue par ce procede Download PDF

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Publication number
WO1993003500A1
WO1993003500A1 PCT/US1992/006449 US9206449W WO9303500A1 WO 1993003500 A1 WO1993003500 A1 WO 1993003500A1 US 9206449 W US9206449 W US 9206449W WO 9303500 A1 WO9303500 A1 WO 9303500A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
approximately
implanting
silicon
silicon dioxide
Prior art date
Application number
PCT/US1992/006449
Other languages
English (en)
Inventor
Sik K. Lui
Original Assignee
Sierra Semiconductor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sierra Semiconductor Corporation filed Critical Sierra Semiconductor Corporation
Publication of WO1993003500A1 publication Critical patent/WO1993003500A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element

Definitions

  • the present invention relates to a method for making a resistive element having high resistivity in a semiconductor device. More particularly, the present invention relates to a method of forming a vertical resistor for use in a SRAM memory cell.
  • polycrystalline silicon is disclosed as a resistive element for use in an SRAM memory cell.
  • the polycrystalline silicon is positioned horizontally.
  • a method for forming a resistive element for use in an SRAM Cell comprises implanting oxygen into polycrystalline silicon to form the resistive element.
  • a method of forming a resistive element between a first and a second conductive element in a semiconductor device is disclosed.
  • the resistive element can be horizontal, vertical or any other shape and can be used in any application. However, the resistive element is particularly suited for use in a static ram memory cell.
  • the resistive element has a resistance having a certain value.
  • the method of the invention comprises the steps of forming the first conductive element. A layer of insulating material is deposited in contact with the first conductive element. A non-insulating element is implanted into the layer of insulating material to decrease the resistance of the layer to the desired certain value of the resistive element. Finally, the second conductive element is formed in contact with the layer of the implanted insulating material.
  • Figure 1 is a schematic circuit diagram of an SRAM memory cell using resistive load elements of the prior art.
  • Figure 2 is a cross-sectional view of a semiconductor structure of the prior art, implementing the schematic circuit shown in figure 1.
  • Figure 3 (a-g) are steps in the method of the present invention in forming a vertical resistive element for use in a static ram memory cell whose circuit diagram is shown in figure 1.
  • Figure 4 is a plot of concentration of the silicon implant into an insulating layer of silicon dioxide, in accordance with the method of the present invention.
  • FIG. 1 there is shown a schematic circuit diagram of a SRAM memory cell 10 of the prior art.
  • the SRAM memory cell 10 comprises two cross- coupled transistors Ql and Q2 with two access transistors Q3 and Q4.
  • the SRAM memory cell 10 is known as a four transistor (or 4T) cell.
  • the Cell 10 comprises two resistive load elements 18 (a and b) . Each of the resistive elements 18 (a and b) is connected to one of the transistors Ql or Q2.
  • each of the transistors Q1-Q4 comprises a source 12, a gate 16 and a drain 14.
  • the source 12 of the transistors Ql and Q2 are connected to a source of first voltage potential, i.e., ground potential.
  • the drain 14 of the transistors Ql and Q2 are connected to transistors Q3 and Q4 respectively and to one end of the resistive elements 18 (a and b) .
  • the other end of the resistive elements 18 (a and b) are connected to a source of second voltage potential, such as V cc .
  • the transistors Ql and Q2 have a gate 16 which is connected to the drain 14 of the other transistor. In this manner, the transistors Ql and Q2 are cross-coupled.
  • Transistor Ql is shown as having source 12, gate 16, and drain 14.
  • a heavily doped polycrystalline layer labeled poly-2 is electrically connected to the drain region 14.
  • the poly-2 has a region 18 which is undoped and forms the intrinsic poly or the resistive element 18.
  • At its other end of the poly-2 is another heavily doped region forming the connection to the source of second voltage potential V cc .
  • the first heavily doped region of the poly- 2 is connected to a first layer of heavily doped polysilicon labelled poly-1 which is connected to the gate 16 of the transistor Q2 (not shown) .
  • the prior art SRAM memory cell 10 has a resistive element 18 which is horizontally displaced.
  • resistive element 18 As the scale of integration increases and it is desired to increase the density of the SRAM memory cell 10 in a device, it is desired to "shrink" the lateral area occupied by each SRAM cell 10.
  • U.S. Patent No. 4,416,049 discloses a vertically aligned resistive element 18 for use in an SRAM memory cell 10 in order to increase the density of an SRAM Memory Circuit.
  • the present invention relates to a method for forming a vertically aligned resistive element which can be used in a 4-T SRAM cell 10.
  • the method of the present invention can be used in any application where a resistive element in a semiconductor device is desired.
  • the method of the present invention can also be used to form a horizontal resistive element.
  • a semiconductor substrate 30 is shown as having field oxide regions 32 formed thereon.
  • a layer of buffered oxide 34 is formed on top of the semiconductor substrate 30.
  • the formation of the field oxide region 32 and the buffer oxide region 34 on the substrate 30 is well known in the art.
  • One method is to begin with a semiconductor substrate 30 and forming the buffer oxide layer 34 on the entire surface of the substrate 30, by oxidizing the silicon substrate. Thereafter, silicon nitride is deposited over the buffered oxide layer 34. The silicon nitride layer is patterned and etched using conventional photolithographic techniques.
  • the mask 36 is applied.
  • the mask 36 is patterned exposing a selected region of the structure.
  • the selected region exposes a portion of the gate oxide 42 and field oxide 32.
  • the exposed region of silicon dioxide from the gate oxide layer 42 and the field oxide region 32 is then etched.
  • the mask 36 is then removed.
  • a 3,000-4,000 Angstrom thick polycrystalline silicon layer 38 is deposited over the entire structure by conventional LPCVD.
  • the polysilicon layer 38 is then doped with an N type dopant such as phosphorus or arsenic at approximately 900-1,000°C.
  • the high temperature drives the dopant into the substrate 30, where the polycrystalline silicon layer 38 is in direct contact with the silicon substrate 30, to form a buried contact with the drain 14a.
  • the silicon dioxide prevents the dopant from being driven into the silicon substrate 30.
  • the polysilicon layer 38 is patterned and etched by conventional lithographic methods to form the gate 16 of transistors Ql and Q2 and the cross-coupling or the electrical connection between the polycrystalline silicon 38 of transistor Ql (which is in contact with the drain 14a of Ql) to the gate 16 of Q2 (not shown, but is directly behind polysilicon 38) and from the polycrystalline silicon 38 of transistor Q2 (which is in contact with the drain 14a of Q2 - not shown, but is directly behind gate 16) to the gate 16 of Ql.
  • a mask is then applied exposing the source 12 and drain 14b of the transistors Ql and Q2. Dopants are implanted into the source 12 and drain 14b regions and the gate 16 to render them conductive.
  • a typical dopant is
  • a mask 42 is formed over the entire structure.
  • the mask 42 is patterned and is exposed.
  • the exposed area is removed.
  • the exposed area is over the region where the vertical resistor 18 would be formed connected to the underlying polysilicon layer 38.
  • Silicon ions are implanted through the exposed area of the mask 42, into the silicon dioxide region 40 between the dotted lines shown in Figure 3f.
  • the silicon is implanted a number of times with each implant having an energy range from 20 KeV to 200 KeV and with the dosages ranging from 1.0 E15 to 1.0 E17.
  • Figure 4 there is shown a graph of the concentration of silicon in a 2,000 Angstrom thick region of silicon dioxide.
  • a second layer of polysilicon 44 is deposited over the entire structure. This can be done for example, by depositing 1,000-2,500 Angstrom thick polysilicon using conventional LPCVD.
  • the second polysilicon layer 44 is then implanted with an N-type dopant such as phosphorus or arsenic.
  • the structure is then annealed at a temperature range of approximately 900 to l,000°C in nitrogen. The annealing process joins the dopants from the drain regions 14a and 14b to form a single contiguous drain region 14.
  • the second polysilicon layer 44 is then patterned and etched by conventional lithographic methods to form the necessary connection to the resistor 18 and to connect to the source of second voltage potential V cc .
  • the result is the structure shown in figure 3g.
  • the method described heretofore is the preferred method, the method can be practiced by implanting any non-insulating element (such as a semiconductor element or a conductive element) into an insulating material.
  • the implanted semiconductor element can be silicon.
  • the implanted conductive element can be aluminum or carbon.
  • the insulating material can be silicon dioxide, BPSG (boron phosphorous doped glass) , PSG (phosphorous doped glass) or silicon nitride.
  • the insulating material has a resistivity that is lowered by the implanting of a non-insulating element.
  • the amount of implanted non- insulating element determines the degree to which the resistivity of the insulating material is lowered until the desired resistivity is achieved.
  • the resistive element can be formed vertically, horizontally or in any other shape and is not necessarily limited to the vertical resistor described in the preferred embodiment.
  • the resistor formed by the method of the present invention can be used for an SRAM cell or any other application in a semiconductor device.

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  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un procédé de formation d'un élément résistant (18) destiné à être utilisé dans un dispositif à semi-conducteur. L'élément résistant (18) peut être utilisé dans un élément de mémoire RAM statique 4T. L'élément résistant (18) est constitué par l'implantation d'un élément non isolant, par exemple du silicium, dans une couche de matériau isolant (40), tel que du dioxyde de silicium, pour diminuer la résistance spécifique de la couche de façon à obtenir un élément résistant (18) présentant la valeur de résistance désirée.
PCT/US1992/006449 1991-08-01 1992-07-31 Procede de formation d'un element resistant dans un dispositif a semi-conducteur et memoire ram statique obtenue par ce procede WO1993003500A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US74004191A 1991-08-01 1991-08-01
US740,041 1991-08-01

Publications (1)

Publication Number Publication Date
WO1993003500A1 true WO1993003500A1 (fr) 1993-02-18

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1992/006449 WO1993003500A1 (fr) 1991-08-01 1992-07-31 Procede de formation d'un element resistant dans un dispositif a semi-conducteur et memoire ram statique obtenue par ce procede

Country Status (1)

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WO (1) WO1993003500A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0863546A1 (fr) * 1997-03-07 1998-09-09 STMicroelectronics S.A. Pseudofusible et application à un circuit d'établissement d'une bascule à la mise sous tension
GB2343787A (en) * 1998-11-06 2000-05-17 United Microelectronics Corp Method of fabricating load resistor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4656729A (en) * 1985-03-25 1987-04-14 International Business Machines Corp. Dual electron injection structure and process with self-limiting oxidation barrier
US4733482A (en) * 1987-04-07 1988-03-29 Hughes Microelectronics Limited EEPROM with metal doped insulator
US4868618A (en) * 1988-03-24 1989-09-19 Northern Telecom Limited Ion implanted semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4656729A (en) * 1985-03-25 1987-04-14 International Business Machines Corp. Dual electron injection structure and process with self-limiting oxidation barrier
US4733482A (en) * 1987-04-07 1988-03-29 Hughes Microelectronics Limited EEPROM with metal doped insulator
US4868618A (en) * 1988-03-24 1989-09-19 Northern Telecom Limited Ion implanted semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0863546A1 (fr) * 1997-03-07 1998-09-09 STMicroelectronics S.A. Pseudofusible et application à un circuit d'établissement d'une bascule à la mise sous tension
FR2760563A1 (fr) * 1997-03-07 1998-09-11 Sgs Thomson Microelectronics Pseudofusible et application a un circuit d'etablissement d'une bascule a la mise sous tension
GB2343787A (en) * 1998-11-06 2000-05-17 United Microelectronics Corp Method of fabricating load resistor
US6140198A (en) * 1998-11-06 2000-10-31 United Microelectronics Corp. Method of fabricating load resistor
GB2343787B (en) * 1998-11-06 2001-01-17 United Microelectronics Corp Method of fabricating load resistor

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