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WO1993004499A1 - Antifusible ameliore et son procede de fabrication - Google Patents

Antifusible ameliore et son procede de fabrication Download PDF

Info

Publication number
WO1993004499A1
WO1993004499A1 PCT/US1992/006913 US9206913W WO9304499A1 WO 1993004499 A1 WO1993004499 A1 WO 1993004499A1 US 9206913 W US9206913 W US 9206913W WO 9304499 A1 WO9304499 A1 WO 9304499A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
barrier layer
interconnection line
amorphous silicon
barrier
Prior art date
Application number
PCT/US1992/006913
Other languages
English (en)
Inventor
Richard Klein
Pankaj Dixit
William P. Ingram, Iii
Laurence H. Cooke
Original Assignee
Crosspoint Solutions, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Crosspoint Solutions, Inc. filed Critical Crosspoint Solutions, Inc.
Publication of WO1993004499A1 publication Critical patent/WO1993004499A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the thickness and the contours of the amorphous silicon layer are known to affect the programming of the antifuse. For example, the thicker the amorphous silicon layer the larger the voltage required to program the antifuse.
  • the amorphous silicon layer is deposited into vias in the intervening silicon dioxide layer which insulates the two interconnection lines from each other. I the amorphous silicon layer is folded, as in this case, the edge effects complicate the electrical performance of the antifuse.
  • the inherent height variation of the vias formed in the intervening silicon dioxide layer adversely affects the thickness uniformity of the amorphous silicon layer at the bottom of the vias.
  • the electrical performance, e.g., the programming voltages, of the resulting antifuses therefore, have large variations. This is undesirable.
  • a second insulating layer 16 of silicon dioxide is deposited on the first insulating layer 19 to cover the first interconnection line 20 and the antifuse stack 23.
  • the insulating layer 16 is formed from doped or undoped silicon dioxide, or silicate or siloxane films or combinations of these materials, to a thickness in the range from 5000 A to 15000 A.
  • the insulating layer 16 is planarized to make the top surface of the layer 16 as flat as possible.
  • a refractory metal may be used for the barrier layers 13 and 15, and optional barrier layers 11 and 17.
  • the term, "refractory metal,” is used to encompass refractory metals, their intermetallics, alloys, silicides, nitrides and combinations thereof.
  • a titanium- tungsten alloy works very well for all the barrier layers 11, 13, 15, and 17. Thicknesses range from 500 to 1500 A.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Structure pour antifusibles formé entre deux lignes métalliques d'interconnexion et procédé de fabrication de ladite structure. Sur une partie de la première ligne métallique d'interconnexion est placé un empilement antifusible pourvu d'au moins une couche de silicium amorphe (14) et d'une première couche barrière (15) située sur ladite couche de silicium amorphe. La première ligne d'interconnexion et l'empilement antifusible sont recouverts d'une couche isolante (16) pourvue d'une traversée (27) qui expose la première couche barrière (15). La seconde ligne d'interconnexion métallique (18, 17) est en contact avec la première couche barrière (15) par l'intermédiaire de la traversée pour former un antifusible entre la première et la seconde ligne métallique d'interconnexion. Une seconde couche barrière (13) placée en-dessous de la couche de silicium amorphe (14) peut constituer une partie de la première ligne d'interconnexion métallique ou une partie de l'empilement antifusible. L'invention concerne également une structure compacte auto-alignée.
PCT/US1992/006913 1991-08-19 1992-08-17 Antifusible ameliore et son procede de fabrication WO1993004499A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US74729891A 1991-08-19 1991-08-19
US747,298 1991-08-19

Publications (1)

Publication Number Publication Date
WO1993004499A1 true WO1993004499A1 (fr) 1993-03-04

Family

ID=25004497

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1992/006913 WO1993004499A1 (fr) 1991-08-19 1992-08-17 Antifusible ameliore et son procede de fabrication

Country Status (1)

Country Link
WO (1) WO1993004499A1 (fr)

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0661745A1 (fr) * 1993-12-21 1995-07-05 Actel Corporation Antifusible entre deux couches de métal avec arrêt de gravure
US5519248A (en) * 1993-07-07 1996-05-21 Actel Corporation Circuits for ESD protection of metal-to-metal antifuses during processing
US5576576A (en) * 1992-11-04 1996-11-19 Actel Corporation Above via metal-to-metal antifuse
US5592016A (en) * 1995-04-14 1997-01-07 Actel Corporation Antifuse with improved antifuse material
WO1997015068A3 (fr) * 1995-10-04 1997-06-19 Actel Corp Dispositif antifusible ameliore, metal sur metal, a traversee, et methodes de programmation
US5670818A (en) * 1990-04-12 1997-09-23 Actel Corporation Electrically programmable antifuse
US5672905A (en) * 1992-08-26 1997-09-30 At&T Global Information Solutions Company Semiconductor fuse and method
US5753528A (en) * 1992-02-26 1998-05-19 Actel Corporation Method of fabricating metal-to-metal antifuse with improved diffusion barrier layer
US5763299A (en) * 1995-06-06 1998-06-09 Actel Corporation Reduced leakage antifuse fabrication method
US5770885A (en) * 1990-04-12 1998-06-23 Actel Corporation Electrically programmable antifuse incorporating dielectric and amorphous silicon interlayers
EP0823733A3 (fr) * 1996-08-08 1998-07-15 Matsushita Electronics Corporation Elément anti-fusible et son procédé de fabrication
US5789795A (en) * 1995-12-28 1998-08-04 Vlsi Technology, Inc. Methods and apparatus for fabricationg anti-fuse devices
US5793094A (en) * 1995-12-28 1998-08-11 Vlsi Technology, Inc. Methods for fabricating anti-fuse structures
US5804500A (en) * 1995-06-02 1998-09-08 Actel Corporation Fabrication process for raised tungsten plug antifuse
US5856234A (en) * 1993-09-14 1999-01-05 Actel Corporation Method of fabricating an antifuse
US5899707A (en) * 1996-08-20 1999-05-04 Vlsi Technology, Inc. Method for making doped antifuse structures
US5913137A (en) * 1993-07-07 1999-06-15 Actel Corporation Process ESD protection devices for use with antifuses
US5963825A (en) * 1992-08-26 1999-10-05 Hyundai Electronics America Method of fabrication of semiconductor fuse with polysilicon plate

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4499557A (en) * 1980-10-28 1985-02-12 Energy Conversion Devices, Inc. Programmable cell for use in programmable electronic arrays
US5070384A (en) * 1990-04-12 1991-12-03 Actel Corporation Electrically programmable antifuse element incorporating a dielectric and amorphous silicon interlayer
US5100827A (en) * 1991-02-27 1992-03-31 At&T Bell Laboratories Buried antifuse

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4499557A (en) * 1980-10-28 1985-02-12 Energy Conversion Devices, Inc. Programmable cell for use in programmable electronic arrays
US5070384A (en) * 1990-04-12 1991-12-03 Actel Corporation Electrically programmable antifuse element incorporating a dielectric and amorphous silicon interlayer
US5100827A (en) * 1991-02-27 1992-03-31 At&T Bell Laboratories Buried antifuse

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
1986 BIPOLAL CIRCUITS AND TECHNOLOGY MEETING, March 1986, BRIAN COOK et al., "Amorphous Silicon Antifuse Technology Fon Biopolar PROMS", pp. 99-100. *

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5770885A (en) * 1990-04-12 1998-06-23 Actel Corporation Electrically programmable antifuse incorporating dielectric and amorphous silicon interlayers
US5670818A (en) * 1990-04-12 1997-09-23 Actel Corporation Electrically programmable antifuse
US5753528A (en) * 1992-02-26 1998-05-19 Actel Corporation Method of fabricating metal-to-metal antifuse with improved diffusion barrier layer
US5672905A (en) * 1992-08-26 1997-09-30 At&T Global Information Solutions Company Semiconductor fuse and method
US5963825A (en) * 1992-08-26 1999-10-05 Hyundai Electronics America Method of fabrication of semiconductor fuse with polysilicon plate
US5576576A (en) * 1992-11-04 1996-11-19 Actel Corporation Above via metal-to-metal antifuse
US5519248A (en) * 1993-07-07 1996-05-21 Actel Corporation Circuits for ESD protection of metal-to-metal antifuses during processing
US5913137A (en) * 1993-07-07 1999-06-15 Actel Corporation Process ESD protection devices for use with antifuses
US5856234A (en) * 1993-09-14 1999-01-05 Actel Corporation Method of fabricating an antifuse
EP0661745A1 (fr) * 1993-12-21 1995-07-05 Actel Corporation Antifusible entre deux couches de métal avec arrêt de gravure
US5592016A (en) * 1995-04-14 1997-01-07 Actel Corporation Antifuse with improved antifuse material
US5804500A (en) * 1995-06-02 1998-09-08 Actel Corporation Fabrication process for raised tungsten plug antifuse
US5763299A (en) * 1995-06-06 1998-06-09 Actel Corporation Reduced leakage antifuse fabrication method
WO1997015068A3 (fr) * 1995-10-04 1997-06-19 Actel Corp Dispositif antifusible ameliore, metal sur metal, a traversee, et methodes de programmation
US5741720A (en) * 1995-10-04 1998-04-21 Actel Corporation Method of programming an improved metal-to-metal via-type antifuse
US5793094A (en) * 1995-12-28 1998-08-11 Vlsi Technology, Inc. Methods for fabricating anti-fuse structures
US5789795A (en) * 1995-12-28 1998-08-04 Vlsi Technology, Inc. Methods and apparatus for fabricationg anti-fuse devices
EP0823733A3 (fr) * 1996-08-08 1998-07-15 Matsushita Electronics Corporation Elément anti-fusible et son procédé de fabrication
US5913138A (en) * 1996-08-08 1999-06-15 Matsushita Electronics Corporation Method of manufacturing an antifuse element having a controlled thickness
US5899707A (en) * 1996-08-20 1999-05-04 Vlsi Technology, Inc. Method for making doped antifuse structures

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