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WO1993012582A1 - Dispositif logique programmable et procedes de fabrication - Google Patents

Dispositif logique programmable et procedes de fabrication Download PDF

Info

Publication number
WO1993012582A1
WO1993012582A1 PCT/US1992/010010 US9210010W WO9312582A1 WO 1993012582 A1 WO1993012582 A1 WO 1993012582A1 US 9210010 W US9210010 W US 9210010W WO 9312582 A1 WO9312582 A1 WO 9312582A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
connection points
links
gate array
cells
Prior art date
Application number
PCT/US1992/010010
Other languages
English (en)
Inventor
Pei-Lin Pai
Fu-Chieh Hsu
Original Assignee
Knights Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Knights Technology, Inc. filed Critical Knights Technology, Inc.
Publication of WO1993012582A1 publication Critical patent/WO1993012582A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • EPROM programmable array logic
  • PLD electrically programmable logic device
  • FPGA field-programmable gate arrays
  • a shorted interlayer connection point 1521 is created through energy-induced reactions between the barrier metal 1525 and the antifuse layer 1524.
  • An alternative energy technique may be employed to create an opened intralayer connection point, for example, employing energy-induced cutting/removal processes.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

Un dispositif programmable à circuits prédiffusés comprend une multiplicité de cellules (50 et 51) dont chacune comprend au moins un dispositif à semi-conducteurs (un transistor, par exemple) (M1-M4); une première multiplicité de liaisons ou de segments d'interconnexion reliant ensemble certains dispositifs choisis parmi les dispositifs à semi-conducteurs (C, D, E, F, G, H); une seconde multiplicité de liaisons ou de segments d'interconnexion (53, U, V, W, X, Y, Z), et une multiplicité de points de connexion reliant certaines liaisons choisies de la première multiplicité de liaisons, à certaines liaisons choisies de la seconde multiplicité de laiisons (L1-L26).
PCT/US1992/010010 1991-12-13 1992-11-19 Dispositif logique programmable et procedes de fabrication WO1993012582A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US80753491A 1991-12-13 1991-12-13
US07/807,534 1991-12-13

Publications (1)

Publication Number Publication Date
WO1993012582A1 true WO1993012582A1 (fr) 1993-06-24

Family

ID=25196597

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1992/010010 WO1993012582A1 (fr) 1991-12-13 1992-11-19 Dispositif logique programmable et procedes de fabrication

Country Status (1)

Country Link
WO (1) WO1993012582A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0681329A3 (fr) * 1994-05-01 1996-11-13 Quick Tech Ltd Réseau logique personnalisable.
DE102014202116B4 (de) * 2013-03-15 2017-03-09 Globalfoundries Inc. Verfahren zum Bilden eines Standardtransistorlayouts unter Verwendung von DSA-Vorstrukturen und einer Standardmetallschicht und Vorrichtung mit einem Standardtransistorlayout

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3987287A (en) * 1974-12-30 1976-10-19 International Business Machines Corporation High density logic array
US4536949A (en) * 1983-05-16 1985-08-27 Fujitsu Limited Method for fabricating an integrated circuit with multi-layer wiring having opening for fuse
US4646266A (en) * 1984-09-28 1987-02-24 Energy Conversion Devices, Inc. Programmable semiconductor structures and methods for using the same
US4847810A (en) * 1986-04-22 1989-07-11 Sharp Kabushiki Kaisha Memory having redundancy circuit
US4968643A (en) * 1986-08-12 1990-11-06 Fujitsu Limited Method for fabricating an activatable conducting link for metallic conductive wiring in a semiconductor device
US5081059A (en) * 1988-06-16 1992-01-14 Fujitsu Limited Method of forming semiconductor integrated circuit using master slice approach
US5083181A (en) * 1987-11-27 1992-01-21 Hitachi, Ltd. Semiconductor integrated circuit device and wiring method thereof
US5136356A (en) * 1989-04-19 1992-08-04 Seiko Epson Corporation Semiconductor device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3987287A (en) * 1974-12-30 1976-10-19 International Business Machines Corporation High density logic array
US4536949A (en) * 1983-05-16 1985-08-27 Fujitsu Limited Method for fabricating an integrated circuit with multi-layer wiring having opening for fuse
US4646266A (en) * 1984-09-28 1987-02-24 Energy Conversion Devices, Inc. Programmable semiconductor structures and methods for using the same
US4847810A (en) * 1986-04-22 1989-07-11 Sharp Kabushiki Kaisha Memory having redundancy circuit
US4968643A (en) * 1986-08-12 1990-11-06 Fujitsu Limited Method for fabricating an activatable conducting link for metallic conductive wiring in a semiconductor device
US5083181A (en) * 1987-11-27 1992-01-21 Hitachi, Ltd. Semiconductor integrated circuit device and wiring method thereof
US5081059A (en) * 1988-06-16 1992-01-14 Fujitsu Limited Method of forming semiconductor integrated circuit using master slice approach
US5136356A (en) * 1989-04-19 1992-08-04 Seiko Epson Corporation Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0681329A3 (fr) * 1994-05-01 1996-11-13 Quick Tech Ltd Réseau logique personnalisable.
US5861641A (en) * 1994-05-01 1999-01-19 Quick Technologies Ltd. Customizable logic array device
DE102014202116B4 (de) * 2013-03-15 2017-03-09 Globalfoundries Inc. Verfahren zum Bilden eines Standardtransistorlayouts unter Verwendung von DSA-Vorstrukturen und einer Standardmetallschicht und Vorrichtung mit einem Standardtransistorlayout

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