WO1993016493A1

WO1993016493A1 - Variable electrical impedance termination for leads on integrated circuit chips

Info

Publication number: WO1993016493A1
Application number: PCT/US1993/001233
Authority: WO
Inventors: David Reynolds
Original assignee: Analog Devices, Inc.
Priority date: 1992-02-11
Filing date: 1993-02-11
Publication date: 1993-08-19

Abstract

An integrated circuit chip is provided with at least a component on it. The component may be, for instance, an analog-to-digital converter or a digital-to-analog converter. The component has at least one connection leading off the chip to facilitate communication between the component and an external device. The chip additionally includes an active element, such as a variable resistor, for compensating for non-ideal electrical impedance experienced by signals at said connection.

Description

VARIABLE ELECTRICAL IMPEDANCE TERMINATION FOR LEADS ON INTEGRATED CIRCUIT CHIPS

Field of the Invention

This invention relates generally to termination strategies for electrical leads on integrated circuit (IC) chips and, more particularly, to variable electrical impedance termination strategies for electrical leads on IC chips.

Description of the Prior Art

Many video systems include IC chips that convert digital data into analog signals representing information such as color and luminance. These chips are known by many different names, including RAM digital-to-analog converters (DACs), video DACs or color pallette DACs. The output signals from such a type of chip are typically forwarded to a video display which generates a video image from the signals.

A typical configuration for a DAC chip 10 is shown in Fig. 1. The chip 10 includes three DACs 12a, 12b and 12c which generate a blue output signal, a green output signal and' a red output signal, respectively. These color output signals are passed to the video display 18 through output terminals 15a, 15b and 15c which are provided on the chip 10. The output signals form the color components for generating a full color image on the video display 18. Typically, the DAC chip 10 is mounted on a printed circuit board 11. The interface from the printed circuit board 11 to the video display 18 is realized through a cable 23 or other suitable connection means. The cable 23 includes conductors 17a, 17b and 17c that run from respective DACs 12a, 12b and 12c on the printed circuit board 11 to the video display 18. As such, each DAC output is doubly terminated (i.e., once on the circuit board 11 and once on the video display 18). The schematic of Fig. 1 shows the termination resistors 14a, 14b and 14c, which are used for the circuit board terminations and resistors 16a, 16b and 16c, which are used for video display terminations.

DACs 12a, 12b and 12c are provided with bias circuitry 37 that provide bias voltages. Fig. 2 shows a more detailed depiction of the circuit employed in the bias circuitry 37. Bias circuitry 37 includes a reference voltage source 39 for supplying a reference voltage, V -. The voltage source 39 is connected to a first input of a high gain operational amplifier (op amp) 19. A feedback leg 29 is connected to a second input of the op amp 19. The output of the op amp 19 is, in turn, connected to the gate of a p-channel.-MOSFET 13. The source of MOSFET 13 is coupled to a voltage, V , whereas the drain of MOSFET 13 is connected to feedback leg 29, which has a resistor 14 connected to it. The gate of the MOSFET 13 is connected to the DAC 12a.

During operation, the bias circuitry 37 operates to provide a bias voltage, ^v _a^ __{as '} to DAC 12a. In particular, op amp 19 generates an output that is indicative of the difference between the reference voltage V _f from voltage source 39 and the voltage on feedback line 29. This output is connected to the gate of MOSFET 13 to regulate the amount of current that flows through the MOSFET and out its drain. The gate of the MOSFET 13 is connected to DAC 12a to provide the bias voltage V., . . The drain of MOSFET 13 is connected in a negative feedback arrangement with a resistor 14 to the second input of op amp 19.

These DAC chips suffer three primary drawbacks. First, the output current for each of the respective DACs 12a, 12b and 12c varies by a small degree due to non-idealities. The system, however, does not account for such variations in output currents. Specifically, the system is designed with the assumption that the output currents from the DACs are equal. The resulting output current discrepancies create error between the color achieved on the video display and the desired color. In particular, to obtain a video output of a specific color, the system determines the appropriate amount of red, green and blue that needs to be generated to produce the color. In performing the calculations for determining how much red, green and blue should be included in the output, the system assumes that the output currents for the respective DACs are equal. Hence, when output currents are not equal, the amounts of blue, green and red that are actually realized are incorrect, and, therefore, the displayed output color is not the desired color. -_. -

A second difficulty suffered with previously known DAC chips is that the electrical impedance of the chip may differ substantially from the electrical impedance of the conductors 17a, 17b and 17c. This electrical impedance mismatch causes reflection of the video signals, which may produce ghost images on the video display 18.

A third difficulty with conventional DAC chips concerns resonance. Many prior art DAC chips may be modeled by the circuit shown in Fig. 3. In particular, they act like a conventional RLC circuit which experiences oscillations. In accordance with this model, the high impedance current source 60 represents parasitic capacitance of the chip, bond wire package and board traces. Further, the inductor 64 represents the bond wire inductance of the package,, and the capacitor 66 represents capacitances of the system such as pin-to-pin capacitance and printed circuit board capacitance. Lastly, the resistor 63 represents the termination resistors on the board and monitor (comparable to resistors 16a, 16b and 16c of Fig. l). A problem with this RLC circuit is that it resonates. Specifically, resonance may occur when a step,change arises in the output excitation. The resonance produces a high frequency ringing on the cable interconnecting the monitor with the circuit board. This ringing interferes with the provision of the desired color outputs.

Efforts to date at overcoming these problems have attempted to solve them by employing corrective passive fixed resistance elements off the DAC chip. In particular, these attempts have relied on fixed resistance elements such as off-chip resistors to try to resolve impedance mismatches. Such resistors have generally been low resistance resistors which are not usually suitable for on-circuit integration.

These problems are not unique to DAC chips; rather other types of chips having different kinds of components on them suffer from some or all of these problems. For instance, analog-to-digital converter (ADC) chips may suffer such problems.

Summary of the Invention

The foregoing problems are overcome in a chip, such as a video chip, that includes at least one component on it such as a digital-to-analog converter (DAC) or an analog to digital converter (ADC) . A connection is provided for each connection to the component to an external element off the chip to enable electrical signals to travel between the components on the chip and the external element. The chip further includes an active element for adjusting the electrical impedance at the connection such that mismatches among the/outputs are substantially reduced. These active elements may be variable resistors. The variable resistors may be implemented using a plurality of MOSFETs.

The active element may be used to remove output current mismatches. An active element may be provided at each output, or alternatively, active elements may be provided only at selected outputs. The active element may also be used to compensate for output current mismatches among components.

In order to compensate adequately for these mismatches, the appropriate level of electrical impedance of each of the relevant connections must first be determined. This may be determined by measuring devices that measure the electrical signals on the connectors. These measurements are processed to determine the diferences in electrical impedance and how to compensate for these differences. Once this is determined, the active elements, such as variable resistors, are set to compensate for the mismatches. Once the active elements have been appropriately set, the mismatches in output voltages are significantly reduced or eliminated.

The component formed on a chip may have a biasing circuit for providing a bias voltage to the component. Similarly, a second biasing circuit may be provided for the active element to supply a bias voltage to the active elements. Preferably, the second biasing circuit is coupled to the first biasing circuit to compensate for the biasing voltage being supplied to the component.

Embodiments of the present invention will be described below in more detail with reference to the drawing.

Brief Description of the Drawing

In the drawing,

Fig. 1 is a schematic diagram of a prior art DAC chip connected to a video display; Fig. 2 is a schematic diagram of the prior art bias circuitry for the chip of Fig. l;

Fig. 3 is a schematic diagram for modeling the behavior of a prior art DAC chip;

Fig. 4 is a schematic diagram of a DAC chip connected to video display in accordance with the present invention;

Fig. 5 is a schematic diagram of a variable resistor circuit and control circuitry for use in the DAC chip of Fig. 4; and

Fig. 6 is a block diagram of the control circuitry of Fig. 5.

Figs. 7a and 7b show alternative embodiments of the bias circuitry for the chip of Fig. 4.

Fig. 8 is a schematic diagram of an alternative embodiment of the present invention employed in an ADC chip.

Detailed Description

A first embodiment of the present invention will be described initially with reference to Figs. 4 and 5. The present invention provides a means for compensating for mismatches in the output currents of devices, such as DACs 22a, 22b and 22c, on a chip 30. It should be appreciated that the chip 30 need not include three DACs as shown in Fig. 4. The present invention also encompasses chips employing more or fewer DACs and encompasses chips employing other types of components which are not DACs. For each DAC 12a, 12b and 12c, at least one active element, like element 28a, 28b or 28c, may be employed to make the output currents of the converters substantially equal. Alternatively, active elements may be provided for only selected DACs. As shown in Fig. 4, the active elements are variable resistors 28a, 28b and 28c which are connected to the outputs of the respective DACs 12a, 12b and 12c. These variable resistors 28a, 28b and 28c are on the chip as opposed to being on the printed circuit board 11. The DAC chip 30 is connected via conductors 17a, 17b and 17c or other suitable connecting means to the video display monitor 18. These conductors may be incorporated together in a cable 23. The variable resistors 28a, 28b and 28c not only resolve mismatches between DAC outputs but also compensate for electrical impedance mismatches between the chip 30 and the conductors 17a, 17b and 17c. The termination resistors at the video display monitor are shown as resistors 16a, 16b and 16c in Fig. 4.

-The biasing circuitry provided to bias the variable resistors 28a, 28b and 28c is the same circuitry that is used to bias the respective DACs 12a, 12b and 12c. This bias circuitry will be described in more detail below.

Separate control circuitry 41a, 41b and 41c is provided for each of the variable resistors 28a, 28b and 28c. The control circuitry will be described in more detail below, but it is worth noting that each set of control circuitry 41a, 41b and 41c includes a respective measuring device 95a, 95b and 95c. The respective DAC outputs are measured by these measuring devices 95a, 95b and 95c. These devices measure the voltage at the outputs of the DACs. A suitable device for measuring the voltages at the DAC is an ADC that produces a digital output indicative of the analog voltage input to the ADC. This ADC may be located on the circuit board. Other suitable devices are photodetectors that measure the intensity of the output of the video display 18 or devices on the board that measure the intensity of the outputs from the DACs. Such devices need not reside on DAC chip 30 as shown in Fig. 4, but rather may reside on the video display 18. The outputs from the measuring devices 95a, 95b and 95c are used to generate control signals to the variable resistors, as will be discribed in more detail below.

As an example, suppose that the outputs at full scale for DACs 12a, 12b and 12c are 25 milliamps, 26 milliamps and 27 milliamps, respectively. These DACs are of similar design and are as similar as fabrication technology can achieve. Consequently, the full scale output differences are due primarily to limits in fabrication accuracy. To compensate for these differences, the variable resistors 28a, 28b and 28c are set by control signals from control circuitry 41a, 41b and 41c, respectively, to resistances of approximately 76 ohms, 75 ohms and 74 ohms. By compensating for the Output voltage mismatches, this system encourages truer color output signals than can be realized in similar prior art systems. Moreover, the variable resistors 28a, 28b and 28c may be set so as to compensate for electrical impedance mismatch between the chip 30 and each of the conductors 17a, 17b and 17c, to reduce the incidence of ghost images and the like. Fig. 5 depicts a circuit forming a variable resistor circuit that is suitable for integration into the DAC chip 20 of Fig. 4 as one of the active elements 28a, 28b and 28c. It is designated as variable resistor 28a merely for illustrative purposes. Fig. 5 also shows control circuitry 41a.* The variable resistor circuit has three branches connected to a supply voltage. Each branch is coupled to a drain of a respective n-channel MOSFET 32, 34 and 36. The respective sources of MOSFETs 32, 34 and 36 are all connected to corresponding second source potentials or grounds. Each of the MOSFETs 32, 34 and 36 has a different cross-sectional area for its channel. The differences in channel area among the MOSFETs 32, 34 and 36 cause the MOSFETs to exhibit different drain to source resistances for the same gate-to-source voltage, V_gs.

A bias voltage, V _as is applied to the gate of each of the n-channel MOSFETs 32, 34 and 36, as shown in Fig., 5. The bias voltage ^v-_κ-;_as biases the n-channel MOSFETs 32, 34 and 36 into their linear regions of operation. This bias voltage ^v-_{b as} serves as a bias for controlling the amount of resistance provided by the variable resistor circuit. The resistance provided by the circuit is also affected by which MOSFET(s) are selected. Selection of MOSFET(s) is realized by controlling the switches 40, 42 and 44.

The switches are coupled to the bias voltage

V,bi.as 48. These switches 40, 42 and 44 control the connection of the respective MOSFETs 32, 34 and 36 to the Vb,i•as 48 line. By^J controlling³ these connections to the bias line, switches 32, 34 and 36 dictate whether the MOSFETs 32, 34 and 36 are active or not. The switches 40, 42 and 44 are controlled by control signals sent over lines 43a, 43b and 43c, respectively. These control signals originate from the control circuitry 41a.

Additional MOSFETs 31, 33 and 35 are provided to prevent MOSFETs 32, 34 and 36, respectively, from floating when the switches 40, 42 and 44, respectively, are open. These MOSFETs 31, 33 and 35 are connected to the lines 43a, 43b and 43c, respectively, which carry the control signals. The sources of these MOSFETs 31, 33 and 35 are coupled to ground.

The system selects a particular branch of the circuit (or parallel branches of the circuit) by control signals 43a, 43b and 43c (which are shown as a single line in Fig. 4) and, thus, also selects one (or more) MOSFET(s) 32, 34 and 36. The switch for the selected branch(es) is closed while the switches for the remaining branch(es) remains open. As discussed above, each MOSFET 32, 34 or 36 provides a different resistance for the same value of V, D1.3._S. Thus, the selection of a particular branch(es) results in a selection of a particular resistance.

The control signals on lines 43a, 43b and 43c originate from the control circuitry 41a. A more detailed view of the control circuitry 41a is shown in Fig. 6. The control circuitry includes the measuring device 95a as discussed above. A measuring device 95a receives video output from DAC 12a and generates an indication of the output which is forwarded to a comparator 81. The comparator 81 compares this output with a reference value indicative of the desired output. The comparator 81 generates an indication of the difference between the reference valve and the measured output and forwards this to the control signal generator 83. The control signal generator 83 generates an appropriate set of control signals to eliminate mismatches between the actual output and the reference valve for the respective colors. These control signals are passed to the variable resistor 28a as discussed with reference to Fig. 5.

Fig. 7a illustrates a first embodiment of the bias circuitry 22a. In accordance with this first embodiment, bias circuitry 37b and 37c have a circuit arrangement like that of bias circuitry 37a. This circuitry 37a includes the components 13a, 14a, 19a, 29a and 39a which were included in the bias circuitry of the prior art (described in the background section with reference to Fig. 1). The details of operation of these components are provided above and will not be repeated here. In addition to these components, the bias circuitry 37a includes a second p-channel MOSFET 80a connected with the first MOSFET 13a. Specifically, the gate of MOSFET 13a is connected to the gate of MOSFET 80a, and the gate of MOSFET 80a is connected to the bias voltage input of the DAC 12a. The source of the MOSFET 80a is connected to the supply voltage _D;D, while the drain of MOSFET 80a is connected to an n-channel MOSFET 82a and to a branch 84a. Lastly, branch 84a leads to the first input of an op amp 86a. The gate of n-channel MOSFET 82a is connected to the output of the op amp 86a. In addition, the source of MOSFET 82a is tied to ground. The other input to the op amp 86a is connected to line 88a, which leads to the reference voltage source 39a. As such, the op amp 86a receives an input on line 84a which is indicative of the voltage across the second MOSFET 82a. The voltage generated at the first input of the op amp 86a is compared to the reference voltage, -, provided at the second input. The output of the op amp 86a is indicative of the difference between the reference voltage and the voltage across MOSFET 82a. This output is coupled to the gate of second MOSFET 82a and serves as a bias for the variable resistor 28a.

The additional components added into the bias circuitry 37a serve to monitor the bias voltage being supplied to the DAC 12a. This bias voltage is then compared to the reference voltage, V ,, to generate an appropriate bias signal for the variable resistor 28a.

Fig. 7b depicts a second alternative embodiment of the bias circuitry 37a. In this second embodiment, bias circuitry 37b and 37c have a circuit arrangement like that of bias circuitry 37a. This alternative embodiment differs from that of the first embodiment of Fig. 6a in that it employs a current mirror. In particular, the second MOSFET 80a is employed as previously described; however, the drain of MOSFET 80a passes to an n-channel MOSFET 82a and to a branch 100a connected in a conventional current mirror configuration so that the current on line 104a mirrors that flowing through the second MOSFET 80a. This line 104a connects to the bias input for the variable resistor 28a.

The present invention helps to diminish the resonant effects experienced by the DAC circuits. Specifically, by bringing the variable resistor onto the chip, the nature of the circuit is changed so that only part of the DAC output current goes to reactive elements, whereas in the prior art systems all of the output current goes to reactive elements (i.e.., the inductive bond wires and the capacitance of the circuit board) . The portion of the DAC output going to variable resistors in the present invention cannot resonate, and the present invention damps resonant effects. Thus, the non-ideal behavior (i.e., resonances) of the circuit is lessened.

The foregoing description explains the integration of the variable resistors into a DAC chip. However, the present invention may also be employed in other varieties of chips. For instance, as depicted in Fig. 8, a variable resistor 76 or other suitable active element may be integrated into an ADC chip 70 having at least one ADC on it. ADC chip 70 shown in Fig. 7 has two ADCs 72 and 74. These ADCs 72a and 72b receive input from off-chip on terminals 90a and 90b, respectively. These terminals 90a and 90b are, in turn, coupled to respective external electrical conductors 94a and 94b. The input of ADC 74 is connected to a passive fixed value resistor 78. The input of the other ADC 72, however, is coupled to a variable resistor 76. The variable resistor 76 serves much the same role served by the active element in the previously described alternative embodiment of Fig. 4. In particular, the variable resistor 76 helps to eliminate a mismatch in signal amplitude experienced at the inputs to the ADC 72a and 72b. As was explained above with respect to the DAC outputs, inputs to different ADCs may have different electrical impedances due to non-idealities. In order to compensate for these non-idealities, the variable resistor 76 is set to a resistance value so that the resulting input signals experienced by the inputs of the different ADCs 72a and 72b are the same. Moreover, the variable resistor 76 may be used to compensate for any electrical impedance mismatch between the electrical impedance of electrical conductor 94a and the electrical impedance of the ADC chip 70. This chip may include a servo loop similar to those shown in Figs. 7a and 7b for adjusting the variable resistor 76.

The embodiment of Fig. 8 depicts only one variable resistor 76. It should be appreciated, nevertheless, that the resistor 78 may also be a variable resistor rather than a passive resistor. Furthermore, even though plural ADCs are shown on ADC chip 70 in Fig. 7, this invention additionally encompasses embodiments where only a single ADC is positioned on a chip and, likewise, encompasses instances wherein more than two ADCs are situated on the chip.

While the present invention has been explained with respect to preferred embodiments shown by way of example only, those skilled in the art will know of other alternative embodiments which do not depart from the spirit and scope of the invention as defined in the appended claims. For instance, the variable resistors may be used with components other than DACs or ADCs, and the variable resistors may be incorporated in chips other than video chips; Still further, the variable resistors may be positioned elsewhere on the chip other than at the outputs of ADCs or the outputs of DACs. The invention may have equal applicability to other on-chip components. Furthermore, MOS components need not be used, rather other suitable components such as JFET components may be equally viable. The examples are, thus, not intended to be limiting, and the invention is defined only in the appended claims and equivalents thereto.

I claim:

Claims

1. An integrated circuit chip, comprising: a) at least one component formed on said chip; b) a connection for connecting said component to an external element so that electrical signals may travel between said external element and said component; and c) an active element formed on said chip for adjusting output current from said component at said connection.

2. An integrated circuit chip as recited in Claim 1 wherein said component comprises a digital to analog converter.

3. An integrated circuit chip as recited in Claim 1 wherein said component comprises an analog to digital converter.

4. An integrated circuit chip as recited in any of Claims 1, 2 or 3 wherein said active element comprises an electrically variable resistor.

5. An integrated circuit chip as recited in Claim 1 wherein said chip comprises a plurality of additional components, each having a connection for facilitating electrical signals to travel between said additional component and an external component, and further comprises, for each additional component, at least one active element for adjusting the output current from said additional component at the connection of said additional component.

6. An integrated circuit chip as recited in Claim 5 wherein a separate active element is provided for each additional component.

7. An integrated circuit chip as recited in Claim 1 further comprising a component biasing circuit for applying a bias voltage to the one component.

8. An integrated circuit chip as recited in Claim

7 further comprising a measuring device for measuring the electrical signals on said connection and further comprising a controller for adjusting the active element in response to measurements made by said measuring device.

9. An integrated circuit chip as recited in Claim

8 further comprising an additional biasing circuit for providing a bias voltage a the active element wherein this biasing circuit is coupled to the biasing circuit so that the additional biasing circuit compensates for the bias voltage provided to the component.

10. An integrated circuit chip as recited in Claim 1 further comprising a measuring device for measuring the electrical signals on said connection and further comprising a controller for adjusting the active element in response to measurements made by said measuring device.

11. An integrated circuit chip, comprising: a) at least one digital to analog converter, each converter having a separate output connection leading off the chip for carrying a respective output signal; and b) an active element for adjusting the output currents of said output signals at said output connections to substantially reduce output current mismatches among said output connections.

12. An integrated circuit chip as recited in Claim 11 wherein said active element comprises at least one electrically variable resistor.

13. An integrated circuit chip as recited in Claim 11 wherein a separate active element is provided for each output connection.

14. An integrated circuit chip as recited in claim 11 having a plurality of digital to analog converters.

15. An integrated circuit chip as recited in Claim 11 further comprising a first biasing circuit for applying a bias voltage to the digital to analog converter.

16. An integrated circuit chip as recited in Claim

15 further comprising a measuring device for measuring the electrical signals on said output connection and further comprising a controller for adjusting the active element in response to the measurements by said measuring device.

17. An integrated circuit chip as recited in Claim

16 further comprising a second biasing circuit for providing a biasing voltage to the active element wherein this second biasing circuit is coupled to the first biasing circuit so that the second biasing circuit compensates for the bias voltage provided to the digital to analog converter.

18. An integrated circuit chip as recited in Claim 11 further comprising a measuring device for measuring the electrical signals on said output connection and further comprising a controller for adjusting the active element in response to measurements by said measuring device.

19. An integrated circuit chip, comprising: a) at least one analog to digital converter, each converter having a separate input connection leading off the chip for carrying a respective input signal; and b) active elements for adjusting the input currents at the connections to substantially diminish mismatches in the input currents at said connections.

20. An integrated circuit chip as recited in Claim 11 wherein the active elements comprise at least one electrically variable resistor.

21. An integrated circuit chip as recited in Claim 11 wherein a separate active element is provided for each converter.

22. An integrated circuit chip as recited in Claim 19 having a plurality of analog to digital converters.

23. An integrated circuit chip as recited in Claim 1 further comprising a first biasing circuit for applying a bias voltage to the analog to digital converter.

24. An integrated circuit chip as recited in Claim 7 further comprising a measuring device for measuring the electrical signals on said input connection and further comprising a controller for adjusting the active element in response to measurements by said measuring device.

25. An integrated circuit chip as recited in Claim 24 further comprising a second biasing circuit for providing a bias voltage to the active element wherein this second biasing circuit is coupled to the first biasing circuit of the at least one component so that the second biasing circuit for the active element compensates for the bias voltage provided to the analog to digital converter.

26. An integrated circuit chip as recited in Claim 1 further comprising a measuring device for measuring the electrical signals on said output connection and further comprising a controller for adjusting the active element in response to measurements by said measuring device.

27. A method of reducing electrical impedance mismatches on a chip having at least one component formed on chip, wherein each component has a connection for connecting- said component to an external element so that electrical signal may travel between said external element and said component it, and each connection has an active element for adjusting the electrical impedance at the connection, comprising the steps of: a) determining the electrical impedance at each connection to determine if there are any mismatches in electrical impedance among the connections; and b) setting the active elements to compensate for any mismatches in electrical impedance among the connections.

28. A method as recited in claim 27 wherein the converters are analog to digital converters.

29. A method as recited in claim 27 wherein the converters are digital to analog converters.