WO1995004405A1

WO1995004405A1 - Method and apparatus for charge pump with reduced charge injection

Info

Publication number: WO1995004405A1
Application number: PCT/US1994/008422
Authority: WO
Inventors: Richard F. Lyon
Original assignee: Apple Computer, Inc.
Priority date: 1993-07-30
Filing date: 1994-07-26
Publication date: 1995-02-09
Also published as: AU7373794A

Abstract

Circuits and methods for substantially reducing charge injection in charge pump phase-locked loop circuits are disclosed. In one embodiment, first p- and n-type metal-oxide-semiconductor (MOS) trnsistors biased to operate as switches are respectively coupled to supply voltage and ground, and are controlled by first and second control signals. Second p- and n-type transistors biased to operate as current sources are respectively coupled between each first p- and n-type transistor and an output node, and are controlled by third and fourth control signals. Inherent stray capacitances to ground are present between the first and second p-type transistors, and between the first and second n-type transistors, due to device construction. When turned on, the switch transistors couple the sources of second p- and n-type transistors to the voltage supply and ground, respectively. By operating the source transistors below threshold in combination with the interchanged positions of the source and switch transistor pairs, two advantages over prior art charge pump implementations may be obtained. First, the interchanged position of the source and switch transistors ensures that excess charge injection (i.e., the current spike) is virtually eliminated whenever the switch transistors are turned on. Second, by operating the source transistors within the subthreshold region of MOS transistor conduction, the charge pump will operate with smaller voltage swings, and accordingly charge injection at turn-off will be even further reduced. Charge pump output current quickly and smoothly approaches the intended design level, with virtually no charge injection. A small amount of excess charge is seen as a small delay in turning off the current source transistors.

Description

METHOD AND APPARATUS FOR CHARGE PUMP WITH REDUCED CHARGE INJECTION

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to electronic devices. More particularly, the present invention relates to a switched current source having reduced charge injection for use in a phase-locked loop.

2. Art Background

Phase-locked loop (PLL) circuits, including charge pump PLLs, are commonly encountered in electronic control circuits, signal measurement circuits, and signal detection systems. As shown in. Figure la, a typical charge pump PLL arrangement includes a phase detector 1, a charge pump 2, a loop filter 3, and a voltage-controlled oscillator (VCO) 4, wherein an oscillator output signal is compared in phase to an input signal applied to the phase detector 1. Any resulting phase difference between the input signal and the oscillator output is filtered by the loop filter 3, and is fed back as a VCO control voltage ^control ^{to ac}*j^ust the frequency of the VCO 4. Alternatively as illustrated in Figure lb, a charge pump PLL may include a delay line 4a instead of VCO 4, as taught by Lofgren. The alternative PLL arrangement (Figure lb) will be described in more detail in connection with Figure 2c. In charge pump PLLs, time intervals (phase error, essentially) detected by phase detector 1 between the PLL input and the VCO output signals are converted into a corresponding quantity of charge by charge pump 2 according to a pair of control signals UP and DOWN supplied to charge pump 2 by phase detector 1. The charge is subsequently integrated by the loop filter 3 to form the VCO control voltage V_controι governing the VCO. Operation of charge pump PLLs is well known in the art, having been described, for example, by Gardner, Charge Pump

Phase-Lock Loops, IEEE Transactions on Comm., Vol. Com-28, No. 11, pp. 1849-58 (1980). As described by Gardner and as shown in Figure 2a, an idealized view of charge pump 2 may consist of two current sources

5 and 6 and two switches 9 and 10 coupled in series between a voltage supply (+V) and ground. In particular, current source 5 generates

(sources) current, whereas current source 6 absorbs (sinks) current. The current sources 5 and 6 are respectively located adjacent to the voltage supply and ground rails, and an output signal is taken from an output point 11 located between switches 9 and 10. A loop filter, comprising an integrating capacitor 12 coupled between the output point 11 and ground, produces an output VCO control voltage V_controι. Switches 9 and 10 are respectively controlled by a pair of switch control signals UP (13) and DOWN (14), which are produced by the phase detector (not shown). UP and DOWN switch control signals 13 and 14 open and close switches 9 and 10 respectively to either charge up or down integrating capacitor 12, depending on the time difference (i.e., the phase difference) detected by the phase detector between leading edges of the input signal to the PLL and the output of the VCO, i.e., whether the input signal leads or lags the VCO frequency. The idealized arrangement shown in Figure 2a is not intended as a functional representation of an actual PLL charge pump and loop filter, but rather as a conceptual model illustrating that opening and closing switches 9 and 10 causes charge to accumulate or decline on capacitor 12. In the idealized arrangement shown in Figure 2a, accumulation or depletion of charge on capacitor 11 may be described by ΔQ = i -Δt, where Q is charge, i is either current i_up or -i_{£jo n} respectively sourced or sinked by current sources 5 or 6, and Δt is the time period wherein switch 9 or 10 is turned on as controlled by the UP or DOWN signals and corresponding to the time differential between leading edges of the input signal and the VCO output signal. It can be seen that any phase error (or, time differential Δt) detected by the phase detector will cause some charge Q to accumulate on or drain from capacitor 12, according to the sign of the phase difference. Accordingly, the loop filter arrangement shown in Figure 2a is said to "pump" charge proportional to phase error (i.e., phase difference) between the input signal and the output signal.

The switch and current source combinations of the idealized charge pump (2) shown in Figure 2a have been implemented according to the arrangement shown in Figure 2b. In Figure 2b, a pair of p-type and n-type metal-oxide-semiconductor (MOS) transistors are coupled in series between a supply voltage and ground to form a charge pump 14.

Specifically, a p-type transistor 15 and an n-type transistor 16 physically implement current switches 9 and 10 of Figure 2a. The output of the charge pump 14 is taken from an output point 17 between the transistors 15 and 16. A loop filter, typically comprising an integrating capacitor 20, is coupled between the output point 17 and ground, as in the case of the idealized PLL circuit shown in Figure 2a. The loop filter (capacitor 20) produces as an output VCO control voltage V_controι.

Current switch transistors 15 and 16 are controlled by a pair of digital control signals /UP (18) and DOWN (19), provided by the phase detector when comparing an input signal to the phase detector and an output signal from the VCO. /UP is an active low logic signal applied to the p- type transistor 15, whereas DOWN is an active high logic signal applied to the n-type transistor 16. Because transistors 15 and 16 simply operate as switches, an external current limiting means, e.g., a resistor 21, typically must be inserted between the output point of the transistors and the integrating capacitor 20 to limit the current flowing to charge (f_Up), or discharge 0^'d_own)_/ capacitor 20. In the charge pump arrangement (14) shown in Figure 2b, the current flowing through the current limiting resistor 21 at any given time will depend upon the instantaneous state of the loop filter, i.e., upon the quantity of charge currently stored in capacitor 20, when the switching event occurs. For example, if capacitor 20 contains a large quantity of charge, then when transistor 15 turns on, charge will accumulate slowly, or perhaps not at all. Alternatively, if capacitor 20 contains a small quantity of charge, then when transistor 15 turns on, charge will accumulate more rapidly.

Referring now to Figure 2c, an improved prior art current source and charge pump arrangement 35 over that shown in Figure 2b is illustrated according to U.S. Patent No. 4,922,141 to Lofgren, et al. In Figure 2c, the charge pump of Lofgren is used in a delay line arrangement to induce variable precise delays, as previously suggested by Figure lb. The arrangement (35) of Lofgren shown in Figure 2c consists of a pair of p-type and n-type MOSFET transistors 58 and 60 coupled drain-to-drain with a resistor 62 therebetween as a current source reference. A pair of input charge pump control signals /UP (63) and DOWN (65) are respectively supplied to a complementary pair of p- type and n-type current switch transistors 66 and 70 switchably coupling a complementary pair of p-type and n-type current source transistors 64 and 68 to an output node 67. Current source transistors 64 and 68 have their sources coupled to alternative voltage supply rails +V and ground, and have their gates respectively coupled to the reference current source transistors 58 and 60 in a current mirror configuration to supply charging current to a loop filter (capacitor 36) coupled between output point 67 and ground. The loop filter (capacitor 36) produces as an output control signal VCP. In fact, the arrangement according to Lofgren produces two complementary control signals of opposite polarity, but for present purposes the charge pump shown in Figure 2b is illustrated in terms of only one output control signal VCP. Capacitor 36 serves to accumulate and deplete charge to vary the magnitude of output control signal VCP subsequently provided to a delay circuit (e.g., delay line 5, Figure lb) to adjust the amount of delay desired. Thus configured, the charge pump and loop filter arrangement 35 of Lofgren shown in Figure 2c does not require the external current-limiting resistor 18 shown in Figure 2b, because the current source transistors 64 and 68 themselves limit the current to the output VCP at capacitor 36 while the corresponding switch transistors (transistors 66 and 70) are turned on.

In either of the physical implementations of charge pump arrangements 14 (Figure 2b) or 35 (Figure 2c), whenever the phase detector detects a phase difference between an input signal and the VCO output signal (Figure lb), or between an input signal and a delayed oscillator signal (Figure lc), the phase detector will seek to increase or decrease the control voltages V_controι (Figure 2b), or VCP (Figure 2c).

For example, in Figure 2c, VCP is increased or decreased by turning on the corresponding current switch (transistors 66 or 70) to couple the appropriate current source (transistors 64 or 68) to the output. Whenever such an adjustment to VCP is made, a current spike will be delivered to integrating capacitor 36 whenever the corresponding current switch transistor 66 or 70 is turned on. The current spike, also referred to as charge injection, is due to stray capacitance inherently existing between the active region and the substrate in MOS devices used to implement the charge pumps. For the charge pump 35 shown in Figure 2c, a first stray capacitance 27 is present between the first current source and switch transistors (64 and 66), and a second stray capacitance 28 is present between the second current source and switch transistors (68 and 70). As shown, stray capacitances 27 and 28 represent the above-noted stray isolation junction capacitance from the active region to the substrate in the drain-to-source regions of adjacent current source and current switch transistor pairs 64-66 and 68-70 formed on the silicon substrate (not shown).

With brief reference to Figure 4a, shown are representative output waveforms for prior art implementations of charge pumps (e.g., 35, Figure 2c). In Figure 4a, for a low-to-high logic transition of control signal DOWN (signal 80a), output current IrjOWN (sig^nal 82a) is seen to have a sharp spike on the leading edge corresponding to the change of state in DOWN control signal 80a. In I_QOWN signal 82a, the spike is seen to tail off and settle to a design value of I_j ^*>_ef . The current spike produces an error in the total charge accumulated in the loop filter, in addition to the desired charge i -Δt. The error in total charge comprises approximately ΔQ = C-ΔV, as shown by signal 82a. The voltage change ΔV on capacitor 28, i.e., the change in control signal V_c 81a, is due to capacitor 28 being connected to the loop filter (capacitor 36) when the switch 70 is closed, and discharging of capacitor 28 to ground when the switch 70 is open. Although the magnitude of stray capacitances 27 and 28, and thus the magnitude of the current spike, may be minimized through geometric optimization of the source/switch transistor pairs 64-66 and 68-70, the current spike effect cannot be completely eliminated and will affect the performance of the charge pump. For example, the charge injection effect on charge pump performance will be noticeable even though the distance between transistors 64 and 66 (and 68 and 70) is relatively small, typically a few micrometers (IO"-^*-*' m), due to the significant capacitance of source-drain diffusions present between transistors 64 and 68. Additionally in the prior art arrangement shown in Figure 2c, because the current source transistors 64 and 68 are located adjacent to the voltage supply and ground rails, the full potential difference between the output VCP and the supply voltage or ground will be applied across stray capacitances 27 and 28, respectively. The foregoing arrangement will result in a significant quantity of charge being transferred to and from stray capacitances 27 or 28 whenever the corresponding switch transistor 66 or 70 is turned on, resulting in a harmful nonlinear phase response in a PLL.

As will be described in the following detailed description, the present invention overcomes many of the problems associated with prior art PLL charge pumps by interchanging the placement of the transistors implementing the switching function and the current limiting function. As a result of the interchanged placement of current source and switch transistors, current spikes due to inherent stray capacitances are substantially eliminated whenever either current switch is closed (turned on), wherein the current characteristic rises uniformly to the specified output level. Correspondingly, a relatively small charge error results when the switch is turned off, but there is no associated current spike.

SUMMARY OF THE INVENTION

Circuit arrangements and methods for preventing excessive charge injection in charge pump phase-locked loop (PLL) circuits are disclosed. A charge pump consists of first and second p-type metal- oxide-semiconductor (MOS) transistors coupled between a voltage supply and an output terminal, and first and second n-type MOS transistors coupled between the output terminal and a ground reference. The first p- and n-type transistors are respectively coupled to the voltage supply and ground, and are biased to operate as switches controlled by first and second control signals /UP and DOWN, respectively. The second p- and n-type transistors may be biased to operate as current sources in saturation mode in either subthreshold or above-threshold region, and are respectively controlled by bias voltages V_Up and Vci_owrι. A loop filter, for example an integrating capacitor, is coupled between the output terminal and ground, and produces an output signal V^_ontro ^* . A first stray capacitance to ground is inherently present between the first and second p-type transistors, and a second stray capacitance to ground is inherently present between first and second n-type transistors, both stray capacitances due to stray isolation junction capacitance in MOS device construction.

When the second p- and n-type transistors operate in subthreshold mode, the source-to-drain current characteristics of the second p- and n-type transistors are exponentially dependent on the gate-to-source voltage, V„_s. The current supplied by the second p- and n-type transistors is sharply reduced for moderate decreases in gate-to- source voltage, as occurs when the stray capacitances at the sources of the second transistors charge away from the corresponding power or ground voltages. When turned on in accordance with the first or second control signals /UP or DOWN, the first p- and n-type transistors operating as switches couple the sources of second p- and n-type transistors operating as current sources to the voltage supply and ground, respectively. Charge is therefore immediately accumulated on or depleted from the first and second stray capacitances through the first p- and n-type transistors. The current flowing within the second p- and n-type transistors is limited according to the subthreshold conduction characteristics induced in the second p- and n-type switch transistors, and excess charge injection from the stray capacitances is avoided by the smaller voltages impressed across the stray capacitances. The current will quickly approach the intended design level, but will not turn off as quickly, thereby allowing better control of current sources in charge pump applications.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood more fully^' from the detailed description given below and from the accompanying drawings of the preferred embodiment of the invention in which:

Figure la illustrates a prior art arrangement of a charge pump in a phase-locked loop including a voltage-controlled oscillator.

Figure lb illustrates a prior art arrangement of a charge pump in a phase-locked loop including a delay line.

Figure 2a illustrates a prior art arrangement of an idealized charge pump arrangement using current sources and switches.

Figure 2b illustrates a simple prior art implementation of the idealized charge pump shown in Figure 2a.

Figure 2c illustrates an improved prior art implementation of the idealized charge pump shown in Figure 2a.

Figure 3 illustrates the charge pump arrangement according to one embodiment of the present invention. Figure 4a illustrates representative voltage and current waveforms obtained with prior art charge pump implementations.

Figure 4b illustrates representative voltage and current waveforms obtained with the charge pump of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention discloses circuit arrangements and methods for preventing excessive charge injection in charge pump circuits used in phase-locked loop (PLL) systems. In the following description, for purposes of explanation, specific numbers, times, dimensions, and configurations are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well known systems are shown in diagrammatic or block diagram form in order not to obscure the present invention unnecessarily.

Reference is now made to Figure 3, wherein is shown a schematic of a charge pump circuit 40 according to the present invention disposed within a PLL including a phase detector and a controlled signal source (e.g., a voltage-controlled oscillator (VCO) or a voltage-controlled delay line). For purposes of this description, the invention will be described in connection with a VCO, although the invention is equally well suited to other charge pump applications. As shown in Figure 3, the charge pump 40 consists of first and second p- type metal-oxide-semiconductor field effect transistors (MOSFETs) 41 and 43 formed on a silicon substrate (not shown) and coupled source-to- drain between a supply voltage V_SUppi_v and an output node 45. The charge pump 40 further consists of first and second n-type MOSFET transistors 42 and 44 coupled source-to-drain between a ground reference voltage GND and the output node 45. The first p-type transistor 41 has its source coupled to the supply voltage V_SUppiy , and is biased to operate as a switch controlled by a first control signal /UP (50). The first n-type transistor 42 has its source coupled to the ground rail GND, and is biased to operate as a switch controlled by a second control signal DOWN (51). As in the prior art, first and second control signals /UP and DOWN (50 and 51) are digital logic level control signals delivered by the phase detector portion of the PLL, where /UP is applied in a logic "0", or "low", state to turn on p-type transistor 41, and DOWN is applied in a logic "1", or "high", state to turn on n-type transistor 42.

As shown in Figure 3, the second p- and n-type transistors 43 and

44 may be biased to operate as subthreshold mode current sources by applying a gate-to-source voltage Vg_g ~ 0.5 volts, which is sufficient to induce subthreshold conduction characterized by an exponential current dependence on gate drive, discussed in more detail below. The second p-type and n-type transistors 43 and 44 are controlled by third and fourth control signals V_up (52) and V_£jown (53), respectively. As is generally known, V_up and V_cjown control signals 52 and 53 may be supplied by a current mirror biasing arrangement. In one embodiment, the current mirror configuration consists of MOSFET biasing transistors 54 and 56 coupled in a mirror arrangement to source transistor 43, and MOS biasing transistor 55 coupled in a mirror arrangement to source transistor 44, as shown. Biasing transistors 54, 55, and 56 ensure that the gate drive levels applied to current source transistors 43 and 44 are approximately equal.

A loop filter typically comprising an integrating capacitor 46 is coupled between the output node 45 and the ground rail GND. The loop filter (46) produces an output control signal V_controι which is routed as an input to the VCO (e.g., 4, Figure la) forming part of the PLL. A first capacitance 47 is shown coupled between the first and second p-type transistors 41 and 43. Similarly, a second capacitance 48 is shown coupled between first and second n-type transistors 42 and 44. Capacitances 47 and 48 result from the same mechanism discussed above in connection with prior art charge pump arrangements. That is, capacitances 47 and 48 represent the stray isolation junction capacitance inherently present between the active region (not shown) and the substrate (not shown) in the drain-to-source regions of adjacent MOSFET current source and current switch transistors (e.g., transistors 41 and 43) formed on the substrate. As will be recalled from the previous discussion, although the stray isolation junction capacitance (47 or 48) may be reduced through geometric optimization of transistor pair 41 and 43, and transistor pair 42 and 44, the capacitance effect cannot be entirely eliminated.

In operation, when either switch transistor 41 or 42 is turned on, the sources of transistors 43 or 44 are essentially either pulled up to the supply voltage V_SUpp^*y or pulled down to ground GND, respectively. With the sources of the current source transistors 43 or 44 held at substantially known voltage potentials while switch transistor 41 or 42 is turned on, current characterized either as f_Up or z^*ci_own will flow to or from the loop filter capacitor 46, charge being either accumulated thereon or depleted therefrom in a known manner. When switch transistor 41 or 42 is turned off, current continues to flow briefly, charging capacitor 47 or 48 until the source voltage (either V_SUpp_jv or

GND) of current source transistor 43 or 44 changes enough to reduce the output current to substantially zero. However, the voltage change on capacitor 47 or 48 typically will be only 200 mV to reduce the output current by three orders of magnitude, due to the steep dependence of a MOS transistor's saturation current on source voltage.

Unlike prior art embodiments described above and embodied in hardware, the present invention substantially overcomes the charge injection problem caused by stray capacitances 47 and 48 by interchanging the placement of switch and current source transistors relative to the supply rails and the point where the charge pump output signal is taken. Specifically, switch transistors 41 and 42 are located immediately adjacent to the power supply and ground rails (V_SUpp ^* _[v and GND respectively), whereas the current source transistors 43 and 44 are placed adjacent to the centrally located output node 45. In addition, by combining the interchanged transistor placement with further modifications to device operating characteristics, further improvement in charge pump operation may be achieved. For example, in one embodiment of the present invention current source transistors 43 and 44 are biased to operate in the subthreshold region, rather than in the more typical above-threshold region. By operating the source transistors below threshold in combination with the interchanged positions of the source and switch transistor pairs, two advantages over prior art charge pump implementations may be obtained. First, the interchanged position of the source and switch transistors ensures that excess charge injection (i.e., the current spike) is virtually eliminated whenever the switch transistors 41 and 42 are turned on. Second, by operating the source transistors 43 and 44 within the subthreshold region of MOS transistor conduction, charge pump 40 will operate with smaller voltage swings on capacitors 47 and 48, and accordingly charge injection at turn-off will be even further reduced. Each advantage is described below.

The interchanged arrangement of source and switch transistors in the present invention overcomes problems associated with prior art charge pumps by reducing the voltage applied across the stray capacitances 47 and 48 existing between the current source and switch transistors, thus reducing stored charge. Because Q = C-V to first order for any capacitor (ΔQ = GΔV for non-constant charge and voltage conditions), if the applied voltage across a capacitor is minimized, it can be seen that the total charge stored on stray capacitances 47 and 48 will also be minimized. By interchanging the order of the current switch transistors 41 and 42 and the current source transistors 43 and 44, relative to prior art configurations described above (switch transistors 41 and 42 are respectively coupled to the supply rails V_SUppiy and ground

GND, and the source transistors 43 and 44 are each drain-coupled to the output node 45), the voltage impressed across stray capacitances 47 and 48 is at most a few hundred millivolts.

In addition, as seen in Figures 4a and 4b, the interchanged source and switch arrangement provides that excess charge due to stray capacitances 47 and 48 is injected at a different time relative to prior art implementations. Whereas in the prior art charge is injected at turn-on (signal 82a, Figure 4a), the interchanged order of source and switch transistors of the present invention ensures that excess charge stored on stray capacitors 47 and 48 is injected only when switch transistors 41 and 42 are turned off (signal 82b, Figure 4b). Compared to prior art charge pump arrangements, the present invention provides for substantially reduced current spikes (due to charge stored on stray capacitances 47 and 48 appearing at the output node 45 and thereafter incorporated in the ^control ^output signal) whenever either switch transistor 41 or 42 is closed .

In the present invention, charge injection may be even further reduced by biasing the current source transistors with lower voltages.

Recall that in prior art charge pump circuits, the voltage existing across the stray capacitances typically is several volts due to the output voltage " control ~ 2-3 volts. In the present invention, by operating at V_gs ~ 0.5 volts, the subthreshold-biased current source MOS transistors 43 and 44 produce an output current which may be described by: ids = e^χP«^κVg - V_s) q/kT) where k = Boltzmann's constant (1.38E-23 Joule/ °K), T is absolute temperature (°K), q is the charge of an electron (1.6E-19 coulombs), and K is a process dependent performance factor. Because at room temperature kT/q is usually expressed equivalently as 25 millivolts (mV), the output current measured at the drain of either transistor 43 or 44 operating in subthreshold mode for a given level of gate drive may be expressed as:

I = I₀- exp(- V_s/25mV), where I₀ is a scale factor characterizing either current source transistor

43 or 44 for a particular gate voltage V„ supplied by the bias circuit (i.e., transistors 54, 55, and 56).

Compared to prior art arrangements, in the present invention there is no current spike, and there is greatly reduced charge injection due to the reduced gate drive necessary to achieve subthreshold conduction in current source transistors 43 and 44. Therefore, the output current characteristic simply rises smoothly and uniformly to the specified output level without overshoot, as shown by IQOWN signal 82b in Figure 4b. Alternatively, when either switch transistors 41 or 42 is turned off, the output current tails off smoothly as charge is transferred to the stray capacitances 47 and 48, again as shown by •--DOWN signal 82b in Figure 4b. The arrangement of the present invention avoids the prior art problem of impressing the full potential difference of either V_SUppiy or ground GND across stray capacitances 47 or 48 whenever switch transistors 41 or 42 are closed. Instead, only a considerably smaller voltage exists across the stray capacitances 47 or 48, at most the gate-to-source voltage V„_s present in either of the current source transistors 43 or 44 (typically a few hundred mV).

The benefit of the present invention is not limited to only MOSFET circuit applications. In one alternative embodiment, the transistors forming the current switches and sources may be implemented with npn and pnp bipolar transistors. In a second alternative embodiment, attributes of the present invention may be achieved in a charge pump constructed with a combination of MOSFET and bipolar devices.

The foregoing has described circuit arrangements and methods for preventing excessive charge injection in switched current source charge pump circuits. The charge pump of the present invention may be used in any circuit where closely controlled control signals are indicated, including phase locked loop (PLL) systems. Although the foregoing has been described in terms of presently preferred and alternate embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described. The method and apparatus of the present invention can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting on the present invention.

Claims

CLAIMSI claim:

1. In a phase-locked loop arrangement including a loop filter and a phase detector, a charge pump circuit comprising: a first transistor for producing a positive output current, said first transistor coupled to an output node of said charge pump further coupled to said loop filter; a first current switch means coupled between said first transistor and a first voltage supply rail for switchably coupling said first transistor to said first voltage supply rail; a second transistor for producing a negative output current, said second transistor coupled to said output node; a second current switch means coupled between said second transistor and a second voltage supply rail for switchably coupling said second transistor to said second voltage supply rail, and current bias means coupled to said first and second transistors for adjusting said positive and negative output currents delivered through said output node to said loop filter.

2. The charge pump circuit as set forth in claim 1, wherein: said first and second transistors respectively comprise a first input and a second input coupled to respectively receive a first and a second analog control signal from said current bias means, said first and second analog control signals respectively controlling the magnitude of said positive and negative output currents, and said first and second current switch means respectively comprise a third input and a fourth input coupled to respectively receive a first and a second digital control signal from said phase detector, said first and second digital control signals selectively turning on and off said first and second current switch means.

3. The charge pump circuit as set forth in claim 2 further comprising: a first stray capacitance inherently present between said first current switch means and said first transistor, said first stray capacitance being charged to a first voltage level when said first current switch means is rendered nonconductive according to said first digital control signal, and a second stray capacitance inherently present between said second current switch means and said second transistor, said second stray capacitance being charged to a second voltage level when said second current switch means is rendered nonconductive according to said second digital control signal.

4. The charge pump circuit as set forth in claim 1, wherein: said first and second current switch means comprise third and fourth transistors, and said first, second, third, and fourth transistors are selected from the group of semiconductor devices consisting of field effect transistors (FETs) and bipolar transistors.

5. The charge pump circuit as set forth in claim 4, wherein said first, second, third, and fourth transistors comprise p- channel and n-channel metal-oxide-semiconductor (MOS) field effect transistors.

6. The charge pump circuit as set forth in claim 4, wherein said first, second, third, and fourth transistors comprise pnp and npn bipolar transistors.

7. The charge pump circuit as set forth in claim 1, wherein the loop filter is coupled to a controlled signal source.

8. The charge pump circuit as set forth in claim 7, wherein the controlled signal source comprises a voltage-controlled oscillator.

9. The charge pump circuit as set forth in claim 7, wherein the controlled signal source comprises a voltage-controlled delay line.

10. The charge pump as set forth in claim 1, wherein the current bias means comprises: a first current mirror arrangement coupled to said first current source means, and a second current mirror arrangement coupled to said second current source means.

11. In a phase-locked loop arrangement including a loop filter and a phase detector, a charge pump circuit comprising: a first metal-oxide-semiconductor (MOS) transistor for producing a positive output current, said first MOS transistor having its drain coupled to an output node of said charge pump further coupled to said loop filter; a second MOS transistor for switchably coupling said first MOS transistor to a first voltage supply rail, said first MOS transistor having its source coupled to the first voltage supply rail and its drain coupled to the source of said first MOS transistor; a third MOS transistor for producing a negative output current, said third MOS transistor having its drain coupled to said output node, and a fourth MOS transistor for switchably coupling said third MOS transistor to a second voltage supply rail, said fourth MOS transistor having its source coupled to the second voltage supply rail and its drain coupled to the source of said third MOS transistor.

12. The charge pump circuit as set forth in claim 11, wherein: the gates of said second and fourth MOS transistors are coupled to respectively receive first and second digital control signals from said phase detector for selectively engaging said first and third MOS transistors, . and said current bias means supplies first and second analog control signals to the gates of said first and third MOS transistors for controlling said positive and negative output currents.

13. The charge pump circuit as set forth in claim 12 further comprising: a first stray capacitance inherently present between said first and second MOS transistors, said first stray capacitance being charged to a first voltage level when said second MOS transistor is rendered nonconductive according to said first digital control signal, and a second stray capacitance inherently present between said third and fourth MOS transistors, said second stray capacitance being charged to a second voltage level when said fourth MOS transistor is rendered nonconductive according to said second digital control signal.

14. The charge pump circuit as set forth in claim 13, wherein said first and second MOS transistors are p-channel transistors, and said third and fourth MOS transistors are n-channel transistors.

15. The charge pump circuit as set forth in claim 13 wherein: said first and second analog control signals respectively comprise a V_Up signal and a V_(jown signal, said V_up signal controlling the magnitude of said positive current produced by said first MOS transistor, said V_cjown signal controlling the magnitude of said negative current produced by said third MOS transistor, and said first and second digital control signals respectively comprise an /UP signal and a DOWN signal, said second MOS transistor closing when said /UP signal comprises a first logic "low" state, said fourth MOS transistor closing when said DOWN signal comprises a second logic "high" state.

16. The charge pump circuit as set forth in claim 11, wherein the loop filter is coupled to a controlled signal source.

17. The charge pump circuit as set forth in claim 16, wherein the controlled signal source comprises a voltage-controlled oscillator.

18. The charge pump circuit as set forth in claim 16, wherein the controlled signal source comprises a voltage- controlled delay.

19. In a phase-locked loop arrangement comprising a charge pump phase detector circuit and a loop filter, a method for reducing charge injection in the charge pump, said method comprising the steps of: producing a positive output current from a first transistor coupled to an output node of said charge pump further coupled to said loop filter; switchably coupling, via a first current switch means, said first transistor to a first voltage supply rail; producing a negative output current from a second transistor coupled to said output node; providing a second current source means for producing an output current comprising a second sense; switchably coupling, via a second current switch means, said second transistor to a second voltage supply rail, and adjusting said positive and negative output currents delivered through said output node to said loop filter by coupling current bias means to said first and second current source means.

20. The method as set forth in claim 19, wherein producing the positive output current comprises: supplying, from said current bias means, a first and a second analog control signal to said first and second transistors respectively, said first and second analog control signals respectively controlling the magnitude of said positive and negative output currents, and supplying, from said phase detector, a first and a second digital control signal to said first and second current switch means respectively, said first and second digital control signals selectively turning on and off said first and second current switch means, respectively.

21. The method as set forth in claim 20, wherein: a first stray capacitance inherently present between said first current switch means and said first transistor is charged to a first voltage level when said first current switch means is rendered nonconductive according to said first digital control signal, and a second stray capacitance inherently present between said second current switch means and said second transistor is charged to a second voltage level when said second current switch means is rendered nonconductive according to said second digital control signal.

22. The method as set forth in claim 19, wherein: said first and second current switch means comprise third and fourth transistors, and said first, second, third, and fourth transistors are selected from the group of semiconductor devices consisting of field effect transistors (FETs) and bipolar transistors.

23. The method as set forth in claim 22, wherein said first, second, third, and fourth transistors comprise p-channel and n- channel metal-oxide-semiconductor (MOS) field effect transistors.

24. The method as set forth in claim 22, wherein said first, second, third, and fourth transistors comprise pnp and npn bipolar transistors.

25. The method as set forth in claim 19, wherein the loop filter is coupled to a controlled signal source.

26. The method as set forth in claim 25, wherein the controlled signal source comprises a voltage-controlled oscillator.

27. The method as set forth in claim 25, wherein the controlled signal source comprises a voltage-controlled delay line.

28. The method as set forth in claim 19 further comprising the steps of: coupling a first current mirror arrangement to said first current source means, and coupling a second current mirror arrangement to said second current source means.