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WO1996001495A1 - Method, carrier and mould parts for encapsulating a chip - Google Patents

Method, carrier and mould parts for encapsulating a chip Download PDF

Info

Publication number
WO1996001495A1
WO1996001495A1 PCT/NL1995/000232 NL9500232W WO9601495A1 WO 1996001495 A1 WO1996001495 A1 WO 1996001495A1 NL 9500232 W NL9500232 W NL 9500232W WO 9601495 A1 WO9601495 A1 WO 9601495A1
Authority
WO
WIPO (PCT)
Prior art keywords
carrier
encapsulating
chip
mould
channel
Prior art date
Application number
PCT/NL1995/000232
Other languages
French (fr)
Inventor
Henricus Bernardus Antonius Giesen
Original Assignee
Fico B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fico B.V. filed Critical Fico B.V.
Publication of WO1996001495A1 publication Critical patent/WO1996001495A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/04—Tubular or hollow articles
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Definitions

  • the invention relates to a method for encapsulating a chip placed on a flat carrier, on one side of which is arranged the chip for encapsulating and on the other side of which are arranged the connection points distributed in a grid structure over the carrier.
  • the invention also relates to a carrier of the stated type and mould parts for encapsulating a chip according to the said method.
  • the carrier referred to in the preamble (also known as "ball grid array board") is larger than the moulding for producing, it is probable that with application of the conventional technique for encapsulating chips a quantity of encapsulating material from the runner remains adhered to the edge of the carrier. This is undesirable because a local thickening of the edge of the carrier can be disadvantageous for the further use of the carrier with encapsulated chip.
  • a mould consisting of at least three mould parts.
  • Such a mould has the important drawback however that automated operation of such a mould is difficult.
  • Another drawback is a comparatively complex and therefore expensive construction of the mould.
  • the present invention therefore has for its object to provide a relatively simple method for encapsulating a chip on a carrier of the stated type.
  • the invention has the further object to provide mould parts and a carrier suitable for applying this method.
  • the invention provides for this purpose a method for encapsulating a chip as according to the preamble by: placing the carrier between two mould halves movable between an opened and a closed position and bounding a mould cavity in the closed position, and transporting encapsulating material from a supply device to a mould cavity through a channel arranged in the carrier.
  • the invention further provides a carrier characterized by a channel arranged in the carrier, and mould parts for use with this method.
  • a feed runner is arranged in the carrier.
  • This feed runner therefore no longer has to be accommodated in the mould parts, whereby the whole mould can be embodied simply.
  • a mould consisting of two mould halves is now a possibility, whereby automation of the moulding is possible.
  • the mould parts can also be less complex in manufacture and thus less costly. Wear of the mould parts and danger of leakage is also limited herewith.
  • a preferred embodiment of the carrier is characterized in that the channel in the carrier is formed by a groove arranged on one side in the carrier.
  • Another preferred embodiment of the carrier is characterized in that the channel arranged in the carrier is an elongate opening in the carrier.
  • the groove in particular limits wear to the mould and simplifies very considerable the construction of the mould.
  • the elongate opening has the advantage that less fluid encapsulating material can also be carried to the mould cavity without the capacity of the feed runner forming a limitation. Due to the elongate opening it is also possible to supply the encapsulating material from a chosen side.
  • Fig. 1 shows a partly cut away perspective view of a flat carrier on one side of which is arranged the encap ⁇ sulated chip and on the other side of which are arranged the connection points distributed in grid structure over the carrier, wherein a part of the encapsulating material is received in a channel arranged in the carrier
  • Fig. 2 shows a partly cut away perspective view of the carrier of fig. 1 in cut-out situation
  • Fig. 3 shows a cross section through a carrier placed between two mould halves, wherein the channel is in a groove located in the carrier
  • Fig. 4 is a cross section through a carrier wherein the channel is an elongate opening.
  • Fig. 1 shows a carrier 1 on which are arranged on one side a chip (not shown here) and on the other side connection points 2 in grid pattern.
  • An encapsulating material 3 for instance an epoxy resin, is arranged round the chip 1.
  • a material portion 4 formed by a runner in the mould half can also be seen on the edge of the carrier 1.
  • a feed runner 7 for encapsulating material is arranged in the carrier 1.
  • the feed runner 7 is filled to the same height as the encapsulating material 8 filling the upper part of the carrier part 5.
  • Fig. 3 shows two mould parts 9, 10 wherein a plunger 11 arranged in the lower mould part 10 by means of heating and applying pressure to a pallet 12 urges encapsulating material through a runner 13 in the upper mould part 9 and then through the runner 7 arranged in the carrier 1 to a mould cavity 14.
  • Fig. 4 shows a carrier 1 wherein a groove-like opening 15, here filled with encapsulating material, forms the channel arranged in the carrier 1.
  • the groove-like opening 15 can be supplied on a chosen side.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)

Abstract

The invention relates to a method for encapsulating a chip placed on a flat carrier (1), on one side of which is arranged the chip for encapsulating and on the other side of which are arranged the connection points distributed in a grid structure over the carrier (1), by: placing the carrier between two mould halves (9, 10) movable between an opened and a closed position and bounding a mould cavity in the closed position, and transporting encapsulating material (3) from a supply device to a mould cavity through a channel (7, 15) arranged in the carrier (1).

Description

METHOD, CARRIER AND MOULD PARTS FOR ENCAPSULATING A CHIP
The invention relates to a method for encapsulating a chip placed on a flat carrier, on one side of which is arranged the chip for encapsulating and on the other side of which are arranged the connection points distributed in a grid structure over the carrier. The invention also relates to a carrier of the stated type and mould parts for encapsulating a chip according to the said method.
Since the carrier referred to in the preamble (also known as "ball grid array board") is larger than the moulding for producing, it is probable that with application of the conventional technique for encapsulating chips a quantity of encapsulating material from the runner remains adhered to the edge of the carrier. This is undesirable because a local thickening of the edge of the carrier can be disadvantageous for the further use of the carrier with encapsulated chip. In order to prevent such a local thickening in the edge of the carrier, use is presently made of a mould consisting of at least three mould parts. Such a mould has the important drawback however that automated operation of such a mould is difficult. Another drawback is a comparatively complex and therefore expensive construction of the mould.
The present invention therefore has for its object to provide a relatively simple method for encapsulating a chip on a carrier of the stated type. The invention has the further object to provide mould parts and a carrier suitable for applying this method.
The invention provides for this purpose a method for encapsulating a chip as according to the preamble by: placing the carrier between two mould halves movable between an opened and a closed position and bounding a mould cavity in the closed position, and transporting encapsulating material from a supply device to a mould cavity through a channel arranged in the carrier.
The invention further provides a carrier characterized by a channel arranged in the carrier, and mould parts for use with this method. With these steps a feed runner is arranged in the carrier. This feed runner therefore no longer has to be accommodated in the mould parts, whereby the whole mould can be embodied simply. A mould consisting of two mould halves is now a possibility, whereby automation of the moulding is possible. The mould parts can also be less complex in manufacture and thus less costly. Wear of the mould parts and danger of leakage is also limited herewith.
A preferred embodiment of the carrier is characterized in that the channel in the carrier is formed by a groove arranged on one side in the carrier. Another preferred embodiment of the carrier is characterized in that the channel arranged in the carrier is an elongate opening in the carrier. The groove in particular limits wear to the mould and simplifies very considerable the construction of the mould. The elongate opening has the advantage that less fluid encapsulating material can also be carried to the mould cavity without the capacity of the feed runner forming a limitation. Due to the elongate opening it is also possible to supply the encapsulating material from a chosen side.
The following invention will be further elucidated with reference to the non-limitative embodiments shown in the following figures. Herein:
Fig. 1 shows a partly cut away perspective view of a flat carrier on one side of which is arranged the encap¬ sulated chip and on the other side of which are arranged the connection points distributed in grid structure over the carrier, wherein a part of the encapsulating material is received in a channel arranged in the carrier, Fig. 2 shows a partly cut away perspective view of the carrier of fig. 1 in cut-out situation,
Fig. 3 shows a cross section through a carrier placed between two mould halves, wherein the channel is in a groove located in the carrier, and Fig. 4 is a cross section through a carrier wherein the channel is an elongate opening.
Fig. 1 shows a carrier 1 on which are arranged on one side a chip (not shown here) and on the other side connection points 2 in grid pattern. An encapsulating material 3, for instance an epoxy resin, is arranged round the chip 1. A material portion 4 formed by a runner in the mould half can also be seen on the edge of the carrier 1. In order to obtain, after cutting out the encapsulated chip, a remaining carrier part 5 designated with the dashed line 6 and having an edge thickness the same throughout, a feed runner 7 for encapsulating material is arranged in the carrier 1. As shown clearly in fig. 2, after arranging of the encapsulating material 3 the feed runner 7 is filled to the same height as the encapsulating material 8 filling the upper part of the carrier part 5.
Fig. 3 shows two mould parts 9, 10 wherein a plunger 11 arranged in the lower mould part 10 by means of heating and applying pressure to a pallet 12 urges encapsulating material through a runner 13 in the upper mould part 9 and then through the runner 7 arranged in the carrier 1 to a mould cavity 14.
Fig. 4 shows a carrier 1 wherein a groove-like opening 15, here filled with encapsulating material, forms the channel arranged in the carrier 1. The groove-like opening 15 can be supplied on a chosen side.
*****

Claims

1. Method for encapsulating a chip placed on a flat carrier, on one side of which is arranged the chip for encapsulating and on the other side of which are arranged the connection points distributed in a grid structure over the carrier, by: placing the carrier between two mould halves movable between an opened and a closed position and bounding a mould cavity in the closed position, and transporting encapsulating material from a supply device to a mould cavity through a channel arranged in the carrier.
2. Carrier for a chip, on one side of which is arranged the chip for encapsulating and on the other side of which are arranged the connection points distributed in the grid structure over the carrier, for use in a method as claimed in claim 1, characterized by a channel arranged in the carrier.
3. Carrier as claimed in claim 2, characterized in that the channel arranged in the carrier is a groove arranged on one side of the carrier.
4. Carrier as claimed in claim 2, characterized in that the channel arranged in the carrier is an elongate opening in the carrier.
5. Mould parts for use with a method as claimed in claim 1.
*****
PCT/NL1995/000232 1994-07-01 1995-07-03 Method, carrier and mould parts for encapsulating a chip WO1996001495A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL9401104A NL9401104A (en) 1994-07-01 1994-07-01 Method, carrier and mold parts for encapsulating a chip.
NL9401104 1994-07-01

Publications (1)

Publication Number Publication Date
WO1996001495A1 true WO1996001495A1 (en) 1996-01-18

Family

ID=19864397

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/NL1995/000232 WO1996001495A1 (en) 1994-07-01 1995-07-03 Method, carrier and mould parts for encapsulating a chip

Country Status (2)

Country Link
NL (1) NL9401104A (en)
WO (1) WO1996001495A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1271640A3 (en) * 1996-07-12 2003-07-16 Fujitsu Limited Mold for manufacturing semiconductor device
WO2004091267A1 (en) * 2003-04-11 2004-10-21 Flex-P Industries Sdn. Bhd Method for packaging small size memory cards
US6881611B1 (en) 1996-07-12 2005-04-19 Fujitsu Limited Method and mold for manufacturing semiconductor device, semiconductor device and method for mounting the device
NL1025300C2 (en) * 2004-01-22 2005-07-25 Fico Bv Support for electronic components and methods for enclosing and separating an electronic component.

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS611067A (en) * 1984-06-13 1986-01-07 Stanley Electric Co Ltd Molding method of led chip mounted on printed board
JPS6441254A (en) * 1987-08-07 1989-02-13 Nec Corp Resin-sealed type semiconductor device
GB2218570A (en) * 1988-05-09 1989-11-15 Nat Semiconductor Corp Plastics moulded pin-grid-array power package
JPH04306865A (en) * 1991-04-03 1992-10-29 Seiko Epson Corp Semiconductor device and manufacture thereof
JPH04373138A (en) * 1991-06-21 1992-12-25 Citizen Watch Co Ltd Resin sealed semiconductor device and its manufacture

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS611067A (en) * 1984-06-13 1986-01-07 Stanley Electric Co Ltd Molding method of led chip mounted on printed board
JPS6441254A (en) * 1987-08-07 1989-02-13 Nec Corp Resin-sealed type semiconductor device
GB2218570A (en) * 1988-05-09 1989-11-15 Nat Semiconductor Corp Plastics moulded pin-grid-array power package
JPH04306865A (en) * 1991-04-03 1992-10-29 Seiko Epson Corp Semiconductor device and manufacture thereof
JPH04373138A (en) * 1991-06-21 1992-12-25 Citizen Watch Co Ltd Resin sealed semiconductor device and its manufacture

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 010, no. 137 (E - 405) 21 May 1986 (1986-05-21) *
PATENT ABSTRACTS OF JAPAN vol. 013, no. 235 (E - 766) 30 May 1989 (1989-05-30) *
PATENT ABSTRACTS OF JAPAN vol. 017, no. 137 (E - 1335) 22 March 1993 (1993-03-22) *
PATENT ABSTRACTS OF JAPAN vol. 017, no. 253 (E - 1367) 19 May 1993 (1993-05-19) *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1271640A3 (en) * 1996-07-12 2003-07-16 Fujitsu Limited Mold for manufacturing semiconductor device
US6881611B1 (en) 1996-07-12 2005-04-19 Fujitsu Limited Method and mold for manufacturing semiconductor device, semiconductor device and method for mounting the device
WO2004091267A1 (en) * 2003-04-11 2004-10-21 Flex-P Industries Sdn. Bhd Method for packaging small size memory cards
NL1025300C2 (en) * 2004-01-22 2005-07-25 Fico Bv Support for electronic components and methods for enclosing and separating an electronic component.
WO2005071732A1 (en) * 2004-01-22 2005-08-04 Fico B.V. Carrier for electronic components and methods for encapsulating and separating an electronic component

Also Published As

Publication number Publication date
NL9401104A (en) 1996-02-01

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