WO1996005558A1 - Commutateur de reseau - Google Patents
Commutateur de reseau Download PDFInfo
- Publication number
- WO1996005558A1 WO1996005558A1 PCT/US1995/010256 US9510256W WO9605558A1 WO 1996005558 A1 WO1996005558 A1 WO 1996005558A1 US 9510256 W US9510256 W US 9510256W WO 9605558 A1 WO9605558 A1 WO 9605558A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- input
- output
- buffer
- channels
- storage
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
Definitions
- the present invention relates to network switches in general and to Ethernet network switches in particular.
- Figs. 1A nd 1B illustrate two different types of Ethernet network formed of a plurality of workstations 10 connected together.
- the Ethernet network of Fig. 1A is a "shared media" network in which the workstations 10 share the bandwidth of the bus 12 which connects them together.
- Bus 12 is typically implemented in a "hub” or “multiport repeater".
- those workstations 10 which are actively sending utilizing the network share the capacity with each other. The fewer the users, the more capacity is available for those who are active. Unfortunately, the opposite is also true; when there are many users, the capacity is shared among all active workstations and thus, each one can only utilize a small portion of the capacity.
- Switched Ethernet networks were designed in which a number of conversations are allowed at once. The active conversations share the available capacity and the conversations are switched so that all can get access at some time.
- a switched network 14 is shown in Fig. 1 B in which point-to-point conversations 16 are enabled.
- the switched network 14 is typically implemented in a network switch.
- the Ethernet protocol involves sending "frames" of data, which include destination information therein, from one workstation, for example workstation 10a, to the entire network. Since all workstations continually listen to the network, the destination workstation, for example workstation 10b, can pick up the frame sent to it.
- Prior art network switches utilize a central processing unit (CPU) to direct frames to a memory device for storage and to forward the frames to their destination workstation at the appropriate time.
- the received frame is loaded into the memory and, only once the frame has been completely stored, is it transmitted to the output port.
- the time a frame takes from input to output is a function of the length of the frame
- a network switch which includes a storage buffer, apparatus having fixed delay on input to the storage buffer, apparatus having fixed delay on output from the storage buffer and association apparatus for associating data within the storage buffer whereby the network switch is connectable to a plurality of channels each of which operates as an input and an output channel.
- the fixed delay input apparatus transfers input data from input channels to the storage buffer with a first fixed delay.
- the fixed delay output apparatus transfers output data from the storage buffer to the output channels with a second fixed delay.
- the association apparatus associates, within the storage buffer, input data from one input channel with at least one output channel thereby converting the input data to output data.
- the storage buffer includes a plurality of storage spaces and the network switch also includes apparatus for temporarily assigning each storage space to a conversation between only one input channel and at least one output channel. Additionally, there is apparatus for indicating to the fixed delay input means to place the input data from each input channel into the assigned storage space for the corresponding conversation.
- the storage spaces are preferably first in, first out (FIFO) buffers.
- the fixed delay input apparatus includes an input buffer and an internal bus.
- the input buffer includes separate input buffer spaces each storing the input data from one of the input channels.
- the internal bus has separate time slots each receiving data from one of the input buffer spaces.
- the input buffer also includes a header buffer for storing routing and status information regarding the data received from each input channel.
- the network switch also includes apparatus for discarding any data for whom the routing information is to an unknown destination.
- the fixed delay output apparatus includes separate output buffer spaces each storing the output data from one of said output channels.
- the input and output data are formed of a portion of a frame.
- the network switch also includes a back pressure controller, activatable once all of the plurality of storage spaces are assigned, for providing either collisions or jam frames on all input channels attempting to start new conversations.
- a number of network switches can be combined together.
- the internal busses are combined while the remaining elements remain separate.
- the network switch includes a two-way buffer at least having one input and one output first in, first out (FIFO) buffer per channel which is large enough to store one frame portion.
- the network switch also includes an internal bus which receives frame portions from the input FIFOs, a storage buffer having a multiplicity of storage FIFOs and a switch controller.
- the internal bus has a timing sequence having a plurality of timing periods of which one timing period is allocated to each input FIFO.
- the switch controller includes apparatus for temporarily assigning each storage FIFO to collect frame portions from timing periods corresponding to one conversation, of the length of a frame, between one input channel and at least one output channel, wherein not all of said output channels are active at the same time.
- the switch controller also includes apparatus for transferring the oldest frame portions of each active output channel to its corresponding output FIFO of the two-way buffer for later transfer out to its active output channel.
- the network switch is connectable to a plurality of channels each of which operates as an input and an output channel.
- the network switch also includes a back pressure controller, activatable once all of said multiplicity of storage FIFOs are active, for providing either collisions or jam frames on all input channels attempting to start new conversations.
- the two-way buffer also includes a header buffer in which is stored routing and status information regarding each frame portion received from the channels.
- the present invention incorporates the method performed by the network switch described hereinabove, which switches data among a plurality of channels each of which operates as an input and an output channel.
- the method includes the steps of transferring input data from the input channels to a storage buffer with a first fixed delay, transferring output data from the storage buffer to the output channels with a second fixed delay.
- the switching method also associates input data from one input channel with at least one output channel, within the storage buffer. In this way, input data is converted to output data.
- the storage buffer includes a plurality of storage spaces.
- the method also includes the steps of temporarily assigning each storage space to a conversation between only one input channel and at least one output channel and of indicating to said fixed delay input apparatus place the input data from each input channel into the assigned storage space for the corresponding conversation.
- the step of transferring input data includes the steps of providing separate input buffer spaces corresponding to each of the input channels, and providing an internal bus having separate time slots each receiving data from one of the input buffer spaces.
- the step of transferring output data includes the step of providing separate output buffer spaces corresponding to each of the output channels.
- the step of transferring output data also includes the step of providing collisions on all input channels attempting to start new conversations once all of said plurality of storage spaces are assigned.
- the step of transferring output data also includes the step of providing jam frames on all input channels attempting to start new conversations once all of said plurality of storage spaces are assigned.
- FIGs. 1A and 1B are block diagram illustrations of prior art networks having a multiport repeater (Fig. 1A) and an Ethernet network switch (Fig. 1B);
- Rg. 2 is a block diagram illustration of a network switch constructed and operative in accordance with a preferred embodiment of the present invention
- Fig. 3 is a timing diagram useful in understanding the operation of the switch of Fig. 2;
- Fig. 4 is a schematic illustration of a storage buffer forming part of the switch of Fig. 2;
- Rg. 5 is a schematic illustration of an alternative embodiment of the switch of Fig. 2 in which a few such switches are connected together;
- Rg. 6 is a timing diagram of the timing of an internal bus in the alternative switch of Rg. 5.
- FIG. 2 - 4 illustrate the network switch 19 of the present invention, implemented for the Ethernet protocol. It will be appreciated that the principles of the present invention can also be implemented for other network protocols.
- the switch 19 comprises two channel busses 20, each connected to a plurality of workstations 10, or channels, two arbiters 21, each operating in conjunction with one of the channel busses 20, a two-way buffer 22, an internal bus 24, a storage buffer 26 and a switch controller 28.
- two channel busses 20 each connected to a plurality of workstations 10, or channels
- two arbiters 21 each operating in conjunction with one of the channel busses 20, a two-way buffer 22, an internal bus 24, a storage buffer 26 and a switch controller 28.
- the two-way buffer 22 comprises an input portion 23 and an output portion 25.
- the input portion 23 comprises a plurality of input first in, first out (FIFO) buffers 30, one per channel 10, and a header buffer 32 and the output portion 25 comprises a plurality of output FIFO buffers 33, one per channel 10. 12 input and output FIFOs 32 and 33, respectively are shown as an example.
- the data to be transferred is not the entire frame, Ethernet or otherwise, as in the prior art, but a portion thereof (herein called a "frame portion") of a predefined size, such as a small percentage of the frame length.
- a frame portion typically includes a destination address (6 bytes), a source address (6 bytes), a payload (46 to 1500 bytes), a length field (2 bytes) and a frame check sum (4 bytes).
- Each arbiter 21 communicates with its channels 10 in a round robin manner. At any given time, one arbiter 21 is operative for input (the "input arbiter") and one arbiter 21 is operative for output (the “output arbiter”).
- the input arbiter 21 transfers the frame portions from the channels 10 connected to it to the corresponding input FIFOs 30 of the two-way buffer 22.
- the output arbiter 21 transfers frame portions from the corresponding output FIFOs 33 of the two-way buffer 22 to the channels 10 connected to the output arbiter.
- the input arbiter 21 provides the switch controller 28 with information about each frame of each channel. For example, the information might include the status of the channel (i.e.
- the channel is available and whether or not it is sending data) and, if there is a frame to be sent, the number of the frame portion within the frame (i.e. the second of 1000) including an indication of whether it is the first, last or middle, and the destination channel of the frame.
- the switch controller 28 accesses the network table 39, in which is stored a map of the entire network as it is currently known, to identify whether or not the designation channels of each frame portion are known. If so, the network table 39 extracts the physical port (i.e. channel) to which each designation channel is attached. If the location of the destination is not known, the switch controller 28 will cause the frame portion to either be broadcast to all channels 10 (in a method known in the art as "negative filtering") or discarded (in a method called herein "positive filtering").
- the switch controller 28 then creates a header for the entire set of frame portions (all 12) in the input portion 28 and places the header into header buffer 30.
- each input FIFO 30 receives input frame portions only from its corresponding channel. Thus, if a channel has no frame portions to send to the network, its corresponding input FIFO 30 will not be filled and the switch controller 28 provides a notation to that effect in the header buffer 32.
- the two-way buffer 22 Once the two-way buffer 22 is full (i.e. it has received frame portions from each of the channels 10 from both channel busses 20), it transfers the data held therein to a transfer buffer 34 which, in turn, transfers all of the data to the internal bus 24 as follows and as shown in Fig. 3.
- Fig. 3 is a timing diagram of the frame portion flow through network switch 19 of the present invention.
- the timing diagram is divided into three equal length periods, an input period 36, a transfer period 37 and an output period 38, each of X clock cycles, where X is typically 80.
- the clock cycles are indicated in Fig. 3 as the space between ticks.
- input frame portions are provided from the channels 10 to the input portion 23 of the two-way buffer 22, as described hereinabove.
- the input frame portions and other data are transferred to the internal bus 24 via the transfer buffer 34.
- output frame portions are provided from the output portion 25 of the two-way buffer 22 to their corresponding channels 10, as detailed hereinbelow. It will be appreciated that the three periods 36 - 38 are pipelined such that, the ith input period 36 occurs at the same time as the (i-1)th transfer period 37 and the (i-2)th output period 38.
- the header is provided first, during a predefined number, such as four clock cycles. In each following clock cycle, one frame portion is provided, in channel order. Thus, the frame portion from channel 1 is provided in the first clock cycle, followed by the frame portion from channel 2, etc. It will be appreciated that the header and frame portions each have their own allocated "time slots" and that the time slots can be of any desired length. If an input FIFO 30 was empty, because its corresponding channel
- the network switch 19 of the present invention enables many conversations to occur at the same time.
- Storage buffer 26 is detailed in Fig. 4 and comprises a multiplicity of "storage FIFOs" 40, where each storage FIFO 40 is operative to collect a frame of data and 10 storage FIFOs 40a - 40j are shown in Fig. 4.
- Each storage FIFO 40 stores frame portions of a single frame which are to be sent either to a single channel (creating a point-to-point conversation) or to many channels (creating a point-to-multi-point conversation).
- the storage FIFOs 40a, 40b and 40c of Fig. 4 are for point-to-point conversations and storage FIFO 40d is for a point-to-multi-point conversation.
- each storage FIFO 40 stores a frame from one conversation.
- the switch controller 28 Before entering data into the storage buffer 26, the switch controller 28 receives the header information from one transfer period 37 and from that information, determines in which storage FIFO 40 to place the frame portion provided in each clock cycles following the header clock cycles. If the header information indicates that the frame portion of a channel is the first frame portion of a new frame, the switch controller 28 places the frame portion, labeled 42, into the next empty storage FIFO 40, such as 40e. Later frame portions 42 from the same channel (received after the current transfer period
- the switch controller 28 places the frame portion 42 into the storage FIFO 40 currently allocated to that channel for input.
- storage FIFOs 40a and 40c more than one channel can be sending frames to the same channel.
- Storage FIFO 40a is allocated to channel 1 for sending a frame to channel 3 and storage FIFO 40c is allocated to channel 2 for sending a frame also to channel 3. Since storage FIFO 40a comes before storage FIFO 40c, storage FIFO 40a will be emptied, as described hereinbelow, prior to emptying storage FIFO -40c. However, both storage FIFOs 40a and 40c can be filling at the same time.
- Switch controller 28 keeps track of which storage FIFO 40 belongs to which destination channel and the order in which the storage FIFOs 40 with data from the same channel were received. Thus, the switch controller 28 knows the order in which to empty the storage FIFOs 40 storing frames for the same channel. Furthermore, the switch controller 28 knows which storage FIFOs 40 store frames for broadcast conversations. For these frames, switch controller 28 keeps track of the channels to which it has already sent a copy of the broadcast frame or frame portions and only removes the data in the broadcast storage FIFO 40d once all the designated channels have received the data.
- switch controller 28 transfers the oldest frame portion 42 in each currently active storage FIFO 40 to the output portion 25 of the two-way buffer 22, via a second transfer buffer
- the frame portions are stored in the output FIFOs 33 corresponding to the channels 10 to which they are to be sent.
- the arbiters 21 access each output RFO 33, in order, and transfer the frame portions stored therein, if any, to the corresponding channel 10 for output.
- the network table 39 also learns the addresses of the source channels from the source address fields present within the frame.
- each arbiter 21 works half of each input and output period.
- This feature enables the present invention to implement a full duplex Ethernet protocol in which, during any one period, both incoming and outgoing frames can be transferred.
- the present invention provides a fixed delay from the input of data through its storage in the storage buffer 26 and from the storage buffer 26 out to the channels 10.
- the fixed input delay is provided by the fixed allocation of space per channel in the input portion 23 of the two-way buffer 22 and the fixed allocation of time per channel during the transfer period 37.
- the fixed output delay is provided by the fixed allocation of space per channel in the output portion 25 of the two-way buffer 22. Because the storage in the input portion 23 and the timing on the internal bus 24 are fixedly allocated, the present invention has no need for a standard input buffer which has to be managed. The present invention only needs to manage the storage buffer 26.
- the time through the storage buffer 26 is variable.
- the variability is a function of the activity of the network and not of the manner in which the storage buffer 26 is designed. For example, if 11 channels all choose to send frames to the twelfth channel, each storage
- FIFO 40 will store a frame, or portion thereof, destined for the twelfth channel. Since the twelfth channel can only receive one frame portion at a time, it will receive data only from the currently active storage FIFO 40.
- switch controller 28 indicates to a back pressure controller 50 to indicate to any channel newly sending to the switch to stop sending for a while.
- back pressure controller 50 forces a collision or sends a jam frame, as are known in the Ethernet protocol, during the "round trip time" or the first 51.2 microseconds of the transmission of the frame.
- the sending channel will resume sending at some, randomly chosen, future time.
- the jam frame as soon as transmission of the jam frames finish, the sending channel will resume sending.
- more than one network switch 19, such as is described hereinabove, can be connected together on the same internal bus 24 to produce a large switch 70.
- Rg. 5 illustrates a few network switches 60 of the present invention connected together to form large switch 70, wherein each is connected to its own channels 10.
- the network switches 60 comprise similar elements and operate in a similar manner to that described hereinabove with respect to network switch 19. However, in this embodiment, the network switches 60 are all connected to the same internal bus 24. Despite this, as will be seen hereinbelow, the fixed delays on input and from the storage buffer are maintained between all of the network switches 60.
- each switch 60 has its own period 62 during which it can transfer data to the internal bus 24.
- period 62a the first switch 60 provides data.
- the second switch 60 provides data, etc.
- Each period 62 includes the timing of the transfer period 37 as described hereinabove with respect to Fig. 3. In other words, four clock cycles for the header, one clock cycle per channel, and one idle cycle, per switch 60.
- the network table 39 includes in it the switch 60 and the channel number to which each workstation of the entire network belongs.
- a channel might be known as the ith channel of the jth switch 60.
- the arbiters 21 define the destination of each frame portion by the channel and switch of the destination workstation.
- the switch controller 28 of each network switch 60 listens to all of the traffic on the internal bus 24 but only transfers into its storage buffer 26 those frame portions which are to be output to its associated channels 10.
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Small-Scale Networks (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP95930157A EP0775346A4 (fr) | 1994-08-14 | 1995-08-11 | Commutateur de reseau |
AU33639/95A AU3363995A (en) | 1994-08-14 | 1995-08-11 | A network switch |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IL110657 | 1994-08-14 | ||
IL110657A IL110657A (en) | 1994-08-14 | 1994-08-14 | Network switch |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1996005558A1 true WO1996005558A1 (fr) | 1996-02-22 |
Family
ID=11066456
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1995/010256 WO1996005558A1 (fr) | 1994-08-14 | 1995-08-11 | Commutateur de reseau |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0775346A4 (fr) |
AU (1) | AU3363995A (fr) |
IL (1) | IL110657A (fr) |
WO (1) | WO1996005558A1 (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0855819A1 (fr) * | 1997-01-22 | 1998-07-29 | Hewlett-Packard Company | Dispositif d'empilementde communateurs de réseau |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5241536A (en) * | 1991-10-03 | 1993-08-31 | Northern Telecom Limited | Broadband input buffered atm switch |
US5274631A (en) * | 1991-03-11 | 1993-12-28 | Kalpana, Inc. | Computer network switching system |
US5291482A (en) * | 1992-07-24 | 1994-03-01 | At&T Bell Laboratories | High bandwidth packet switch |
US5311509A (en) * | 1991-09-13 | 1994-05-10 | International Business Machines Corporation | Configurable gigabits switch adapter |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4788679A (en) * | 1986-09-02 | 1988-11-29 | Nippon Telegraph And Telephone Corporation | Packet switch with variable data transfer rate links |
EP0312628B1 (fr) * | 1987-10-20 | 1993-12-29 | International Business Machines Corporation | Dispositif modulaire de commutation à grande vitesse pour le trafic en mode circuit et paquet |
US5168492A (en) * | 1991-04-11 | 1992-12-01 | Northern Telecom Limited | Rotating-access ATM-STM packet switch |
-
1994
- 1994-08-14 IL IL110657A patent/IL110657A/xx not_active IP Right Cessation
-
1995
- 1995-08-11 EP EP95930157A patent/EP0775346A4/fr not_active Withdrawn
- 1995-08-11 AU AU33639/95A patent/AU3363995A/en not_active Abandoned
- 1995-08-11 WO PCT/US1995/010256 patent/WO1996005558A1/fr not_active Application Discontinuation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5274631A (en) * | 1991-03-11 | 1993-12-28 | Kalpana, Inc. | Computer network switching system |
US5311509A (en) * | 1991-09-13 | 1994-05-10 | International Business Machines Corporation | Configurable gigabits switch adapter |
US5241536A (en) * | 1991-10-03 | 1993-08-31 | Northern Telecom Limited | Broadband input buffered atm switch |
US5291482A (en) * | 1992-07-24 | 1994-03-01 | At&T Bell Laboratories | High bandwidth packet switch |
Non-Patent Citations (1)
Title |
---|
See also references of EP0775346A4 * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0855819A1 (fr) * | 1997-01-22 | 1998-07-29 | Hewlett-Packard Company | Dispositif d'empilementde communateurs de réseau |
Also Published As
Publication number | Publication date |
---|---|
IL110657A0 (en) | 1994-11-11 |
EP0775346A4 (fr) | 1999-09-22 |
EP0775346A1 (fr) | 1997-05-28 |
IL110657A (en) | 1997-07-13 |
AU3363995A (en) | 1996-03-07 |
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