[go: up one dir, main page]

WO1996008767A3 - Microcontroller system with a multiple-register stacking instruction - Google Patents

Microcontroller system with a multiple-register stacking instruction Download PDF

Info

Publication number
WO1996008767A3
WO1996008767A3 PCT/IB1995/000677 IB9500677W WO9608767A3 WO 1996008767 A3 WO1996008767 A3 WO 1996008767A3 IB 9500677 W IB9500677 W IB 9500677W WO 9608767 A3 WO9608767 A3 WO 9608767A3
Authority
WO
WIPO (PCT)
Prior art keywords
microcontroller system
transfer
instruction
stacking instruction
register
Prior art date
Application number
PCT/IB1995/000677
Other languages
French (fr)
Other versions
WO1996008767A2 (en
Inventor
Farrell Ostler
Neil Birns
Ori Mizrahi-Shalom
Original Assignee
Philips Electronics Nv
Philips Norden Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics Nv, Philips Norden Ab filed Critical Philips Electronics Nv
Publication of WO1996008767A2 publication Critical patent/WO1996008767A2/en
Publication of WO1996008767A3 publication Critical patent/WO1996008767A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

A microcontroller system transfers data between a memory stack and a plurality of general-purpose registers listed in an instruction in a single instruction cycle. An address generation circuit automatically generates register addresses only for those registers involved in the transfer. The stack pointer is modified or updated for each transfer.
PCT/IB1995/000677 1994-09-16 1995-08-22 Microcontroller system with a multiple-register stacking instruction WO1996008767A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US30804994A 1994-09-16 1994-09-16
US08/308,049 1994-09-16

Publications (2)

Publication Number Publication Date
WO1996008767A2 WO1996008767A2 (en) 1996-03-21
WO1996008767A3 true WO1996008767A3 (en) 1996-05-30

Family

ID=23192319

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB1995/000677 WO1996008767A2 (en) 1994-09-16 1995-08-22 Microcontroller system with a multiple-register stacking instruction

Country Status (1)

Country Link
WO (1) WO1996008767A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2889845B2 (en) * 1995-09-22 1999-05-10 松下電器産業株式会社 Information processing device
JPH1091443A (en) 1996-05-22 1998-04-10 Seiko Epson Corp Information processing circuit, microcomputer and electronic equipment
US5913054A (en) * 1996-12-16 1999-06-15 International Business Machines Corporation Method and system for processing a multiple-register instruction that permit multiple data words to be written in a single processor cycle
JP2001236206A (en) * 1999-10-01 2001-08-31 Hitachi Ltd Data loading method and storage method, data word loading method and storage method, and floating-point comparison method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3614741A (en) * 1970-03-23 1971-10-19 Digital Equipment Corp Data processing system with instruction addresses identifying one of a plurality of registers including the program counter
US4334269A (en) * 1978-11-20 1982-06-08 Panafacom Limited Data processing system having an integrated stack and register machine architecture

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3614741A (en) * 1970-03-23 1971-10-19 Digital Equipment Corp Data processing system with instruction addresses identifying one of a plurality of registers including the program counter
US4334269A (en) * 1978-11-20 1982-06-08 Panafacom Limited Data processing system having an integrated stack and register machine architecture

Also Published As

Publication number Publication date
WO1996008767A2 (en) 1996-03-21

Similar Documents

Publication Publication Date Title
KR950008226B1 (en) Bus master with burst transfer mode
EP0889401A3 (en) Interpreter generation and implementation utilizing interpreter states and register caching
WO1996006390A3 (en) A two-way set-associative cache memory
TR28547A (en) Reverse transfer processor with memory address circuit.
MY116707A (en) Coprocessor data access control
EP0735463A3 (en) Computer processor having a register file with reduced read and/or write port bandwidth
WO2000038060A3 (en) Interrupt/software-controlled thread processing
GB2345170A (en) Memory transactions on a low pin count bus
CA2138263A1 (en) Multiprocessor
WO1999014663A3 (en) Data processing unit with digital signal processing capabilities
DE69509804D1 (en) DATA PACKAGE TRANSFER IN CODEMULTIPLEX MULTIPLE ACCESS SYSTEMS
CA2145106A1 (en) Intelligent Memory-Based Input/Output System
GB2263378B (en) Computer bus with virtual memory data transfer capability using virtual address/data lines
CA2319726A1 (en) Interleaving/deinterleaving device and method for communication system
EP0388300A3 (en) Controller for direct memory access
WO1996008767A3 (en) Microcontroller system with a multiple-register stacking instruction
KR850700079A (en) Micro with internal address mapper
CA2116284A1 (en) Parallel Data Transfer Circuit
CA2215844A1 (en) Multiprocessing system with address mapping
EP0256134A4 (en) Central processing unit.
TW364979B (en) Program execution method and program execution device
CA2027740A1 (en) Electronic device with data transmission function
JPH03260750A (en) DMA transfer method
JPS5563422A (en) Data transfer system
EP0208458A3 (en) A data stack for data processors

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP KR

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

WWE Wipo information: entry into national phase

Ref document number: 1995927072

Country of ref document: EP

AK Designated states

Kind code of ref document: A3

Designated state(s): JP KR

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

WWW Wipo information: withdrawn in national office

Ref document number: 1995927072

Country of ref document: EP

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase